1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef __AMD_SHARED_H__ 24 #define __AMD_SHARED_H__ 25 26 #include <drm/amd_asic_type.h> 27 28 29 #define AMD_MAX_USEC_TIMEOUT 1000000 /* 1000 ms */ 30 31 /* 32 * Chip flags 33 */ 34 enum amd_chip_flags { 35 AMD_ASIC_MASK = 0x0000ffffUL, 36 AMD_FLAGS_MASK = 0xffff0000UL, 37 AMD_IS_MOBILITY = 0x00010000UL, 38 AMD_IS_APU = 0x00020000UL, 39 AMD_IS_PX = 0x00040000UL, 40 AMD_EXP_HW_SUPPORT = 0x00080000UL, 41 }; 42 43 enum amd_apu_flags { 44 AMD_APU_IS_RAVEN = 0x00000001UL, 45 AMD_APU_IS_RAVEN2 = 0x00000002UL, 46 AMD_APU_IS_PICASSO = 0x00000004UL, 47 AMD_APU_IS_RENOIR = 0x00000008UL, 48 AMD_APU_IS_GREEN_SARDINE = 0x00000010UL, 49 AMD_APU_IS_VANGOGH = 0x00000020UL, 50 AMD_APU_IS_CYAN_SKILLFISH2 = 0x00000040UL, 51 }; 52 53 /** 54 * DOC: IP Blocks 55 * 56 * GPUs are composed of IP (intellectual property) blocks. These 57 * IP blocks provide various functionalities: display, graphics, 58 * video decode, etc. The IP blocks that comprise a particular GPU 59 * are listed in the GPU's respective SoC file. amdgpu_device.c 60 * acquires the list of IP blocks for the GPU in use on initialization. 61 * It can then operate on this list to perform standard driver operations 62 * such as: init, fini, suspend, resume, etc. 63 * 64 * 65 * IP block implementations are named using the following convention: 66 * <functionality>_v<version> (E.g.: gfx_v6_0). 67 */ 68 69 /** 70 * enum amd_ip_block_type - Used to classify IP blocks by functionality. 71 * 72 * @AMD_IP_BLOCK_TYPE_COMMON: GPU Family 73 * @AMD_IP_BLOCK_TYPE_GMC: Graphics Memory Controller 74 * @AMD_IP_BLOCK_TYPE_IH: Interrupt Handler 75 * @AMD_IP_BLOCK_TYPE_SMC: System Management Controller 76 * @AMD_IP_BLOCK_TYPE_PSP: Platform Security Processor 77 * @AMD_IP_BLOCK_TYPE_DCE: Display and Compositing Engine 78 * @AMD_IP_BLOCK_TYPE_GFX: Graphics and Compute Engine 79 * @AMD_IP_BLOCK_TYPE_SDMA: System DMA Engine 80 * @AMD_IP_BLOCK_TYPE_UVD: Unified Video Decoder 81 * @AMD_IP_BLOCK_TYPE_VCE: Video Compression Engine 82 * @AMD_IP_BLOCK_TYPE_ACP: Audio Co-Processor 83 * @AMD_IP_BLOCK_TYPE_VCN: Video Core/Codec Next 84 * @AMD_IP_BLOCK_TYPE_MES: Micro-Engine Scheduler 85 * @AMD_IP_BLOCK_TYPE_JPEG: JPEG Engine 86 */ 87 enum amd_ip_block_type { 88 AMD_IP_BLOCK_TYPE_COMMON, 89 AMD_IP_BLOCK_TYPE_GMC, 90 AMD_IP_BLOCK_TYPE_IH, 91 AMD_IP_BLOCK_TYPE_SMC, 92 AMD_IP_BLOCK_TYPE_PSP, 93 AMD_IP_BLOCK_TYPE_DCE, 94 AMD_IP_BLOCK_TYPE_GFX, 95 AMD_IP_BLOCK_TYPE_SDMA, 96 AMD_IP_BLOCK_TYPE_UVD, 97 AMD_IP_BLOCK_TYPE_VCE, 98 AMD_IP_BLOCK_TYPE_ACP, 99 AMD_IP_BLOCK_TYPE_VCN, 100 AMD_IP_BLOCK_TYPE_MES, 101 AMD_IP_BLOCK_TYPE_JPEG 102 }; 103 104 enum amd_clockgating_state { 105 AMD_CG_STATE_GATE = 0, 106 AMD_CG_STATE_UNGATE, 107 }; 108 109 110 enum amd_powergating_state { 111 AMD_PG_STATE_GATE = 0, 112 AMD_PG_STATE_UNGATE, 113 }; 114 115 116 /* CG flags */ 117 #define AMD_CG_SUPPORT_GFX_MGCG (1 << 0) 118 #define AMD_CG_SUPPORT_GFX_MGLS (1 << 1) 119 #define AMD_CG_SUPPORT_GFX_CGCG (1 << 2) 120 #define AMD_CG_SUPPORT_GFX_CGLS (1 << 3) 121 #define AMD_CG_SUPPORT_GFX_CGTS (1 << 4) 122 #define AMD_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 123 #define AMD_CG_SUPPORT_GFX_CP_LS (1 << 6) 124 #define AMD_CG_SUPPORT_GFX_RLC_LS (1 << 7) 125 #define AMD_CG_SUPPORT_MC_LS (1 << 8) 126 #define AMD_CG_SUPPORT_MC_MGCG (1 << 9) 127 #define AMD_CG_SUPPORT_SDMA_LS (1 << 10) 128 #define AMD_CG_SUPPORT_SDMA_MGCG (1 << 11) 129 #define AMD_CG_SUPPORT_BIF_LS (1 << 12) 130 #define AMD_CG_SUPPORT_UVD_MGCG (1 << 13) 131 #define AMD_CG_SUPPORT_VCE_MGCG (1 << 14) 132 #define AMD_CG_SUPPORT_HDP_LS (1 << 15) 133 #define AMD_CG_SUPPORT_HDP_MGCG (1 << 16) 134 #define AMD_CG_SUPPORT_ROM_MGCG (1 << 17) 135 #define AMD_CG_SUPPORT_DRM_LS (1 << 18) 136 #define AMD_CG_SUPPORT_BIF_MGCG (1 << 19) 137 #define AMD_CG_SUPPORT_GFX_3D_CGCG (1 << 20) 138 #define AMD_CG_SUPPORT_GFX_3D_CGLS (1 << 21) 139 #define AMD_CG_SUPPORT_DRM_MGCG (1 << 22) 140 #define AMD_CG_SUPPORT_DF_MGCG (1 << 23) 141 #define AMD_CG_SUPPORT_VCN_MGCG (1 << 24) 142 #define AMD_CG_SUPPORT_HDP_DS (1 << 25) 143 #define AMD_CG_SUPPORT_HDP_SD (1 << 26) 144 #define AMD_CG_SUPPORT_IH_CG (1 << 27) 145 #define AMD_CG_SUPPORT_ATHUB_LS (1 << 28) 146 #define AMD_CG_SUPPORT_ATHUB_MGCG (1 << 29) 147 #define AMD_CG_SUPPORT_JPEG_MGCG (1 << 30) 148 #define AMD_CG_SUPPORT_GFX_FGCG (1 << 31) 149 /* PG flags */ 150 #define AMD_PG_SUPPORT_GFX_PG (1 << 0) 151 #define AMD_PG_SUPPORT_GFX_SMG (1 << 1) 152 #define AMD_PG_SUPPORT_GFX_DMG (1 << 2) 153 #define AMD_PG_SUPPORT_UVD (1 << 3) 154 #define AMD_PG_SUPPORT_VCE (1 << 4) 155 #define AMD_PG_SUPPORT_CP (1 << 5) 156 #define AMD_PG_SUPPORT_GDS (1 << 6) 157 #define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7) 158 #define AMD_PG_SUPPORT_SDMA (1 << 8) 159 #define AMD_PG_SUPPORT_ACP (1 << 9) 160 #define AMD_PG_SUPPORT_SAMU (1 << 10) 161 #define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11) 162 #define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12) 163 #define AMD_PG_SUPPORT_MMHUB (1 << 13) 164 #define AMD_PG_SUPPORT_VCN (1 << 14) 165 #define AMD_PG_SUPPORT_VCN_DPG (1 << 15) 166 #define AMD_PG_SUPPORT_ATHUB (1 << 16) 167 #define AMD_PG_SUPPORT_JPEG (1 << 17) 168 169 /** 170 * enum PP_FEATURE_MASK - Used to mask power play features. 171 * 172 * @PP_SCLK_DPM_MASK: Dynamic adjustment of the system (graphics) clock. 173 * @PP_MCLK_DPM_MASK: Dynamic adjustment of the memory clock. 174 * @PP_PCIE_DPM_MASK: Dynamic adjustment of PCIE clocks and lanes. 175 * @PP_SCLK_DEEP_SLEEP_MASK: System (graphics) clock deep sleep. 176 * @PP_POWER_CONTAINMENT_MASK: Power containment. 177 * @PP_UVD_HANDSHAKE_MASK: Unified video decoder handshake. 178 * @PP_SMC_VOLTAGE_CONTROL_MASK: Dynamic voltage control. 179 * @PP_VBI_TIME_SUPPORT_MASK: Vertical blank interval support. 180 * @PP_ULV_MASK: Ultra low voltage. 181 * @PP_ENABLE_GFX_CG_THRU_SMU: SMU control of GFX engine clockgating. 182 * @PP_CLOCK_STRETCH_MASK: Clock stretching. 183 * @PP_OD_FUZZY_FAN_CONTROL_MASK: Overdrive fuzzy fan control. 184 * @PP_SOCCLK_DPM_MASK: Dynamic adjustment of the SoC clock. 185 * @PP_DCEFCLK_DPM_MASK: Dynamic adjustment of the Display Controller Engine Fabric clock. 186 * @PP_OVERDRIVE_MASK: Over- and under-clocking support. 187 * @PP_GFXOFF_MASK: Dynamic graphics engine power control. 188 * @PP_ACG_MASK: Adaptive clock generator. 189 * @PP_STUTTER_MODE: Stutter mode. 190 * @PP_AVFS_MASK: Adaptive voltage and frequency scaling. 191 * 192 * To override these settings on boot, append amdgpu.ppfeaturemask=<mask> to 193 * the kernel's command line parameters. This is usually done through a system's 194 * boot loader (E.g. GRUB). If manually loading the driver, pass 195 * ppfeaturemask=<mask> as a modprobe parameter. 196 */ 197 enum PP_FEATURE_MASK { 198 PP_SCLK_DPM_MASK = 0x1, 199 PP_MCLK_DPM_MASK = 0x2, 200 PP_PCIE_DPM_MASK = 0x4, 201 PP_SCLK_DEEP_SLEEP_MASK = 0x8, 202 PP_POWER_CONTAINMENT_MASK = 0x10, 203 PP_UVD_HANDSHAKE_MASK = 0x20, 204 PP_SMC_VOLTAGE_CONTROL_MASK = 0x40, 205 PP_VBI_TIME_SUPPORT_MASK = 0x80, 206 PP_ULV_MASK = 0x100, 207 PP_ENABLE_GFX_CG_THRU_SMU = 0x200, 208 PP_CLOCK_STRETCH_MASK = 0x400, 209 PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800, 210 PP_SOCCLK_DPM_MASK = 0x1000, 211 PP_DCEFCLK_DPM_MASK = 0x2000, 212 PP_OVERDRIVE_MASK = 0x4000, 213 PP_GFXOFF_MASK = 0x8000, 214 PP_ACG_MASK = 0x10000, 215 PP_STUTTER_MODE = 0x20000, 216 PP_AVFS_MASK = 0x40000, 217 PP_GFX_DCS_MASK = 0x80000, 218 }; 219 220 enum amd_harvest_ip_mask { 221 AMD_HARVEST_IP_VCN_MASK = 0x1, 222 AMD_HARVEST_IP_JPEG_MASK = 0x2, 223 AMD_HARVEST_IP_DMU_MASK = 0x4, 224 }; 225 226 enum DC_FEATURE_MASK { 227 //Default value can be found at "uint amdgpu_dc_feature_mask" 228 DC_FBC_MASK = (1 << 0), //0x1, disabled by default 229 DC_MULTI_MON_PP_MCLK_SWITCH_MASK = (1 << 1), //0x2, enabled by default 230 DC_DISABLE_FRACTIONAL_PWM_MASK = (1 << 2), //0x4, disabled by default 231 DC_PSR_MASK = (1 << 3), //0x8, disabled by default 232 DC_EDP_NO_POWER_SEQUENCING = (1 << 4), //0x10, disabled by default 233 }; 234 235 enum DC_DEBUG_MASK { 236 DC_DISABLE_PIPE_SPLIT = 0x1, 237 DC_DISABLE_STUTTER = 0x2, 238 DC_DISABLE_DSC = 0x4, 239 DC_DISABLE_CLOCK_GATING = 0x8 240 }; 241 242 enum amd_dpm_forced_level; 243 244 /** 245 * struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks 246 * @name: Name of IP block 247 * @early_init: sets up early driver state (pre sw_init), 248 * does not configure hw - Optional 249 * @late_init: sets up late driver/hw state (post hw_init) - Optional 250 * @sw_init: sets up driver state, does not configure hw 251 * @sw_fini: tears down driver state, does not configure hw 252 * @early_fini: tears down stuff before dev detached from driver 253 * @hw_init: sets up the hw state 254 * @hw_fini: tears down the hw state 255 * @late_fini: final cleanup 256 * @suspend: handles IP specific hw/sw changes for suspend 257 * @resume: handles IP specific hw/sw changes for resume 258 * @is_idle: returns current IP block idle status 259 * @wait_for_idle: poll for idle 260 * @check_soft_reset: check soft reset the IP block 261 * @pre_soft_reset: pre soft reset the IP block 262 * @soft_reset: soft reset the IP block 263 * @post_soft_reset: post soft reset the IP block 264 * @set_clockgating_state: enable/disable cg for the IP block 265 * @set_powergating_state: enable/disable pg for the IP block 266 * @get_clockgating_state: get current clockgating status 267 * @enable_umd_pstate: enable UMD powerstate 268 * 269 * These hooks provide an interface for controlling the operational state 270 * of IP blocks. After acquiring a list of IP blocks for the GPU in use, 271 * the driver can make chip-wide state changes by walking this list and 272 * making calls to hooks from each IP block. This list is ordered to ensure 273 * that the driver initializes the IP blocks in a safe sequence. 274 */ 275 struct amd_ip_funcs { 276 char *name; 277 int (*early_init)(void *handle); 278 int (*late_init)(void *handle); 279 int (*sw_init)(void *handle); 280 int (*sw_fini)(void *handle); 281 int (*early_fini)(void *handle); 282 int (*hw_init)(void *handle); 283 int (*hw_fini)(void *handle); 284 void (*late_fini)(void *handle); 285 int (*suspend)(void *handle); 286 int (*resume)(void *handle); 287 bool (*is_idle)(void *handle); 288 int (*wait_for_idle)(void *handle); 289 bool (*check_soft_reset)(void *handle); 290 int (*pre_soft_reset)(void *handle); 291 int (*soft_reset)(void *handle); 292 int (*post_soft_reset)(void *handle); 293 int (*set_clockgating_state)(void *handle, 294 enum amd_clockgating_state state); 295 int (*set_powergating_state)(void *handle, 296 enum amd_powergating_state state); 297 void (*get_clockgating_state)(void *handle, u32 *flags); 298 int (*enable_umd_pstate)(void *handle, enum amd_dpm_forced_level *level); 299 }; 300 301 302 #endif /* __AMD_SHARED_H__ */ 303
