1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Christian König <christian.koenig@amd.com>
23 */
24
25 #include <linux/firmware.h>
26 #include <drm/drmP.h>
27 #include "amdgpu.h"
28 #include "amdgpu_uvd.h"
29 #include "vid.h"
30 #include "uvd/uvd_6_0_d.h"
31 #include "uvd/uvd_6_0_sh_mask.h"
32 #include "oss/oss_2_0_d.h"
33 #include "oss/oss_2_0_sh_mask.h"
34 #include "smu/smu_7_1_3_d.h"
35 #include "smu/smu_7_1_3_sh_mask.h"
36 #include "bif/bif_5_1_d.h"
37 #include "gmc/gmc_8_1_d.h"
38 #include "vi.h"
39 #include "ivsrcid/ivsrcid_vislands30.h"
40
41 /* Polaris10/11/12 firmware version */
42 #define FW_1_130_16 ((1 << 24) | (130 << 16) | (16 << 8))
43
44 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
45 static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev);
46
47 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
48 static int uvd_v6_0_start(struct amdgpu_device *adev);
49 static void uvd_v6_0_stop(struct amdgpu_device *adev);
50 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev);
51 static int uvd_v6_0_set_clockgating_state(void *handle,
52 enum amd_clockgating_state state);
53 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
54 bool enable);
55
56 /**
57 * uvd_v6_0_enc_support - get encode support status
58 *
59 * @adev: amdgpu_device pointer
60 *
61 * Returns the current hardware encode support status
62 */
uvd_v6_0_enc_support(struct amdgpu_device * adev)63 static inline bool uvd_v6_0_enc_support(struct amdgpu_device *adev)
64 {
65 return ((adev->asic_type >= CHIP_POLARIS10) &&
66 (adev->asic_type <= CHIP_VEGAM) &&
67 (!adev->uvd.fw_version || adev->uvd.fw_version >= FW_1_130_16));
68 }
69
70 /**
71 * uvd_v6_0_ring_get_rptr - get read pointer
72 *
73 * @ring: amdgpu_ring pointer
74 *
75 * Returns the current hardware read pointer
76 */
uvd_v6_0_ring_get_rptr(struct amdgpu_ring * ring)77 static uint64_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
78 {
79 struct amdgpu_device *adev = ring->adev;
80
81 return RREG32(mmUVD_RBC_RB_RPTR);
82 }
83
84 /**
85 * uvd_v6_0_enc_ring_get_rptr - get enc read pointer
86 *
87 * @ring: amdgpu_ring pointer
88 *
89 * Returns the current hardware enc read pointer
90 */
uvd_v6_0_enc_ring_get_rptr(struct amdgpu_ring * ring)91 static uint64_t uvd_v6_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
92 {
93 struct amdgpu_device *adev = ring->adev;
94
95 if (ring == &adev->uvd.inst->ring_enc[0])
96 return RREG32(mmUVD_RB_RPTR);
97 else
98 return RREG32(mmUVD_RB_RPTR2);
99 }
100 /**
101 * uvd_v6_0_ring_get_wptr - get write pointer
102 *
103 * @ring: amdgpu_ring pointer
104 *
105 * Returns the current hardware write pointer
106 */
uvd_v6_0_ring_get_wptr(struct amdgpu_ring * ring)107 static uint64_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
108 {
109 struct amdgpu_device *adev = ring->adev;
110
111 return RREG32(mmUVD_RBC_RB_WPTR);
112 }
113
114 /**
115 * uvd_v6_0_enc_ring_get_wptr - get enc write pointer
116 *
117 * @ring: amdgpu_ring pointer
118 *
119 * Returns the current hardware enc write pointer
120 */
uvd_v6_0_enc_ring_get_wptr(struct amdgpu_ring * ring)121 static uint64_t uvd_v6_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
122 {
123 struct amdgpu_device *adev = ring->adev;
124
125 if (ring == &adev->uvd.inst->ring_enc[0])
126 return RREG32(mmUVD_RB_WPTR);
127 else
128 return RREG32(mmUVD_RB_WPTR2);
129 }
130
131 /**
132 * uvd_v6_0_ring_set_wptr - set write pointer
133 *
134 * @ring: amdgpu_ring pointer
135 *
136 * Commits the write pointer to the hardware
137 */
uvd_v6_0_ring_set_wptr(struct amdgpu_ring * ring)138 static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
139 {
140 struct amdgpu_device *adev = ring->adev;
141
142 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
143 }
144
145 /**
146 * uvd_v6_0_enc_ring_set_wptr - set enc write pointer
147 *
148 * @ring: amdgpu_ring pointer
149 *
150 * Commits the enc write pointer to the hardware
151 */
uvd_v6_0_enc_ring_set_wptr(struct amdgpu_ring * ring)152 static void uvd_v6_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
153 {
154 struct amdgpu_device *adev = ring->adev;
155
156 if (ring == &adev->uvd.inst->ring_enc[0])
157 WREG32(mmUVD_RB_WPTR,
158 lower_32_bits(ring->wptr));
159 else
160 WREG32(mmUVD_RB_WPTR2,
161 lower_32_bits(ring->wptr));
162 }
163
164 /**
165 * uvd_v6_0_enc_ring_test_ring - test if UVD ENC ring is working
166 *
167 * @ring: the engine to test on
168 *
169 */
uvd_v6_0_enc_ring_test_ring(struct amdgpu_ring * ring)170 static int uvd_v6_0_enc_ring_test_ring(struct amdgpu_ring *ring)
171 {
172 struct amdgpu_device *adev = ring->adev;
173 uint32_t rptr = amdgpu_ring_get_rptr(ring);
174 unsigned i;
175 int r;
176
177 r = amdgpu_ring_alloc(ring, 16);
178 if (r) {
179 DRM_ERROR("amdgpu: uvd enc failed to lock ring %d (%d).\n",
180 ring->idx, r);
181 return r;
182 }
183 amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
184 amdgpu_ring_commit(ring);
185
186 for (i = 0; i < adev->usec_timeout; i++) {
187 if (amdgpu_ring_get_rptr(ring) != rptr)
188 break;
189 DRM_UDELAY(1);
190 }
191
192 if (i < adev->usec_timeout) {
193 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
194 ring->idx, i);
195 } else {
196 DRM_ERROR("amdgpu: ring %d test failed\n",
197 ring->idx);
198 r = -ETIMEDOUT;
199 }
200
201 return r;
202 }
203
204 /**
205 * uvd_v6_0_enc_get_create_msg - generate a UVD ENC create msg
206 *
207 * @adev: amdgpu_device pointer
208 * @ring: ring we should submit the msg to
209 * @handle: session handle to use
210 * @fence: optional fence to return
211 *
212 * Open up a stream for HW test
213 */
uvd_v6_0_enc_get_create_msg(struct amdgpu_ring * ring,uint32_t handle,struct dma_fence ** fence)214 static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
215 struct dma_fence **fence)
216 {
217 const unsigned ib_size_dw = 16;
218 struct amdgpu_job *job;
219 struct amdgpu_ib *ib;
220 struct dma_fence *f = NULL;
221 uint64_t dummy;
222 int i, r;
223
224 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
225 if (r)
226 return r;
227
228 ib = &job->ibs[0];
229 dummy = ib->gpu_addr + 1024;
230
231 ib->length_dw = 0;
232 ib->ptr[ib->length_dw++] = 0x00000018;
233 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
234 ib->ptr[ib->length_dw++] = handle;
235 ib->ptr[ib->length_dw++] = 0x00010000;
236 ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
237 ib->ptr[ib->length_dw++] = dummy;
238
239 ib->ptr[ib->length_dw++] = 0x00000014;
240 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
241 ib->ptr[ib->length_dw++] = 0x0000001c;
242 ib->ptr[ib->length_dw++] = 0x00000001;
243 ib->ptr[ib->length_dw++] = 0x00000000;
244
245 ib->ptr[ib->length_dw++] = 0x00000008;
246 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
247
248 for (i = ib->length_dw; i < ib_size_dw; ++i)
249 ib->ptr[i] = 0x0;
250
251 r = amdgpu_job_submit_direct(job, ring, &f);
252 if (r)
253 goto err;
254
255 if (fence)
256 *fence = dma_fence_get(f);
257 dma_fence_put(f);
258 return 0;
259
260 err:
261 amdgpu_job_free(job);
262 return r;
263 }
264
265 /**
266 * uvd_v6_0_enc_get_destroy_msg - generate a UVD ENC destroy msg
267 *
268 * @adev: amdgpu_device pointer
269 * @ring: ring we should submit the msg to
270 * @handle: session handle to use
271 * @fence: optional fence to return
272 *
273 * Close up a stream for HW test or if userspace failed to do so
274 */
uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring * ring,uint32_t handle,bool direct,struct dma_fence ** fence)275 static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring,
276 uint32_t handle,
277 bool direct, struct dma_fence **fence)
278 {
279 const unsigned ib_size_dw = 16;
280 struct amdgpu_job *job;
281 struct amdgpu_ib *ib;
282 struct dma_fence *f = NULL;
283 uint64_t dummy;
284 int i, r;
285
286 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
287 if (r)
288 return r;
289
290 ib = &job->ibs[0];
291 dummy = ib->gpu_addr + 1024;
292
293 ib->length_dw = 0;
294 ib->ptr[ib->length_dw++] = 0x00000018;
295 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
296 ib->ptr[ib->length_dw++] = handle;
297 ib->ptr[ib->length_dw++] = 0x00010000;
298 ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
299 ib->ptr[ib->length_dw++] = dummy;
300
301 ib->ptr[ib->length_dw++] = 0x00000014;
302 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
303 ib->ptr[ib->length_dw++] = 0x0000001c;
304 ib->ptr[ib->length_dw++] = 0x00000001;
305 ib->ptr[ib->length_dw++] = 0x00000000;
306
307 ib->ptr[ib->length_dw++] = 0x00000008;
308 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
309
310 for (i = ib->length_dw; i < ib_size_dw; ++i)
311 ib->ptr[i] = 0x0;
312
313 if (direct)
314 r = amdgpu_job_submit_direct(job, ring, &f);
315 else
316 r = amdgpu_job_submit(job, &ring->adev->vce.entity,
317 AMDGPU_FENCE_OWNER_UNDEFINED, &f);
318 if (r)
319 goto err;
320
321 if (fence)
322 *fence = dma_fence_get(f);
323 dma_fence_put(f);
324 return 0;
325
326 err:
327 amdgpu_job_free(job);
328 return r;
329 }
330
331 /**
332 * uvd_v6_0_enc_ring_test_ib - test if UVD ENC IBs are working
333 *
334 * @ring: the engine to test on
335 *
336 */
uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring * ring,long timeout)337 static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
338 {
339 struct dma_fence *fence = NULL;
340 long r;
341
342 r = uvd_v6_0_enc_get_create_msg(ring, 1, NULL);
343 if (r) {
344 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
345 goto error;
346 }
347
348 r = uvd_v6_0_enc_get_destroy_msg(ring, 1, true, &fence);
349 if (r) {
350 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
351 goto error;
352 }
353
354 r = dma_fence_wait_timeout(fence, false, timeout);
355 if (r == 0) {
356 DRM_ERROR("amdgpu: IB test timed out.\n");
357 r = -ETIMEDOUT;
358 } else if (r < 0) {
359 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
360 } else {
361 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
362 r = 0;
363 }
364 error:
365 dma_fence_put(fence);
366 return r;
367 }
uvd_v6_0_early_init(void * handle)368 static int uvd_v6_0_early_init(void *handle)
369 {
370 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
371 adev->uvd.num_uvd_inst = 1;
372
373 if (!(adev->flags & AMD_IS_APU) &&
374 (RREG32_SMC(ixCC_HARVEST_FUSES) & CC_HARVEST_FUSES__UVD_DISABLE_MASK))
375 return -ENOENT;
376
377 uvd_v6_0_set_ring_funcs(adev);
378
379 if (uvd_v6_0_enc_support(adev)) {
380 adev->uvd.num_enc_rings = 2;
381 uvd_v6_0_set_enc_ring_funcs(adev);
382 }
383
384 uvd_v6_0_set_irq_funcs(adev);
385
386 return 0;
387 }
388
uvd_v6_0_sw_init(void * handle)389 static int uvd_v6_0_sw_init(void *handle)
390 {
391 struct amdgpu_ring *ring;
392 int i, r;
393 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
394
395 /* UVD TRAP */
396 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
397 if (r)
398 return r;
399
400 /* UVD ENC TRAP */
401 if (uvd_v6_0_enc_support(adev)) {
402 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
403 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP, &adev->uvd.inst->irq);
404 if (r)
405 return r;
406 }
407 }
408
409 r = amdgpu_uvd_sw_init(adev);
410 if (r)
411 return r;
412
413 if (!uvd_v6_0_enc_support(adev)) {
414 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
415 adev->uvd.inst->ring_enc[i].funcs = NULL;
416
417 adev->uvd.inst->irq.num_types = 1;
418 adev->uvd.num_enc_rings = 0;
419
420 DRM_INFO("UVD ENC is disabled\n");
421 }
422
423 r = amdgpu_uvd_resume(adev);
424 if (r)
425 return r;
426
427 ring = &adev->uvd.inst->ring;
428 sprintf(ring->name, "uvd");
429 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);
430 if (r)
431 return r;
432
433 if (uvd_v6_0_enc_support(adev)) {
434 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
435 ring = &adev->uvd.inst->ring_enc[i];
436 sprintf(ring->name, "uvd_enc%d", i);
437 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);
438 if (r)
439 return r;
440 }
441 }
442
443 r = amdgpu_uvd_entity_init(adev);
444
445 return r;
446 }
447
uvd_v6_0_sw_fini(void * handle)448 static int uvd_v6_0_sw_fini(void *handle)
449 {
450 int i, r;
451 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
452
453 r = amdgpu_uvd_suspend(adev);
454 if (r)
455 return r;
456
457 if (uvd_v6_0_enc_support(adev)) {
458 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
459 amdgpu_ring_fini(&adev->uvd.inst->ring_enc[i]);
460 }
461
462 return amdgpu_uvd_sw_fini(adev);
463 }
464
465 /**
466 * uvd_v6_0_hw_init - start and test UVD block
467 *
468 * @adev: amdgpu_device pointer
469 *
470 * Initialize the hardware, boot up the VCPU and do some testing
471 */
uvd_v6_0_hw_init(void * handle)472 static int uvd_v6_0_hw_init(void *handle)
473 {
474 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
475 struct amdgpu_ring *ring = &adev->uvd.inst->ring;
476 uint32_t tmp;
477 int i, r;
478
479 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
480 uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
481 uvd_v6_0_enable_mgcg(adev, true);
482
483 ring->ready = true;
484 r = amdgpu_ring_test_ring(ring);
485 if (r) {
486 ring->ready = false;
487 goto done;
488 }
489
490 r = amdgpu_ring_alloc(ring, 10);
491 if (r) {
492 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
493 goto done;
494 }
495
496 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
497 amdgpu_ring_write(ring, tmp);
498 amdgpu_ring_write(ring, 0xFFFFF);
499
500 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
501 amdgpu_ring_write(ring, tmp);
502 amdgpu_ring_write(ring, 0xFFFFF);
503
504 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
505 amdgpu_ring_write(ring, tmp);
506 amdgpu_ring_write(ring, 0xFFFFF);
507
508 /* Clear timeout status bits */
509 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
510 amdgpu_ring_write(ring, 0x8);
511
512 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
513 amdgpu_ring_write(ring, 3);
514
515 amdgpu_ring_commit(ring);
516
517 if (uvd_v6_0_enc_support(adev)) {
518 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
519 ring = &adev->uvd.inst->ring_enc[i];
520 ring->ready = true;
521 r = amdgpu_ring_test_ring(ring);
522 if (r) {
523 ring->ready = false;
524 goto done;
525 }
526 }
527 }
528
529 done:
530 if (!r) {
531 if (uvd_v6_0_enc_support(adev))
532 DRM_INFO("UVD and UVD ENC initialized successfully.\n");
533 else
534 DRM_INFO("UVD initialized successfully.\n");
535 }
536
537 return r;
538 }
539
540 /**
541 * uvd_v6_0_hw_fini - stop the hardware block
542 *
543 * @adev: amdgpu_device pointer
544 *
545 * Stop the UVD block, mark ring as not ready any more
546 */
uvd_v6_0_hw_fini(void * handle)547 static int uvd_v6_0_hw_fini(void *handle)
548 {
549 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
550 struct amdgpu_ring *ring = &adev->uvd.inst->ring;
551
552 if (RREG32(mmUVD_STATUS) != 0)
553 uvd_v6_0_stop(adev);
554
555 ring->ready = false;
556
557 return 0;
558 }
559
uvd_v6_0_suspend(void * handle)560 static int uvd_v6_0_suspend(void *handle)
561 {
562 int r;
563 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
564
565 r = uvd_v6_0_hw_fini(adev);
566 if (r)
567 return r;
568
569 return amdgpu_uvd_suspend(adev);
570 }
571
uvd_v6_0_resume(void * handle)572 static int uvd_v6_0_resume(void *handle)
573 {
574 int r;
575 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
576
577 r = amdgpu_uvd_resume(adev);
578 if (r)
579 return r;
580
581 return uvd_v6_0_hw_init(adev);
582 }
583
584 /**
585 * uvd_v6_0_mc_resume - memory controller programming
586 *
587 * @adev: amdgpu_device pointer
588 *
589 * Let the UVD memory controller know it's offsets
590 */
uvd_v6_0_mc_resume(struct amdgpu_device * adev)591 static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
592 {
593 uint64_t offset;
594 uint32_t size;
595
596 /* programm memory controller bits 0-27 */
597 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
598 lower_32_bits(adev->uvd.inst->gpu_addr));
599 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
600 upper_32_bits(adev->uvd.inst->gpu_addr));
601
602 offset = AMDGPU_UVD_FIRMWARE_OFFSET;
603 size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
604 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
605 WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
606
607 offset += size;
608 size = AMDGPU_UVD_HEAP_SIZE;
609 WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
610 WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
611
612 offset += size;
613 size = AMDGPU_UVD_STACK_SIZE +
614 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles);
615 WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
616 WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
617
618 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
619 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
620 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
621
622 WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
623 }
624
625 #if 0
626 static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
627 bool enable)
628 {
629 u32 data, data1;
630
631 data = RREG32(mmUVD_CGC_GATE);
632 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
633 if (enable) {
634 data |= UVD_CGC_GATE__SYS_MASK |
635 UVD_CGC_GATE__UDEC_MASK |
636 UVD_CGC_GATE__MPEG2_MASK |
637 UVD_CGC_GATE__RBC_MASK |
638 UVD_CGC_GATE__LMI_MC_MASK |
639 UVD_CGC_GATE__IDCT_MASK |
640 UVD_CGC_GATE__MPRD_MASK |
641 UVD_CGC_GATE__MPC_MASK |
642 UVD_CGC_GATE__LBSI_MASK |
643 UVD_CGC_GATE__LRBBM_MASK |
644 UVD_CGC_GATE__UDEC_RE_MASK |
645 UVD_CGC_GATE__UDEC_CM_MASK |
646 UVD_CGC_GATE__UDEC_IT_MASK |
647 UVD_CGC_GATE__UDEC_DB_MASK |
648 UVD_CGC_GATE__UDEC_MP_MASK |
649 UVD_CGC_GATE__WCB_MASK |
650 UVD_CGC_GATE__VCPU_MASK |
651 UVD_CGC_GATE__SCPU_MASK;
652 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
653 UVD_SUVD_CGC_GATE__SIT_MASK |
654 UVD_SUVD_CGC_GATE__SMP_MASK |
655 UVD_SUVD_CGC_GATE__SCM_MASK |
656 UVD_SUVD_CGC_GATE__SDB_MASK |
657 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
658 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
659 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
660 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
661 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
662 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
663 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
664 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
665 } else {
666 data &= ~(UVD_CGC_GATE__SYS_MASK |
667 UVD_CGC_GATE__UDEC_MASK |
668 UVD_CGC_GATE__MPEG2_MASK |
669 UVD_CGC_GATE__RBC_MASK |
670 UVD_CGC_GATE__LMI_MC_MASK |
671 UVD_CGC_GATE__LMI_UMC_MASK |
672 UVD_CGC_GATE__IDCT_MASK |
673 UVD_CGC_GATE__MPRD_MASK |
674 UVD_CGC_GATE__MPC_MASK |
675 UVD_CGC_GATE__LBSI_MASK |
676 UVD_CGC_GATE__LRBBM_MASK |
677 UVD_CGC_GATE__UDEC_RE_MASK |
678 UVD_CGC_GATE__UDEC_CM_MASK |
679 UVD_CGC_GATE__UDEC_IT_MASK |
680 UVD_CGC_GATE__UDEC_DB_MASK |
681 UVD_CGC_GATE__UDEC_MP_MASK |
682 UVD_CGC_GATE__WCB_MASK |
683 UVD_CGC_GATE__VCPU_MASK |
684 UVD_CGC_GATE__SCPU_MASK);
685 data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK |
686 UVD_SUVD_CGC_GATE__SIT_MASK |
687 UVD_SUVD_CGC_GATE__SMP_MASK |
688 UVD_SUVD_CGC_GATE__SCM_MASK |
689 UVD_SUVD_CGC_GATE__SDB_MASK |
690 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
691 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
692 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
693 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
694 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
695 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
696 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
697 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK);
698 }
699 WREG32(mmUVD_CGC_GATE, data);
700 WREG32(mmUVD_SUVD_CGC_GATE, data1);
701 }
702 #endif
703
704 /**
705 * uvd_v6_0_start - start UVD block
706 *
707 * @adev: amdgpu_device pointer
708 *
709 * Setup and start the UVD block
710 */
uvd_v6_0_start(struct amdgpu_device * adev)711 static int uvd_v6_0_start(struct amdgpu_device *adev)
712 {
713 struct amdgpu_ring *ring = &adev->uvd.inst->ring;
714 uint32_t rb_bufsz, tmp;
715 uint32_t lmi_swap_cntl;
716 uint32_t mp_swap_cntl;
717 int i, j, r;
718
719 /* disable DPG */
720 WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
721
722 /* disable byte swapping */
723 lmi_swap_cntl = 0;
724 mp_swap_cntl = 0;
725
726 uvd_v6_0_mc_resume(adev);
727
728 /* disable interupt */
729 WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0);
730
731 /* stall UMC and register bus before resetting VCPU */
732 WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 1);
733 mdelay(1);
734
735 /* put LMI, VCPU, RBC etc... into reset */
736 WREG32(mmUVD_SOFT_RESET,
737 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
738 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
739 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
740 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
741 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
742 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
743 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
744 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
745 mdelay(5);
746
747 /* take UVD block out of reset */
748 WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_UVD, 0);
749 mdelay(5);
750
751 /* initialize UVD memory controller */
752 WREG32(mmUVD_LMI_CTRL,
753 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
754 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
755 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
756 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
757 UVD_LMI_CTRL__REQ_MODE_MASK |
758 UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK);
759
760 #ifdef __BIG_ENDIAN
761 /* swap (8 in 32) RB and IB */
762 lmi_swap_cntl = 0xa;
763 mp_swap_cntl = 0;
764 #endif
765 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
766 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
767
768 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
769 WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
770 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
771 WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
772 WREG32(mmUVD_MPC_SET_ALU, 0);
773 WREG32(mmUVD_MPC_SET_MUX, 0x88);
774
775 /* take all subblocks out of reset, except VCPU */
776 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
777 mdelay(5);
778
779 /* enable VCPU clock */
780 WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
781
782 /* enable UMC */
783 WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 0);
784
785 /* boot up the VCPU */
786 WREG32(mmUVD_SOFT_RESET, 0);
787 mdelay(10);
788
789 for (i = 0; i < 10; ++i) {
790 uint32_t status;
791
792 for (j = 0; j < 100; ++j) {
793 status = RREG32(mmUVD_STATUS);
794 if (status & 2)
795 break;
796 mdelay(10);
797 }
798 r = 0;
799 if (status & 2)
800 break;
801
802 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
803 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 1);
804 mdelay(10);
805 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 0);
806 mdelay(10);
807 r = -1;
808 }
809
810 if (r) {
811 DRM_ERROR("UVD not responding, giving up!!!\n");
812 return r;
813 }
814 /* enable master interrupt */
815 WREG32_P(mmUVD_MASTINT_EN,
816 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
817 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
818
819 /* clear the bit 4 of UVD_STATUS */
820 WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
821
822 /* force RBC into idle state */
823 rb_bufsz = order_base_2(ring->ring_size);
824 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
825 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
826 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
827 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
828 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
829 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
830 WREG32(mmUVD_RBC_RB_CNTL, tmp);
831
832 /* set the write pointer delay */
833 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
834
835 /* set the wb address */
836 WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
837
838 /* programm the RB_BASE for ring buffer */
839 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
840 lower_32_bits(ring->gpu_addr));
841 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
842 upper_32_bits(ring->gpu_addr));
843
844 /* Initialize the ring buffer's read and write pointers */
845 WREG32(mmUVD_RBC_RB_RPTR, 0);
846
847 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
848 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
849
850 WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0);
851
852 if (uvd_v6_0_enc_support(adev)) {
853 ring = &adev->uvd.inst->ring_enc[0];
854 WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
855 WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
856 WREG32(mmUVD_RB_BASE_LO, ring->gpu_addr);
857 WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
858 WREG32(mmUVD_RB_SIZE, ring->ring_size / 4);
859
860 ring = &adev->uvd.inst->ring_enc[1];
861 WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
862 WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
863 WREG32(mmUVD_RB_BASE_LO2, ring->gpu_addr);
864 WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
865 WREG32(mmUVD_RB_SIZE2, ring->ring_size / 4);
866 }
867
868 return 0;
869 }
870
871 /**
872 * uvd_v6_0_stop - stop UVD block
873 *
874 * @adev: amdgpu_device pointer
875 *
876 * stop the UVD block
877 */
uvd_v6_0_stop(struct amdgpu_device * adev)878 static void uvd_v6_0_stop(struct amdgpu_device *adev)
879 {
880 /* force RBC into idle state */
881 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
882
883 /* Stall UMC and register bus before resetting VCPU */
884 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
885 mdelay(1);
886
887 /* put VCPU into reset */
888 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
889 mdelay(5);
890
891 /* disable VCPU clock */
892 WREG32(mmUVD_VCPU_CNTL, 0x0);
893
894 /* Unstall UMC and register bus */
895 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
896
897 WREG32(mmUVD_STATUS, 0);
898 }
899
900 /**
901 * uvd_v6_0_ring_emit_fence - emit an fence & trap command
902 *
903 * @ring: amdgpu_ring pointer
904 * @fence: fence to emit
905 *
906 * Write a fence and a trap command to the ring.
907 */
uvd_v6_0_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)908 static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
909 unsigned flags)
910 {
911 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
912
913 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
914 amdgpu_ring_write(ring, seq);
915 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
916 amdgpu_ring_write(ring, addr & 0xffffffff);
917 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
918 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
919 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
920 amdgpu_ring_write(ring, 0);
921
922 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
923 amdgpu_ring_write(ring, 0);
924 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
925 amdgpu_ring_write(ring, 0);
926 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
927 amdgpu_ring_write(ring, 2);
928 }
929
930 /**
931 * uvd_v6_0_enc_ring_emit_fence - emit an enc fence & trap command
932 *
933 * @ring: amdgpu_ring pointer
934 * @fence: fence to emit
935 *
936 * Write enc a fence and a trap command to the ring.
937 */
uvd_v6_0_enc_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)938 static void uvd_v6_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
939 u64 seq, unsigned flags)
940 {
941 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
942
943 amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
944 amdgpu_ring_write(ring, addr);
945 amdgpu_ring_write(ring, upper_32_bits(addr));
946 amdgpu_ring_write(ring, seq);
947 amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
948 }
949
950 /**
951 * uvd_v6_0_ring_emit_hdp_flush - skip HDP flushing
952 *
953 * @ring: amdgpu_ring pointer
954 */
uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring * ring)955 static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
956 {
957 /* The firmware doesn't seem to like touching registers at this point. */
958 }
959
960 /**
961 * uvd_v6_0_ring_test_ring - register write test
962 *
963 * @ring: amdgpu_ring pointer
964 *
965 * Test if we can successfully write to the context register
966 */
uvd_v6_0_ring_test_ring(struct amdgpu_ring * ring)967 static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring)
968 {
969 struct amdgpu_device *adev = ring->adev;
970 uint32_t tmp = 0;
971 unsigned i;
972 int r;
973
974 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
975 r = amdgpu_ring_alloc(ring, 3);
976 if (r) {
977 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
978 ring->idx, r);
979 return r;
980 }
981 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
982 amdgpu_ring_write(ring, 0xDEADBEEF);
983 amdgpu_ring_commit(ring);
984 for (i = 0; i < adev->usec_timeout; i++) {
985 tmp = RREG32(mmUVD_CONTEXT_ID);
986 if (tmp == 0xDEADBEEF)
987 break;
988 DRM_UDELAY(1);
989 }
990
991 if (i < adev->usec_timeout) {
992 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
993 ring->idx, i);
994 } else {
995 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
996 ring->idx, tmp);
997 r = -EINVAL;
998 }
999 return r;
1000 }
1001
1002 /**
1003 * uvd_v6_0_ring_emit_ib - execute indirect buffer
1004 *
1005 * @ring: amdgpu_ring pointer
1006 * @ib: indirect buffer to execute
1007 *
1008 * Write ring commands to execute the indirect buffer
1009 */
uvd_v6_0_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_ib * ib,unsigned vmid,bool ctx_switch)1010 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1011 struct amdgpu_ib *ib,
1012 unsigned vmid, bool ctx_switch)
1013 {
1014 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0));
1015 amdgpu_ring_write(ring, vmid);
1016
1017 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
1018 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1019 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
1020 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1021 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
1022 amdgpu_ring_write(ring, ib->length_dw);
1023 }
1024
1025 /**
1026 * uvd_v6_0_enc_ring_emit_ib - enc execute indirect buffer
1027 *
1028 * @ring: amdgpu_ring pointer
1029 * @ib: indirect buffer to execute
1030 *
1031 * Write enc ring commands to execute the indirect buffer
1032 */
uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_ib * ib,unsigned int vmid,bool ctx_switch)1033 static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1034 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
1035 {
1036 amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
1037 amdgpu_ring_write(ring, vmid);
1038 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1039 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1040 amdgpu_ring_write(ring, ib->length_dw);
1041 }
1042
uvd_v6_0_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1043 static void uvd_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
1044 uint32_t reg, uint32_t val)
1045 {
1046 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1047 amdgpu_ring_write(ring, reg << 2);
1048 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1049 amdgpu_ring_write(ring, val);
1050 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1051 amdgpu_ring_write(ring, 0x8);
1052 }
1053
uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)1054 static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1055 unsigned vmid, uint64_t pd_addr)
1056 {
1057 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1058
1059 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1060 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1061 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1062 amdgpu_ring_write(ring, 0);
1063 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
1064 amdgpu_ring_write(ring, 1 << vmid); /* mask */
1065 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1066 amdgpu_ring_write(ring, 0xC);
1067 }
1068
uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring * ring)1069 static void uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1070 {
1071 uint32_t seq = ring->fence_drv.sync_seq;
1072 uint64_t addr = ring->fence_drv.gpu_addr;
1073
1074 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1075 amdgpu_ring_write(ring, lower_32_bits(addr));
1076 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1077 amdgpu_ring_write(ring, upper_32_bits(addr));
1078 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
1079 amdgpu_ring_write(ring, 0xffffffff); /* mask */
1080 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH9, 0));
1081 amdgpu_ring_write(ring, seq);
1082 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1083 amdgpu_ring_write(ring, 0xE);
1084 }
1085
uvd_v6_0_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)1086 static void uvd_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1087 {
1088 int i;
1089
1090 WARN_ON(ring->wptr % 2 || count % 2);
1091
1092 for (i = 0; i < count / 2; i++) {
1093 amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0));
1094 amdgpu_ring_write(ring, 0);
1095 }
1096 }
1097
uvd_v6_0_enc_ring_emit_pipeline_sync(struct amdgpu_ring * ring)1098 static void uvd_v6_0_enc_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1099 {
1100 uint32_t seq = ring->fence_drv.sync_seq;
1101 uint64_t addr = ring->fence_drv.gpu_addr;
1102
1103 amdgpu_ring_write(ring, HEVC_ENC_CMD_WAIT_GE);
1104 amdgpu_ring_write(ring, lower_32_bits(addr));
1105 amdgpu_ring_write(ring, upper_32_bits(addr));
1106 amdgpu_ring_write(ring, seq);
1107 }
1108
uvd_v6_0_enc_ring_insert_end(struct amdgpu_ring * ring)1109 static void uvd_v6_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1110 {
1111 amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
1112 }
1113
uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned int vmid,uint64_t pd_addr)1114 static void uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1115 unsigned int vmid, uint64_t pd_addr)
1116 {
1117 amdgpu_ring_write(ring, HEVC_ENC_CMD_UPDATE_PTB);
1118 amdgpu_ring_write(ring, vmid);
1119 amdgpu_ring_write(ring, pd_addr >> 12);
1120
1121 amdgpu_ring_write(ring, HEVC_ENC_CMD_FLUSH_TLB);
1122 amdgpu_ring_write(ring, vmid);
1123 }
1124
uvd_v6_0_is_idle(void * handle)1125 static bool uvd_v6_0_is_idle(void *handle)
1126 {
1127 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1128
1129 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
1130 }
1131
uvd_v6_0_wait_for_idle(void * handle)1132 static int uvd_v6_0_wait_for_idle(void *handle)
1133 {
1134 unsigned i;
1135 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1136
1137 for (i = 0; i < adev->usec_timeout; i++) {
1138 if (uvd_v6_0_is_idle(handle))
1139 return 0;
1140 }
1141 return -ETIMEDOUT;
1142 }
1143
1144 #define AMDGPU_UVD_STATUS_BUSY_MASK 0xfd
uvd_v6_0_check_soft_reset(void * handle)1145 static bool uvd_v6_0_check_soft_reset(void *handle)
1146 {
1147 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1148 u32 srbm_soft_reset = 0;
1149 u32 tmp = RREG32(mmSRBM_STATUS);
1150
1151 if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
1152 REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
1153 (RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK))
1154 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
1155
1156 if (srbm_soft_reset) {
1157 adev->uvd.inst->srbm_soft_reset = srbm_soft_reset;
1158 return true;
1159 } else {
1160 adev->uvd.inst->srbm_soft_reset = 0;
1161 return false;
1162 }
1163 }
1164
uvd_v6_0_pre_soft_reset(void * handle)1165 static int uvd_v6_0_pre_soft_reset(void *handle)
1166 {
1167 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1168
1169 if (!adev->uvd.inst->srbm_soft_reset)
1170 return 0;
1171
1172 uvd_v6_0_stop(adev);
1173 return 0;
1174 }
1175
uvd_v6_0_soft_reset(void * handle)1176 static int uvd_v6_0_soft_reset(void *handle)
1177 {
1178 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1179 u32 srbm_soft_reset;
1180
1181 if (!adev->uvd.inst->srbm_soft_reset)
1182 return 0;
1183 srbm_soft_reset = adev->uvd.inst->srbm_soft_reset;
1184
1185 if (srbm_soft_reset) {
1186 u32 tmp;
1187
1188 tmp = RREG32(mmSRBM_SOFT_RESET);
1189 tmp |= srbm_soft_reset;
1190 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1191 WREG32(mmSRBM_SOFT_RESET, tmp);
1192 tmp = RREG32(mmSRBM_SOFT_RESET);
1193
1194 udelay(50);
1195
1196 tmp &= ~srbm_soft_reset;
1197 WREG32(mmSRBM_SOFT_RESET, tmp);
1198 tmp = RREG32(mmSRBM_SOFT_RESET);
1199
1200 /* Wait a little for things to settle down */
1201 udelay(50);
1202 }
1203
1204 return 0;
1205 }
1206
uvd_v6_0_post_soft_reset(void * handle)1207 static int uvd_v6_0_post_soft_reset(void *handle)
1208 {
1209 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1210
1211 if (!adev->uvd.inst->srbm_soft_reset)
1212 return 0;
1213
1214 mdelay(5);
1215
1216 return uvd_v6_0_start(adev);
1217 }
1218
uvd_v6_0_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1219 static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev,
1220 struct amdgpu_irq_src *source,
1221 unsigned type,
1222 enum amdgpu_interrupt_state state)
1223 {
1224 // TODO
1225 return 0;
1226 }
1227
uvd_v6_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1228 static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
1229 struct amdgpu_irq_src *source,
1230 struct amdgpu_iv_entry *entry)
1231 {
1232 bool int_handled = true;
1233 DRM_DEBUG("IH: UVD TRAP\n");
1234
1235 switch (entry->src_id) {
1236 case 124:
1237 amdgpu_fence_process(&adev->uvd.inst->ring);
1238 break;
1239 case 119:
1240 if (likely(uvd_v6_0_enc_support(adev)))
1241 amdgpu_fence_process(&adev->uvd.inst->ring_enc[0]);
1242 else
1243 int_handled = false;
1244 break;
1245 case 120:
1246 if (likely(uvd_v6_0_enc_support(adev)))
1247 amdgpu_fence_process(&adev->uvd.inst->ring_enc[1]);
1248 else
1249 int_handled = false;
1250 break;
1251 }
1252
1253 if (false == int_handled)
1254 DRM_ERROR("Unhandled interrupt: %d %d\n",
1255 entry->src_id, entry->src_data[0]);
1256
1257 return 0;
1258 }
1259
uvd_v6_0_enable_clock_gating(struct amdgpu_device * adev,bool enable)1260 static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
1261 {
1262 uint32_t data1, data3;
1263
1264 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1265 data3 = RREG32(mmUVD_CGC_GATE);
1266
1267 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
1268 UVD_SUVD_CGC_GATE__SIT_MASK |
1269 UVD_SUVD_CGC_GATE__SMP_MASK |
1270 UVD_SUVD_CGC_GATE__SCM_MASK |
1271 UVD_SUVD_CGC_GATE__SDB_MASK |
1272 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
1273 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
1274 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
1275 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
1276 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
1277 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
1278 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
1279 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
1280
1281 if (enable) {
1282 data3 |= (UVD_CGC_GATE__SYS_MASK |
1283 UVD_CGC_GATE__UDEC_MASK |
1284 UVD_CGC_GATE__MPEG2_MASK |
1285 UVD_CGC_GATE__RBC_MASK |
1286 UVD_CGC_GATE__LMI_MC_MASK |
1287 UVD_CGC_GATE__LMI_UMC_MASK |
1288 UVD_CGC_GATE__IDCT_MASK |
1289 UVD_CGC_GATE__MPRD_MASK |
1290 UVD_CGC_GATE__MPC_MASK |
1291 UVD_CGC_GATE__LBSI_MASK |
1292 UVD_CGC_GATE__LRBBM_MASK |
1293 UVD_CGC_GATE__UDEC_RE_MASK |
1294 UVD_CGC_GATE__UDEC_CM_MASK |
1295 UVD_CGC_GATE__UDEC_IT_MASK |
1296 UVD_CGC_GATE__UDEC_DB_MASK |
1297 UVD_CGC_GATE__UDEC_MP_MASK |
1298 UVD_CGC_GATE__WCB_MASK |
1299 UVD_CGC_GATE__JPEG_MASK |
1300 UVD_CGC_GATE__SCPU_MASK |
1301 UVD_CGC_GATE__JPEG2_MASK);
1302 /* only in pg enabled, we can gate clock to vcpu*/
1303 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
1304 data3 |= UVD_CGC_GATE__VCPU_MASK;
1305
1306 data3 &= ~UVD_CGC_GATE__REGS_MASK;
1307 } else {
1308 data3 = 0;
1309 }
1310
1311 WREG32(mmUVD_SUVD_CGC_GATE, data1);
1312 WREG32(mmUVD_CGC_GATE, data3);
1313 }
1314
uvd_v6_0_set_sw_clock_gating(struct amdgpu_device * adev)1315 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev)
1316 {
1317 uint32_t data, data2;
1318
1319 data = RREG32(mmUVD_CGC_CTRL);
1320 data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
1321
1322
1323 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
1324 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
1325
1326
1327 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
1328 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1329 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
1330
1331 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
1332 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
1333 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
1334 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
1335 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
1336 UVD_CGC_CTRL__SYS_MODE_MASK |
1337 UVD_CGC_CTRL__UDEC_MODE_MASK |
1338 UVD_CGC_CTRL__MPEG2_MODE_MASK |
1339 UVD_CGC_CTRL__REGS_MODE_MASK |
1340 UVD_CGC_CTRL__RBC_MODE_MASK |
1341 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
1342 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
1343 UVD_CGC_CTRL__IDCT_MODE_MASK |
1344 UVD_CGC_CTRL__MPRD_MODE_MASK |
1345 UVD_CGC_CTRL__MPC_MODE_MASK |
1346 UVD_CGC_CTRL__LBSI_MODE_MASK |
1347 UVD_CGC_CTRL__LRBBM_MODE_MASK |
1348 UVD_CGC_CTRL__WCB_MODE_MASK |
1349 UVD_CGC_CTRL__VCPU_MODE_MASK |
1350 UVD_CGC_CTRL__JPEG_MODE_MASK |
1351 UVD_CGC_CTRL__SCPU_MODE_MASK |
1352 UVD_CGC_CTRL__JPEG2_MODE_MASK);
1353 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
1354 UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
1355 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
1356 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
1357 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
1358
1359 WREG32(mmUVD_CGC_CTRL, data);
1360 WREG32(mmUVD_SUVD_CGC_CTRL, data2);
1361 }
1362
1363 #if 0
1364 static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev)
1365 {
1366 uint32_t data, data1, cgc_flags, suvd_flags;
1367
1368 data = RREG32(mmUVD_CGC_GATE);
1369 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1370
1371 cgc_flags = UVD_CGC_GATE__SYS_MASK |
1372 UVD_CGC_GATE__UDEC_MASK |
1373 UVD_CGC_GATE__MPEG2_MASK |
1374 UVD_CGC_GATE__RBC_MASK |
1375 UVD_CGC_GATE__LMI_MC_MASK |
1376 UVD_CGC_GATE__IDCT_MASK |
1377 UVD_CGC_GATE__MPRD_MASK |
1378 UVD_CGC_GATE__MPC_MASK |
1379 UVD_CGC_GATE__LBSI_MASK |
1380 UVD_CGC_GATE__LRBBM_MASK |
1381 UVD_CGC_GATE__UDEC_RE_MASK |
1382 UVD_CGC_GATE__UDEC_CM_MASK |
1383 UVD_CGC_GATE__UDEC_IT_MASK |
1384 UVD_CGC_GATE__UDEC_DB_MASK |
1385 UVD_CGC_GATE__UDEC_MP_MASK |
1386 UVD_CGC_GATE__WCB_MASK |
1387 UVD_CGC_GATE__VCPU_MASK |
1388 UVD_CGC_GATE__SCPU_MASK |
1389 UVD_CGC_GATE__JPEG_MASK |
1390 UVD_CGC_GATE__JPEG2_MASK;
1391
1392 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1393 UVD_SUVD_CGC_GATE__SIT_MASK |
1394 UVD_SUVD_CGC_GATE__SMP_MASK |
1395 UVD_SUVD_CGC_GATE__SCM_MASK |
1396 UVD_SUVD_CGC_GATE__SDB_MASK;
1397
1398 data |= cgc_flags;
1399 data1 |= suvd_flags;
1400
1401 WREG32(mmUVD_CGC_GATE, data);
1402 WREG32(mmUVD_SUVD_CGC_GATE, data1);
1403 }
1404 #endif
1405
uvd_v6_0_enable_mgcg(struct amdgpu_device * adev,bool enable)1406 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
1407 bool enable)
1408 {
1409 u32 orig, data;
1410
1411 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
1412 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
1413 data |= 0xfff;
1414 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
1415
1416 orig = data = RREG32(mmUVD_CGC_CTRL);
1417 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
1418 if (orig != data)
1419 WREG32(mmUVD_CGC_CTRL, data);
1420 } else {
1421 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
1422 data &= ~0xfff;
1423 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
1424
1425 orig = data = RREG32(mmUVD_CGC_CTRL);
1426 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
1427 if (orig != data)
1428 WREG32(mmUVD_CGC_CTRL, data);
1429 }
1430 }
1431
uvd_v6_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)1432 static int uvd_v6_0_set_clockgating_state(void *handle,
1433 enum amd_clockgating_state state)
1434 {
1435 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1436 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1437
1438 if (enable) {
1439 /* wait for STATUS to clear */
1440 if (uvd_v6_0_wait_for_idle(handle))
1441 return -EBUSY;
1442 uvd_v6_0_enable_clock_gating(adev, true);
1443 /* enable HW gates because UVD is idle */
1444 /* uvd_v6_0_set_hw_clock_gating(adev); */
1445 } else {
1446 /* disable HW gating and enable Sw gating */
1447 uvd_v6_0_enable_clock_gating(adev, false);
1448 }
1449 uvd_v6_0_set_sw_clock_gating(adev);
1450 return 0;
1451 }
1452
uvd_v6_0_set_powergating_state(void * handle,enum amd_powergating_state state)1453 static int uvd_v6_0_set_powergating_state(void *handle,
1454 enum amd_powergating_state state)
1455 {
1456 /* This doesn't actually powergate the UVD block.
1457 * That's done in the dpm code via the SMC. This
1458 * just re-inits the block as necessary. The actual
1459 * gating still happens in the dpm code. We should
1460 * revisit this when there is a cleaner line between
1461 * the smc and the hw blocks
1462 */
1463 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1464 int ret = 0;
1465
1466 WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1467
1468 if (state == AMD_PG_STATE_GATE) {
1469 uvd_v6_0_stop(adev);
1470 } else {
1471 ret = uvd_v6_0_start(adev);
1472 if (ret)
1473 goto out;
1474 }
1475
1476 out:
1477 return ret;
1478 }
1479
uvd_v6_0_get_clockgating_state(void * handle,u32 * flags)1480 static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags)
1481 {
1482 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1483 int data;
1484
1485 mutex_lock(&adev->pm.mutex);
1486
1487 if (adev->flags & AMD_IS_APU)
1488 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU);
1489 else
1490 data = RREG32_SMC(ixCURRENT_PG_STATUS);
1491
1492 if (data & CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
1493 DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
1494 goto out;
1495 }
1496
1497 /* AMD_CG_SUPPORT_UVD_MGCG */
1498 data = RREG32(mmUVD_CGC_CTRL);
1499 if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
1500 *flags |= AMD_CG_SUPPORT_UVD_MGCG;
1501
1502 out:
1503 mutex_unlock(&adev->pm.mutex);
1504 }
1505
1506 static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
1507 .name = "uvd_v6_0",
1508 .early_init = uvd_v6_0_early_init,
1509 .late_init = NULL,
1510 .sw_init = uvd_v6_0_sw_init,
1511 .sw_fini = uvd_v6_0_sw_fini,
1512 .hw_init = uvd_v6_0_hw_init,
1513 .hw_fini = uvd_v6_0_hw_fini,
1514 .suspend = uvd_v6_0_suspend,
1515 .resume = uvd_v6_0_resume,
1516 .is_idle = uvd_v6_0_is_idle,
1517 .wait_for_idle = uvd_v6_0_wait_for_idle,
1518 .check_soft_reset = uvd_v6_0_check_soft_reset,
1519 .pre_soft_reset = uvd_v6_0_pre_soft_reset,
1520 .soft_reset = uvd_v6_0_soft_reset,
1521 .post_soft_reset = uvd_v6_0_post_soft_reset,
1522 .set_clockgating_state = uvd_v6_0_set_clockgating_state,
1523 .set_powergating_state = uvd_v6_0_set_powergating_state,
1524 .get_clockgating_state = uvd_v6_0_get_clockgating_state,
1525 };
1526
1527 static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
1528 .type = AMDGPU_RING_TYPE_UVD,
1529 .align_mask = 0xf,
1530 .support_64bit_ptrs = false,
1531 .get_rptr = uvd_v6_0_ring_get_rptr,
1532 .get_wptr = uvd_v6_0_ring_get_wptr,
1533 .set_wptr = uvd_v6_0_ring_set_wptr,
1534 .parse_cs = amdgpu_uvd_ring_parse_cs,
1535 .emit_frame_size =
1536 6 + /* hdp invalidate */
1537 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
1538 14, /* uvd_v6_0_ring_emit_fence x1 no user fence */
1539 .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
1540 .emit_ib = uvd_v6_0_ring_emit_ib,
1541 .emit_fence = uvd_v6_0_ring_emit_fence,
1542 .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
1543 .test_ring = uvd_v6_0_ring_test_ring,
1544 .test_ib = amdgpu_uvd_ring_test_ib,
1545 .insert_nop = uvd_v6_0_ring_insert_nop,
1546 .pad_ib = amdgpu_ring_generic_pad_ib,
1547 .begin_use = amdgpu_uvd_ring_begin_use,
1548 .end_use = amdgpu_uvd_ring_end_use,
1549 .emit_wreg = uvd_v6_0_ring_emit_wreg,
1550 };
1551
1552 static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
1553 .type = AMDGPU_RING_TYPE_UVD,
1554 .align_mask = 0xf,
1555 .support_64bit_ptrs = false,
1556 .get_rptr = uvd_v6_0_ring_get_rptr,
1557 .get_wptr = uvd_v6_0_ring_get_wptr,
1558 .set_wptr = uvd_v6_0_ring_set_wptr,
1559 .emit_frame_size =
1560 6 + /* hdp invalidate */
1561 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
1562 VI_FLUSH_GPU_TLB_NUM_WREG * 6 + 8 + /* uvd_v6_0_ring_emit_vm_flush */
1563 14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
1564 .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
1565 .emit_ib = uvd_v6_0_ring_emit_ib,
1566 .emit_fence = uvd_v6_0_ring_emit_fence,
1567 .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush,
1568 .emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync,
1569 .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
1570 .test_ring = uvd_v6_0_ring_test_ring,
1571 .test_ib = amdgpu_uvd_ring_test_ib,
1572 .insert_nop = uvd_v6_0_ring_insert_nop,
1573 .pad_ib = amdgpu_ring_generic_pad_ib,
1574 .begin_use = amdgpu_uvd_ring_begin_use,
1575 .end_use = amdgpu_uvd_ring_end_use,
1576 .emit_wreg = uvd_v6_0_ring_emit_wreg,
1577 };
1578
1579 static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = {
1580 .type = AMDGPU_RING_TYPE_UVD_ENC,
1581 .align_mask = 0x3f,
1582 .nop = HEVC_ENC_CMD_NO_OP,
1583 .support_64bit_ptrs = false,
1584 .get_rptr = uvd_v6_0_enc_ring_get_rptr,
1585 .get_wptr = uvd_v6_0_enc_ring_get_wptr,
1586 .set_wptr = uvd_v6_0_enc_ring_set_wptr,
1587 .emit_frame_size =
1588 4 + /* uvd_v6_0_enc_ring_emit_pipeline_sync */
1589 5 + /* uvd_v6_0_enc_ring_emit_vm_flush */
1590 5 + 5 + /* uvd_v6_0_enc_ring_emit_fence x2 vm fence */
1591 1, /* uvd_v6_0_enc_ring_insert_end */
1592 .emit_ib_size = 5, /* uvd_v6_0_enc_ring_emit_ib */
1593 .emit_ib = uvd_v6_0_enc_ring_emit_ib,
1594 .emit_fence = uvd_v6_0_enc_ring_emit_fence,
1595 .emit_vm_flush = uvd_v6_0_enc_ring_emit_vm_flush,
1596 .emit_pipeline_sync = uvd_v6_0_enc_ring_emit_pipeline_sync,
1597 .test_ring = uvd_v6_0_enc_ring_test_ring,
1598 .test_ib = uvd_v6_0_enc_ring_test_ib,
1599 .insert_nop = amdgpu_ring_insert_nop,
1600 .insert_end = uvd_v6_0_enc_ring_insert_end,
1601 .pad_ib = amdgpu_ring_generic_pad_ib,
1602 .begin_use = amdgpu_uvd_ring_begin_use,
1603 .end_use = amdgpu_uvd_ring_end_use,
1604 };
1605
uvd_v6_0_set_ring_funcs(struct amdgpu_device * adev)1606 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev)
1607 {
1608 if (adev->asic_type >= CHIP_POLARIS10) {
1609 adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_vm_funcs;
1610 DRM_INFO("UVD is enabled in VM mode\n");
1611 } else {
1612 adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_phys_funcs;
1613 DRM_INFO("UVD is enabled in physical mode\n");
1614 }
1615 }
1616
uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device * adev)1617 static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1618 {
1619 int i;
1620
1621 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
1622 adev->uvd.inst->ring_enc[i].funcs = &uvd_v6_0_enc_ring_vm_funcs;
1623
1624 DRM_INFO("UVD ENC is enabled in VM mode\n");
1625 }
1626
1627 static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = {
1628 .set = uvd_v6_0_set_interrupt_state,
1629 .process = uvd_v6_0_process_interrupt,
1630 };
1631
uvd_v6_0_set_irq_funcs(struct amdgpu_device * adev)1632 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1633 {
1634 if (uvd_v6_0_enc_support(adev))
1635 adev->uvd.inst->irq.num_types = adev->uvd.num_enc_rings + 1;
1636 else
1637 adev->uvd.inst->irq.num_types = 1;
1638
1639 adev->uvd.inst->irq.funcs = &uvd_v6_0_irq_funcs;
1640 }
1641
1642 const struct amdgpu_ip_block_version uvd_v6_0_ip_block =
1643 {
1644 .type = AMD_IP_BLOCK_TYPE_UVD,
1645 .major = 6,
1646 .minor = 0,
1647 .rev = 0,
1648 .funcs = &uvd_v6_0_ip_funcs,
1649 };
1650
1651 const struct amdgpu_ip_block_version uvd_v6_2_ip_block =
1652 {
1653 .type = AMD_IP_BLOCK_TYPE_UVD,
1654 .major = 6,
1655 .minor = 2,
1656 .rev = 0,
1657 .funcs = &uvd_v6_0_ip_funcs,
1658 };
1659
1660 const struct amdgpu_ip_block_version uvd_v6_3_ip_block =
1661 {
1662 .type = AMD_IP_BLOCK_TYPE_UVD,
1663 .major = 6,
1664 .minor = 3,
1665 .rev = 0,
1666 .funcs = &uvd_v6_0_ip_funcs,
1667 };
1668
