1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright 2017 Texas Instruments, Inc. 4 */ 5 #ifndef __DT_BINDINGS_CLK_AM4_H 6 #define __DT_BINDINGS_CLK_AM4_H 7 8 #define AM4_CLKCTRL_OFFSET 0x20 9 #define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET) 10 11 /* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ 12 13 /* l4_wkup clocks */ 14 #define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120) 15 #define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220) 16 #define AM4_WKUP_M3_CLKCTRL AM4_CLKCTRL_INDEX(0x228) 17 #define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230) 18 #define AM4_TIMER1_CLKCTRL AM4_CLKCTRL_INDEX(0x328) 19 #define AM4_WD_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x338) 20 #define AM4_I2C1_CLKCTRL AM4_CLKCTRL_INDEX(0x340) 21 #define AM4_UART1_CLKCTRL AM4_CLKCTRL_INDEX(0x348) 22 #define AM4_SMARTREFLEX0_CLKCTRL AM4_CLKCTRL_INDEX(0x350) 23 #define AM4_SMARTREFLEX1_CLKCTRL AM4_CLKCTRL_INDEX(0x358) 24 #define AM4_CONTROL_CLKCTRL AM4_CLKCTRL_INDEX(0x360) 25 #define AM4_GPIO1_CLKCTRL AM4_CLKCTRL_INDEX(0x368) 26 27 /* mpu clocks */ 28 #define AM4_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 29 30 /* gfx_l3 clocks */ 31 #define AM4_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 32 33 /* l4_rtc clocks */ 34 #define AM4_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 35 36 /* l4_per clocks */ 37 #define AM4_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 38 #define AM4_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28) 39 #define AM4_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30) 40 #define AM4_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40) 41 #define AM4_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50) 42 #define AM4_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58) 43 #define AM4_VPFE0_CLKCTRL AM4_CLKCTRL_INDEX(0x68) 44 #define AM4_VPFE1_CLKCTRL AM4_CLKCTRL_INDEX(0x70) 45 #define AM4_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78) 46 #define AM4_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80) 47 #define AM4_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88) 48 #define AM4_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90) 49 #define AM4_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0) 50 #define AM4_GPMC_CLKCTRL AM4_CLKCTRL_INDEX(0x220) 51 #define AM4_MCASP0_CLKCTRL AM4_CLKCTRL_INDEX(0x238) 52 #define AM4_MCASP1_CLKCTRL AM4_CLKCTRL_INDEX(0x240) 53 #define AM4_MMC3_CLKCTRL AM4_CLKCTRL_INDEX(0x248) 54 #define AM4_QSPI_CLKCTRL AM4_CLKCTRL_INDEX(0x258) 55 #define AM4_USB_OTG_SS0_CLKCTRL AM4_CLKCTRL_INDEX(0x260) 56 #define AM4_USB_OTG_SS1_CLKCTRL AM4_CLKCTRL_INDEX(0x268) 57 #define AM4_PRUSS_CLKCTRL AM4_CLKCTRL_INDEX(0x320) 58 #define AM4_L4_LS_CLKCTRL AM4_CLKCTRL_INDEX(0x420) 59 #define AM4_D_CAN0_CLKCTRL AM4_CLKCTRL_INDEX(0x428) 60 #define AM4_D_CAN1_CLKCTRL AM4_CLKCTRL_INDEX(0x430) 61 #define AM4_EPWMSS0_CLKCTRL AM4_CLKCTRL_INDEX(0x438) 62 #define AM4_EPWMSS1_CLKCTRL AM4_CLKCTRL_INDEX(0x440) 63 #define AM4_EPWMSS2_CLKCTRL AM4_CLKCTRL_INDEX(0x448) 64 #define AM4_EPWMSS3_CLKCTRL AM4_CLKCTRL_INDEX(0x450) 65 #define AM4_EPWMSS4_CLKCTRL AM4_CLKCTRL_INDEX(0x458) 66 #define AM4_EPWMSS5_CLKCTRL AM4_CLKCTRL_INDEX(0x460) 67 #define AM4_ELM_CLKCTRL AM4_CLKCTRL_INDEX(0x468) 68 #define AM4_GPIO2_CLKCTRL AM4_CLKCTRL_INDEX(0x478) 69 #define AM4_GPIO3_CLKCTRL AM4_CLKCTRL_INDEX(0x480) 70 #define AM4_GPIO4_CLKCTRL AM4_CLKCTRL_INDEX(0x488) 71 #define AM4_GPIO5_CLKCTRL AM4_CLKCTRL_INDEX(0x490) 72 #define AM4_GPIO6_CLKCTRL AM4_CLKCTRL_INDEX(0x498) 73 #define AM4_HDQ1W_CLKCTRL AM4_CLKCTRL_INDEX(0x4a0) 74 #define AM4_I2C2_CLKCTRL AM4_CLKCTRL_INDEX(0x4a8) 75 #define AM4_I2C3_CLKCTRL AM4_CLKCTRL_INDEX(0x4b0) 76 #define AM4_MAILBOX_CLKCTRL AM4_CLKCTRL_INDEX(0x4b8) 77 #define AM4_MMC1_CLKCTRL AM4_CLKCTRL_INDEX(0x4c0) 78 #define AM4_MMC2_CLKCTRL AM4_CLKCTRL_INDEX(0x4c8) 79 #define AM4_RNG_CLKCTRL AM4_CLKCTRL_INDEX(0x4e0) 80 #define AM4_SPI0_CLKCTRL AM4_CLKCTRL_INDEX(0x500) 81 #define AM4_SPI1_CLKCTRL AM4_CLKCTRL_INDEX(0x508) 82 #define AM4_SPI2_CLKCTRL AM4_CLKCTRL_INDEX(0x510) 83 #define AM4_SPI3_CLKCTRL AM4_CLKCTRL_INDEX(0x518) 84 #define AM4_SPI4_CLKCTRL AM4_CLKCTRL_INDEX(0x520) 85 #define AM4_SPINLOCK_CLKCTRL AM4_CLKCTRL_INDEX(0x528) 86 #define AM4_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x530) 87 #define AM4_TIMER3_CLKCTRL AM4_CLKCTRL_INDEX(0x538) 88 #define AM4_TIMER4_CLKCTRL AM4_CLKCTRL_INDEX(0x540) 89 #define AM4_TIMER5_CLKCTRL AM4_CLKCTRL_INDEX(0x548) 90 #define AM4_TIMER6_CLKCTRL AM4_CLKCTRL_INDEX(0x550) 91 #define AM4_TIMER7_CLKCTRL AM4_CLKCTRL_INDEX(0x558) 92 #define AM4_TIMER8_CLKCTRL AM4_CLKCTRL_INDEX(0x560) 93 #define AM4_TIMER9_CLKCTRL AM4_CLKCTRL_INDEX(0x568) 94 #define AM4_TIMER10_CLKCTRL AM4_CLKCTRL_INDEX(0x570) 95 #define AM4_TIMER11_CLKCTRL AM4_CLKCTRL_INDEX(0x578) 96 #define AM4_UART2_CLKCTRL AM4_CLKCTRL_INDEX(0x580) 97 #define AM4_UART3_CLKCTRL AM4_CLKCTRL_INDEX(0x588) 98 #define AM4_UART4_CLKCTRL AM4_CLKCTRL_INDEX(0x590) 99 #define AM4_UART5_CLKCTRL AM4_CLKCTRL_INDEX(0x598) 100 #define AM4_UART6_CLKCTRL AM4_CLKCTRL_INDEX(0x5a0) 101 #define AM4_OCP2SCP0_CLKCTRL AM4_CLKCTRL_INDEX(0x5b8) 102 #define AM4_OCP2SCP1_CLKCTRL AM4_CLKCTRL_INDEX(0x5c0) 103 #define AM4_EMIF_CLKCTRL AM4_CLKCTRL_INDEX(0x720) 104 #define AM4_DSS_CORE_CLKCTRL AM4_CLKCTRL_INDEX(0xa20) 105 #define AM4_CPGMAC0_CLKCTRL AM4_CLKCTRL_INDEX(0xb20) 106 107 /* XXX: Compatibility part end. */ 108 109 /* l3s_tsc clocks */ 110 #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120 111 #define AM4_L3S_TSC_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_TSC_CLKCTRL_OFFSET) 112 #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120) 113 114 /* l4_wkup_aon clocks */ 115 #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228 116 #define AM4_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_AON_CLKCTRL_OFFSET) 117 #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228) 118 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230) 119 120 /* l4_wkup clocks */ 121 #define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220 122 #define AM4_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_CLKCTRL_OFFSET) 123 #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220) 124 #define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328) 125 #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338) 126 #define AM4_L4_WKUP_I2C1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x340) 127 #define AM4_L4_WKUP_UART1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x348) 128 #define AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x350) 129 #define AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x358) 130 #define AM4_L4_WKUP_CONTROL_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x360) 131 #define AM4_L4_WKUP_GPIO1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x368) 132 133 /* mpu clocks */ 134 #define AM4_MPU_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 135 136 /* gfx_l3 clocks */ 137 #define AM4_GFX_L3_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 138 139 /* l4_rtc clocks */ 140 #define AM4_L4_RTC_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 141 142 /* l3 clocks */ 143 #define AM4_L3_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 144 #define AM4_L3_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28) 145 #define AM4_L3_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30) 146 #define AM4_L3_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40) 147 #define AM4_L3_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50) 148 #define AM4_L3_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58) 149 #define AM4_L3_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78) 150 #define AM4_L3_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80) 151 #define AM4_L3_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88) 152 #define AM4_L3_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90) 153 #define AM4_L3_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0) 154 155 /* l3s clocks */ 156 #define AM4_L3S_CLKCTRL_OFFSET 0x68 157 #define AM4_L3S_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_CLKCTRL_OFFSET) 158 #define AM4_L3S_VPFE0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x68) 159 #define AM4_L3S_VPFE1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x70) 160 #define AM4_L3S_GPMC_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x220) 161 #define AM4_L3S_MCASP0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x238) 162 #define AM4_L3S_MCASP1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x240) 163 #define AM4_L3S_MMC3_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x248) 164 #define AM4_L3S_QSPI_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x258) 165 #define AM4_L3S_USB_OTG_SS0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x260) 166 #define AM4_L3S_USB_OTG_SS1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x268) 167 168 /* pruss_ocp clocks */ 169 #define AM4_PRUSS_OCP_CLKCTRL_OFFSET 0x320 170 #define AM4_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM4_PRUSS_OCP_CLKCTRL_OFFSET) 171 #define AM4_PRUSS_OCP_PRUSS_CLKCTRL AM4_PRUSS_OCP_CLKCTRL_INDEX(0x320) 172 173 /* l4ls clocks */ 174 #define AM4_L4LS_CLKCTRL_OFFSET 0x420 175 #define AM4_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM4_L4LS_CLKCTRL_OFFSET) 176 #define AM4_L4LS_L4_LS_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x420) 177 #define AM4_L4LS_D_CAN0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x428) 178 #define AM4_L4LS_D_CAN1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x430) 179 #define AM4_L4LS_EPWMSS0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x438) 180 #define AM4_L4LS_EPWMSS1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x440) 181 #define AM4_L4LS_EPWMSS2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x448) 182 #define AM4_L4LS_EPWMSS3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x450) 183 #define AM4_L4LS_EPWMSS4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x458) 184 #define AM4_L4LS_EPWMSS5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x460) 185 #define AM4_L4LS_ELM_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x468) 186 #define AM4_L4LS_GPIO2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x478) 187 #define AM4_L4LS_GPIO3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x480) 188 #define AM4_L4LS_GPIO4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x488) 189 #define AM4_L4LS_GPIO5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x490) 190 #define AM4_L4LS_GPIO6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x498) 191 #define AM4_L4LS_HDQ1W_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a0) 192 #define AM4_L4LS_I2C2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a8) 193 #define AM4_L4LS_I2C3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b0) 194 #define AM4_L4LS_MAILBOX_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b8) 195 #define AM4_L4LS_MMC1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c0) 196 #define AM4_L4LS_MMC2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c8) 197 #define AM4_L4LS_RNG_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4e0) 198 #define AM4_L4LS_SPI0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x500) 199 #define AM4_L4LS_SPI1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x508) 200 #define AM4_L4LS_SPI2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x510) 201 #define AM4_L4LS_SPI3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x518) 202 #define AM4_L4LS_SPI4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x520) 203 #define AM4_L4LS_SPINLOCK_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x528) 204 #define AM4_L4LS_TIMER2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x530) 205 #define AM4_L4LS_TIMER3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x538) 206 #define AM4_L4LS_TIMER4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x540) 207 #define AM4_L4LS_TIMER5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x548) 208 #define AM4_L4LS_TIMER6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x550) 209 #define AM4_L4LS_TIMER7_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x558) 210 #define AM4_L4LS_TIMER8_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x560) 211 #define AM4_L4LS_TIMER9_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x568) 212 #define AM4_L4LS_TIMER10_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x570) 213 #define AM4_L4LS_TIMER11_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x578) 214 #define AM4_L4LS_UART2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x580) 215 #define AM4_L4LS_UART3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x588) 216 #define AM4_L4LS_UART4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x590) 217 #define AM4_L4LS_UART5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x598) 218 #define AM4_L4LS_UART6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5a0) 219 #define AM4_L4LS_OCP2SCP0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5b8) 220 #define AM4_L4LS_OCP2SCP1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5c0) 221 222 /* emif clocks */ 223 #define AM4_EMIF_CLKCTRL_OFFSET 0x720 224 #define AM4_EMIF_CLKCTRL_INDEX(offset) ((offset) - AM4_EMIF_CLKCTRL_OFFSET) 225 #define AM4_EMIF_EMIF_CLKCTRL AM4_EMIF_CLKCTRL_INDEX(0x720) 226 227 /* dss clocks */ 228 #define AM4_DSS_CLKCTRL_OFFSET 0xa20 229 #define AM4_DSS_CLKCTRL_INDEX(offset) ((offset) - AM4_DSS_CLKCTRL_OFFSET) 230 #define AM4_DSS_DSS_CORE_CLKCTRL AM4_DSS_CLKCTRL_INDEX(0xa20) 231 232 /* cpsw_125mhz clocks */ 233 #define AM4_CPSW_125MHZ_CLKCTRL_OFFSET 0xb20 234 #define AM4_CPSW_125MHZ_CLKCTRL_INDEX(offset) ((offset) - AM4_CPSW_125MHZ_CLKCTRL_OFFSET) 235 #define AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL AM4_CPSW_125MHZ_CLKCTRL_INDEX(0xb20) 236 237 #endif 238
