1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Cryptographic API. 4 * 5 * Support for OMAP AES HW ACCELERATOR defines 6 * 7 * Copyright (c) 2015 Texas Instruments Incorporated 8 */ 9 #ifndef __OMAP_AES_H__ 10 #define __OMAP_AES_H__ 11 12 #include <crypto/engine.h> 13 14 #define DST_MAXBURST 4 15 #define DMA_MIN (DST_MAXBURST * sizeof(u32)) 16 17 #define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset) 18 19 /* 20 * OMAP TRM gives bitfields as start:end, where start is the higher bit 21 * number. For example 7:0 22 */ 23 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end)) 24 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) 25 26 #define AES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \ 27 (((x) ^ 0x01) * 0x04)) 28 #define AES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04)) 29 30 #define AES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs) 31 #define AES_REG_CTRL_CONTEXT_READY BIT(31) 32 #define AES_REG_CTRL_CTR_WIDTH_MASK GENMASK(8, 7) 33 #define AES_REG_CTRL_CTR_WIDTH_32 0 34 #define AES_REG_CTRL_CTR_WIDTH_64 BIT(7) 35 #define AES_REG_CTRL_CTR_WIDTH_96 BIT(8) 36 #define AES_REG_CTRL_CTR_WIDTH_128 GENMASK(8, 7) 37 #define AES_REG_CTRL_GCM GENMASK(17, 16) 38 #define AES_REG_CTRL_CTR BIT(6) 39 #define AES_REG_CTRL_CBC BIT(5) 40 #define AES_REG_CTRL_KEY_SIZE GENMASK(4, 3) 41 #define AES_REG_CTRL_DIRECTION BIT(2) 42 #define AES_REG_CTRL_INPUT_READY BIT(1) 43 #define AES_REG_CTRL_OUTPUT_READY BIT(0) 44 #define AES_REG_CTRL_MASK GENMASK(24, 2) 45 46 #define AES_REG_C_LEN_0 0x54 47 #define AES_REG_C_LEN_1 0x58 48 #define AES_REG_A_LEN 0x5C 49 50 #define AES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04)) 51 #define AES_REG_TAG_N(dd, x) (0x70 + ((x) * 0x04)) 52 53 #define AES_REG_REV(dd) ((dd)->pdata->rev_ofs) 54 55 #define AES_REG_MASK(dd) ((dd)->pdata->mask_ofs) 56 #define AES_REG_MASK_SIDLE BIT(6) 57 #define AES_REG_MASK_START BIT(5) 58 #define AES_REG_MASK_DMA_OUT_EN BIT(3) 59 #define AES_REG_MASK_DMA_IN_EN BIT(2) 60 #define AES_REG_MASK_SOFTRESET BIT(1) 61 #define AES_REG_AUTOIDLE BIT(0) 62 63 #define AES_REG_LENGTH_N(x) (0x54 + ((x) * 0x04)) 64 65 #define AES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs) 66 #define AES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs) 67 #define AES_REG_IRQ_DATA_IN BIT(1) 68 #define AES_REG_IRQ_DATA_OUT BIT(2) 69 #define DEFAULT_TIMEOUT (5 * HZ) 70 71 #define DEFAULT_AUTOSUSPEND_DELAY 1000 72 73 #define FLAGS_MODE_MASK 0x001f 74 #define FLAGS_ENCRYPT BIT(0) 75 #define FLAGS_CBC BIT(1) 76 #define FLAGS_CTR BIT(2) 77 #define FLAGS_GCM BIT(3) 78 #define FLAGS_RFC4106_GCM BIT(4) 79 80 #define FLAGS_INIT BIT(5) 81 #define FLAGS_FAST BIT(6) 82 #define FLAGS_BUSY BIT(7) 83 84 #define FLAGS_IN_DATA_ST_SHIFT 8 85 #define FLAGS_OUT_DATA_ST_SHIFT 10 86 #define FLAGS_ASSOC_DATA_ST_SHIFT 12 87 88 #define AES_BLOCK_WORDS (AES_BLOCK_SIZE >> 2) 89 90 struct omap_aes_gcm_result { 91 struct completion completion; 92 int err; 93 }; 94 95 struct omap_aes_ctx { 96 struct crypto_engine_ctx enginectx; 97 int keylen; 98 u32 key[AES_KEYSIZE_256 / sizeof(u32)]; 99 u8 nonce[4]; 100 struct crypto_sync_skcipher *fallback; 101 struct crypto_skcipher *ctr; 102 }; 103 104 struct omap_aes_reqctx { 105 struct omap_aes_dev *dd; 106 unsigned long mode; 107 u8 iv[AES_BLOCK_SIZE]; 108 u32 auth_tag[AES_BLOCK_SIZE / sizeof(u32)]; 109 }; 110 111 #define OMAP_AES_QUEUE_LENGTH 1 112 #define OMAP_AES_CACHE_SIZE 0 113 114 struct omap_aes_algs_info { 115 struct crypto_alg *algs_list; 116 unsigned int size; 117 unsigned int registered; 118 }; 119 120 struct omap_aes_aead_algs { 121 struct aead_alg *algs_list; 122 unsigned int size; 123 unsigned int registered; 124 }; 125 126 struct omap_aes_pdata { 127 struct omap_aes_algs_info *algs_info; 128 unsigned int algs_info_size; 129 struct omap_aes_aead_algs *aead_algs_info; 130 131 void (*trigger)(struct omap_aes_dev *dd, int length); 132 133 u32 key_ofs; 134 u32 iv_ofs; 135 u32 ctrl_ofs; 136 u32 data_ofs; 137 u32 rev_ofs; 138 u32 mask_ofs; 139 u32 irq_enable_ofs; 140 u32 irq_status_ofs; 141 142 u32 dma_enable_in; 143 u32 dma_enable_out; 144 u32 dma_start; 145 146 u32 major_mask; 147 u32 major_shift; 148 u32 minor_mask; 149 u32 minor_shift; 150 }; 151 152 struct omap_aes_dev { 153 struct list_head list; 154 unsigned long phys_base; 155 void __iomem *io_base; 156 struct omap_aes_ctx *ctx; 157 struct device *dev; 158 unsigned long flags; 159 int err; 160 161 struct tasklet_struct done_task; 162 struct aead_queue aead_queue; 163 spinlock_t lock; 164 165 struct ablkcipher_request *req; 166 struct aead_request *aead_req; 167 struct crypto_engine *engine; 168 169 /* 170 * total is used by PIO mode for book keeping so introduce 171 * variable total_save as need it to calc page_order 172 */ 173 size_t total; 174 size_t total_save; 175 size_t assoc_len; 176 size_t authsize; 177 178 struct scatterlist *in_sg; 179 struct scatterlist *out_sg; 180 181 /* Buffers for copying for unaligned cases */ 182 struct scatterlist in_sgl[2]; 183 struct scatterlist out_sgl; 184 struct scatterlist *orig_out; 185 186 struct scatter_walk in_walk; 187 struct scatter_walk out_walk; 188 struct dma_chan *dma_lch_in; 189 struct dma_chan *dma_lch_out; 190 int in_sg_len; 191 int out_sg_len; 192 int pio_only; 193 const struct omap_aes_pdata *pdata; 194 }; 195 196 u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset); 197 void omap_aes_write(struct omap_aes_dev *dd, u32 offset, u32 value); 198 struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_reqctx *rctx); 199 int omap_aes_gcm_setkey(struct crypto_aead *tfm, const u8 *key, 200 unsigned int keylen); 201 int omap_aes_4106gcm_setkey(struct crypto_aead *tfm, const u8 *key, 202 unsigned int keylen); 203 int omap_aes_gcm_encrypt(struct aead_request *req); 204 int omap_aes_gcm_decrypt(struct aead_request *req); 205 int omap_aes_4106gcm_encrypt(struct aead_request *req); 206 int omap_aes_4106gcm_decrypt(struct aead_request *req); 207 int omap_aes_write_ctrl(struct omap_aes_dev *dd); 208 int omap_aes_crypt_dma_start(struct omap_aes_dev *dd); 209 int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd); 210 void omap_aes_gcm_dma_out_callback(void *data); 211 void omap_aes_clear_copy_flags(struct omap_aes_dev *dd); 212 213 #endif 214
