1 /*
2 * Copyright (C) 2016 IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9 #include <linux/bitops.h>
10 #include <linux/init.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/mutex.h>
15 #include <linux/of.h>
16 #include <linux/platform_device.h>
17 #include <linux/pinctrl/pinctrl.h>
18 #include <linux/pinctrl/pinmux.h>
19 #include <linux/pinctrl/pinconf.h>
20 #include <linux/pinctrl/pinconf-generic.h>
21 #include <linux/string.h>
22 #include <linux/types.h>
23
24 #include "../core.h"
25 #include "../pinctrl-utils.h"
26 #include "pinctrl-aspeed.h"
27
28 #define ASPEED_G5_NR_PINS 236
29
30 #define COND1 { ASPEED_IP_SCU, SCU90, BIT(6), 0, 0 }
31 #define COND2 { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
32
33 /* LHCR0 is offset from the end of the H8S/2168-compatible registers */
34 #define LHCR0 0x20
35 #define GFX064 0x64
36
37 #define B14 0
38 SSSF_PIN_DECL(B14, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0));
39
40 #define D14 1
41 SSSF_PIN_DECL(D14, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1));
42
43 #define D13 2
44 SIG_EXPR_LIST_DECL_SINGLE(SPI1CS1, SPI1CS1, SIG_DESC_SET(SCU80, 15));
45 SIG_EXPR_LIST_DECL_SINGLE(TIMER3, TIMER3, SIG_DESC_SET(SCU80, 2));
46 MS_PIN_DECL(D13, GPIOA2, SPI1CS1, TIMER3);
47 FUNC_GROUP_DECL(SPI1CS1, D13);
48 FUNC_GROUP_DECL(TIMER3, D13);
49
50 #define E13 3
51 SSSF_PIN_DECL(E13, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3));
52
53 #define I2C9_DESC SIG_DESC_SET(SCU90, 22)
54
55 #define C14 4
56 SIG_EXPR_LIST_DECL_SINGLE(SCL9, I2C9, I2C9_DESC, COND1);
57 SIG_EXPR_LIST_DECL_SINGLE(TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4), COND1);
58 MS_PIN_DECL(C14, GPIOA4, SCL9, TIMER5);
59
60 FUNC_GROUP_DECL(TIMER5, C14);
61
62 #define A13 5
63 SIG_EXPR_LIST_DECL_SINGLE(SDA9, I2C9, I2C9_DESC, COND1);
64 SIG_EXPR_LIST_DECL_SINGLE(TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5), COND1);
65 MS_PIN_DECL(A13, GPIOA5, SDA9, TIMER6);
66
67 FUNC_GROUP_DECL(TIMER6, A13);
68
69 FUNC_GROUP_DECL(I2C9, C14, A13);
70
71 #define MDIO2_DESC SIG_DESC_SET(SCU90, 2)
72
73 #define C13 6
74 SIG_EXPR_LIST_DECL_SINGLE(MDC2, MDIO2, MDIO2_DESC, COND1);
75 SIG_EXPR_LIST_DECL_SINGLE(TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6), COND1);
76 MS_PIN_DECL(C13, GPIOA6, MDC2, TIMER7);
77
78 FUNC_GROUP_DECL(TIMER7, C13);
79
80 #define B13 7
81 SIG_EXPR_LIST_DECL_SINGLE(MDIO2, MDIO2, MDIO2_DESC, COND1);
82 SIG_EXPR_LIST_DECL_SINGLE(TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7), COND1);
83 MS_PIN_DECL(B13, GPIOA7, MDIO2, TIMER8);
84
85 FUNC_GROUP_DECL(TIMER8, B13);
86
87 FUNC_GROUP_DECL(MDIO2, C13, B13);
88
89 #define K19 8
90 GPIO_PIN_DECL(K19, GPIOB0);
91
92 #define L19 9
93 GPIO_PIN_DECL(L19, GPIOB1);
94
95 #define L18 10
96 GPIO_PIN_DECL(L18, GPIOB2);
97
98 #define K18 11
99 GPIO_PIN_DECL(K18, GPIOB3);
100
101 #define J20 12
102 SSSF_PIN_DECL(J20, GPIOB4, USBCKI, SIG_DESC_SET(HW_STRAP1, 23));
103
104 #define H21 13
105 #define H21_DESC SIG_DESC_SET(SCU80, 13)
106 SIG_EXPR_LIST_DECL_SINGLE(LPCPD, LPCPD, H21_DESC);
107 SIG_EXPR_LIST_DECL_SINGLE(LPCSMI, LPCSMI, H21_DESC);
108 MS_PIN_DECL(H21, GPIOB5, LPCPD, LPCSMI);
109 FUNC_GROUP_DECL(LPCPD, H21);
110 FUNC_GROUP_DECL(LPCSMI, H21);
111
112 #define H22 14
113 SSSF_PIN_DECL(H22, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14));
114
115 #define H20 15
116 GPIO_PIN_DECL(H20, GPIOB7);
117
118 #define SD1_DESC SIG_DESC_SET(SCU90, 0)
119
120 #define C12 16
121 #define I2C10_DESC SIG_DESC_SET(SCU90, 23)
122 SIG_EXPR_LIST_DECL_SINGLE(SD1CLK, SD1, SD1_DESC);
123 SIG_EXPR_LIST_DECL_SINGLE(SCL10, I2C10, I2C10_DESC);
124 MS_PIN_DECL(C12, GPIOC0, SD1CLK, SCL10);
125
126 #define A12 17
127 SIG_EXPR_LIST_DECL_SINGLE(SD1CMD, SD1, SD1_DESC);
128 SIG_EXPR_LIST_DECL_SINGLE(SDA10, I2C10, I2C10_DESC);
129 MS_PIN_DECL(A12, GPIOC1, SD1CMD, SDA10);
130
131 FUNC_GROUP_DECL(I2C10, C12, A12);
132
133 #define B12 18
134 #define I2C11_DESC SIG_DESC_SET(SCU90, 24)
135 SIG_EXPR_LIST_DECL_SINGLE(SD1DAT0, SD1, SD1_DESC);
136 SIG_EXPR_LIST_DECL_SINGLE(SCL11, I2C11, I2C11_DESC);
137 MS_PIN_DECL(B12, GPIOC2, SD1DAT0, SCL11);
138
139 #define D9 19
140 SIG_EXPR_LIST_DECL_SINGLE(SD1DAT1, SD1, SD1_DESC);
141 SIG_EXPR_LIST_DECL_SINGLE(SDA11, I2C11, I2C11_DESC);
142 MS_PIN_DECL(D9, GPIOC3, SD1DAT1, SDA11);
143
144 FUNC_GROUP_DECL(I2C11, B12, D9);
145
146 #define D10 20
147 #define I2C12_DESC SIG_DESC_SET(SCU90, 25)
148 SIG_EXPR_LIST_DECL_SINGLE(SD1DAT2, SD1, SD1_DESC);
149 SIG_EXPR_LIST_DECL_SINGLE(SCL12, I2C12, I2C12_DESC);
150 MS_PIN_DECL(D10, GPIOC4, SD1DAT2, SCL12);
151
152 #define E12 21
153 SIG_EXPR_LIST_DECL_SINGLE(SD1DAT3, SD1, SD1_DESC);
154 SIG_EXPR_LIST_DECL_SINGLE(SDA12, I2C12, I2C12_DESC);
155 MS_PIN_DECL(E12, GPIOC5, SD1DAT3, SDA12);
156
157 FUNC_GROUP_DECL(I2C12, D10, E12);
158
159 #define C11 22
160 #define I2C13_DESC SIG_DESC_SET(SCU90, 26)
161 SIG_EXPR_LIST_DECL_SINGLE(SD1CD, SD1, SD1_DESC);
162 SIG_EXPR_LIST_DECL_SINGLE(SCL13, I2C13, I2C13_DESC);
163 MS_PIN_DECL(C11, GPIOC6, SD1CD, SCL13);
164
165 #define B11 23
166 SIG_EXPR_LIST_DECL_SINGLE(SD1WP, SD1, SD1_DESC);
167 SIG_EXPR_LIST_DECL_SINGLE(SDA13, I2C13, I2C13_DESC);
168 MS_PIN_DECL(B11, GPIOC7, SD1WP, SDA13);
169
170 FUNC_GROUP_DECL(I2C13, C11, B11);
171 FUNC_GROUP_DECL(SD1, C12, A12, B12, D9, D10, E12, C11, B11);
172
173 #define SD2_DESC SIG_DESC_SET(SCU90, 1)
174 #define GPID0_DESC SIG_DESC_SET(SCU8C, 8)
175 #define GPID_DESC SIG_DESC_SET(HW_STRAP1, 21)
176
177 #define F19 24
178 SIG_EXPR_LIST_DECL_SINGLE(SD2CLK, SD2, SD2_DESC);
179 SIG_EXPR_DECL(GPID0IN, GPID0, GPID0_DESC);
180 SIG_EXPR_DECL(GPID0IN, GPID, GPID_DESC);
181 SIG_EXPR_LIST_DECL_DUAL(GPID0IN, GPID0, GPID);
182 MS_PIN_DECL(F19, GPIOD0, SD2CLK, GPID0IN);
183
184 #define E21 25
185 SIG_EXPR_LIST_DECL_SINGLE(SD2CMD, SD2, SD2_DESC);
186 SIG_EXPR_DECL(GPID0OUT, GPID0, GPID0_DESC);
187 SIG_EXPR_DECL(GPID0OUT, GPID, GPID_DESC);
188 SIG_EXPR_LIST_DECL_DUAL(GPID0OUT, GPID0, GPID);
189 MS_PIN_DECL(E21, GPIOD1, SD2CMD, GPID0OUT);
190
191 FUNC_GROUP_DECL(GPID0, F19, E21);
192
193 #define GPID2_DESC SIG_DESC_SET(SCU8C, 9)
194
195 #define F20 26
196 SIG_EXPR_LIST_DECL_SINGLE(SD2DAT0, SD2, SD2_DESC);
197 SIG_EXPR_DECL(GPID2IN, GPID2, GPID2_DESC);
198 SIG_EXPR_DECL(GPID2IN, GPID, GPID_DESC);
199 SIG_EXPR_LIST_DECL_DUAL(GPID2IN, GPID2, GPID);
200 MS_PIN_DECL(F20, GPIOD2, SD2DAT0, GPID2IN);
201
202 #define D20 27
203 SIG_EXPR_LIST_DECL_SINGLE(SD2DAT1, SD2, SD2_DESC);
204 SIG_EXPR_DECL(GPID2OUT, GPID2, GPID2_DESC);
205 SIG_EXPR_DECL(GPID2OUT, GPID, GPID_DESC);
206 SIG_EXPR_LIST_DECL_DUAL(GPID2OUT, GPID2, GPID);
207 MS_PIN_DECL(D20, GPIOD3, SD2DAT1, GPID2OUT);
208
209 FUNC_GROUP_DECL(GPID2, F20, D20);
210
211 #define GPID4_DESC SIG_DESC_SET(SCU8C, 10)
212
213 #define D21 28
214 SIG_EXPR_LIST_DECL_SINGLE(SD2DAT2, SD2, SD2_DESC);
215 SIG_EXPR_DECL(GPID4IN, GPID4, GPID4_DESC);
216 SIG_EXPR_DECL(GPID4IN, GPID, GPID_DESC);
217 SIG_EXPR_LIST_DECL_DUAL(GPID4IN, GPID4, GPID);
218 MS_PIN_DECL(D21, GPIOD4, SD2DAT2, GPID4IN);
219
220 #define E20 29
221 SIG_EXPR_LIST_DECL_SINGLE(SD2DAT3, SD2, SD2_DESC);
222 SIG_EXPR_DECL(GPID4OUT, GPID4, GPID4_DESC);
223 SIG_EXPR_DECL(GPID4OUT, GPID, GPID_DESC);
224 SIG_EXPR_LIST_DECL_DUAL(GPID4OUT, GPID4, GPID);
225 MS_PIN_DECL(E20, GPIOD5, SD2DAT3, GPID4OUT);
226
227 FUNC_GROUP_DECL(GPID4, D21, E20);
228
229 #define GPID6_DESC SIG_DESC_SET(SCU8C, 11)
230
231 #define G18 30
232 SIG_EXPR_LIST_DECL_SINGLE(SD2CD, SD2, SD2_DESC);
233 SIG_EXPR_DECL(GPID6IN, GPID6, GPID6_DESC);
234 SIG_EXPR_DECL(GPID6IN, GPID, GPID_DESC);
235 SIG_EXPR_LIST_DECL_DUAL(GPID6IN, GPID6, GPID);
236 MS_PIN_DECL(G18, GPIOD6, SD2CD, GPID6IN);
237
238 #define C21 31
239 SIG_EXPR_LIST_DECL_SINGLE(SD2WP, SD2, SD2_DESC);
240 SIG_EXPR_DECL(GPID6OUT, GPID6, GPID6_DESC);
241 SIG_EXPR_DECL(GPID6OUT, GPID, GPID_DESC);
242 SIG_EXPR_LIST_DECL_DUAL(GPID6OUT, GPID6, GPID);
243 MS_PIN_DECL(C21, GPIOD7, SD2WP, GPID6OUT);
244
245 FUNC_GROUP_DECL(GPID6, G18, C21);
246 FUNC_GROUP_DECL(SD2, F19, E21, F20, D20, D21, E20, G18, C21);
247
248 #define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22)
249 #define GPIE0_DESC SIG_DESC_SET(SCU8C, 12)
250
251 #define B20 32
252 SIG_EXPR_LIST_DECL_SINGLE(NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16));
253 SIG_EXPR_DECL(GPIE0IN, GPIE0, GPIE0_DESC);
254 SIG_EXPR_DECL(GPIE0IN, GPIE, GPIE_DESC);
255 SIG_EXPR_LIST_DECL_DUAL(GPIE0IN, GPIE0, GPIE);
256 MS_PIN_DECL(B20, GPIOE0, NCTS3, GPIE0IN);
257 FUNC_GROUP_DECL(NCTS3, B20);
258
259 #define C20 33
260 SIG_EXPR_LIST_DECL_SINGLE(NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17));
261 SIG_EXPR_DECL(GPIE0OUT, GPIE0, GPIE0_DESC);
262 SIG_EXPR_DECL(GPIE0OUT, GPIE, GPIE_DESC);
263 SIG_EXPR_LIST_DECL_DUAL(GPIE0OUT, GPIE0, GPIE);
264 MS_PIN_DECL(C20, GPIOE1, NDCD3, GPIE0OUT);
265 FUNC_GROUP_DECL(NDCD3, C20);
266
267 FUNC_GROUP_DECL(GPIE0, B20, C20);
268
269 #define GPIE2_DESC SIG_DESC_SET(SCU8C, 13)
270
271 #define F18 34
272 SIG_EXPR_LIST_DECL_SINGLE(NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18));
273 SIG_EXPR_DECL(GPIE2IN, GPIE2, GPIE2_DESC);
274 SIG_EXPR_DECL(GPIE2IN, GPIE, GPIE_DESC);
275 SIG_EXPR_LIST_DECL_DUAL(GPIE2IN, GPIE2, GPIE);
276 MS_PIN_DECL(F18, GPIOE2, NDSR3, GPIE2IN);
277 FUNC_GROUP_DECL(NDSR3, F18);
278
279
280 #define F17 35
281 SIG_EXPR_LIST_DECL_SINGLE(NRI3, NRI3, SIG_DESC_SET(SCU80, 19));
282 SIG_EXPR_DECL(GPIE2OUT, GPIE2, GPIE2_DESC);
283 SIG_EXPR_DECL(GPIE2OUT, GPIE, GPIE_DESC);
284 SIG_EXPR_LIST_DECL_DUAL(GPIE2OUT, GPIE2, GPIE);
285 MS_PIN_DECL(F17, GPIOE3, NRI3, GPIE2OUT);
286 FUNC_GROUP_DECL(NRI3, F17);
287
288 FUNC_GROUP_DECL(GPIE2, F18, F17);
289
290 #define GPIE4_DESC SIG_DESC_SET(SCU8C, 14)
291
292 #define E18 36
293 SIG_EXPR_LIST_DECL_SINGLE(NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20));
294 SIG_EXPR_DECL(GPIE4IN, GPIE4, GPIE4_DESC);
295 SIG_EXPR_DECL(GPIE4IN, GPIE, GPIE_DESC);
296 SIG_EXPR_LIST_DECL_DUAL(GPIE4IN, GPIE4, GPIE);
297 MS_PIN_DECL(E18, GPIOE4, NDTR3, GPIE4IN);
298 FUNC_GROUP_DECL(NDTR3, E18);
299
300 #define D19 37
301 SIG_EXPR_LIST_DECL_SINGLE(NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21));
302 SIG_EXPR_DECL(GPIE4OUT, GPIE4, GPIE4_DESC);
303 SIG_EXPR_DECL(GPIE4OUT, GPIE, GPIE_DESC);
304 SIG_EXPR_LIST_DECL_DUAL(GPIE4OUT, GPIE4, GPIE);
305 MS_PIN_DECL(D19, GPIOE5, NRTS3, GPIE4OUT);
306 FUNC_GROUP_DECL(NRTS3, D19);
307
308 FUNC_GROUP_DECL(GPIE4, E18, D19);
309
310 #define GPIE6_DESC SIG_DESC_SET(SCU8C, 15)
311
312 #define A20 38
313 SIG_EXPR_LIST_DECL_SINGLE(TXD3, TXD3, SIG_DESC_SET(SCU80, 22));
314 SIG_EXPR_DECL(GPIE6IN, GPIE6, GPIE6_DESC);
315 SIG_EXPR_DECL(GPIE6IN, GPIE, GPIE_DESC);
316 SIG_EXPR_LIST_DECL_DUAL(GPIE6IN, GPIE6, GPIE);
317 MS_PIN_DECL(A20, GPIOE6, TXD3, GPIE6IN);
318 FUNC_GROUP_DECL(TXD3, A20);
319
320 #define B19 39
321 SIG_EXPR_LIST_DECL_SINGLE(RXD3, RXD3, SIG_DESC_SET(SCU80, 23));
322 SIG_EXPR_DECL(GPIE6OUT, GPIE6, GPIE6_DESC);
323 SIG_EXPR_DECL(GPIE6OUT, GPIE, GPIE_DESC);
324 SIG_EXPR_LIST_DECL_DUAL(GPIE6OUT, GPIE6, GPIE);
325 MS_PIN_DECL(B19, GPIOE7, RXD3, GPIE6OUT);
326 FUNC_GROUP_DECL(RXD3, B19);
327
328 FUNC_GROUP_DECL(GPIE6, A20, B19);
329
330 #define LPCHC_DESC SIG_DESC_IP_SET(ASPEED_IP_LPC, LHCR0, 0)
331 #define LPCPLUS_DESC SIG_DESC_SET(SCU90, 30)
332
333 #define J19 40
334 SIG_EXPR_DECL(LHAD0, LPCHC, LPCHC_DESC);
335 SIG_EXPR_DECL(LHAD0, LPCPLUS, LPCPLUS_DESC);
336 SIG_EXPR_LIST_DECL_DUAL(LHAD0, LPCHC, LPCPLUS);
337 SIG_EXPR_LIST_DECL_SINGLE(NCTS4, NCTS4, SIG_DESC_SET(SCU80, 24));
338 MS_PIN_DECL(J19, GPIOF0, LHAD0, NCTS4);
339 FUNC_GROUP_DECL(NCTS4, J19);
340
341 #define J18 41
342 SIG_EXPR_DECL(LHAD1, LPCHC, LPCHC_DESC);
343 SIG_EXPR_DECL(LHAD1, LPCPLUS, LPCPLUS_DESC);
344 SIG_EXPR_LIST_DECL_DUAL(LHAD1, LPCHC, LPCPLUS);
345 SIG_EXPR_LIST_DECL_SINGLE(NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25));
346 MS_PIN_DECL(J18, GPIOF1, LHAD1, NDCD4);
347 FUNC_GROUP_DECL(NDCD4, J18);
348
349 #define B22 42
350 SIG_EXPR_DECL(LHAD2, LPCHC, LPCHC_DESC);
351 SIG_EXPR_DECL(LHAD2, LPCPLUS, LPCPLUS_DESC);
352 SIG_EXPR_LIST_DECL_DUAL(LHAD2, LPCHC, LPCPLUS);
353 SIG_EXPR_LIST_DECL_SINGLE(NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26));
354 MS_PIN_DECL(B22, GPIOF2, LHAD2, NDSR4);
355 FUNC_GROUP_DECL(NDSR4, B22);
356
357 #define B21 43
358 SIG_EXPR_DECL(LHAD3, LPCHC, LPCHC_DESC);
359 SIG_EXPR_DECL(LHAD3, LPCPLUS, LPCPLUS_DESC);
360 SIG_EXPR_LIST_DECL_DUAL(LHAD3, LPCHC, LPCPLUS);
361 SIG_EXPR_LIST_DECL_SINGLE(NRI4, NRI4, SIG_DESC_SET(SCU80, 27));
362 MS_PIN_DECL(B21, GPIOF3, LHAD3, NRI4);
363 FUNC_GROUP_DECL(NRI4, B21);
364
365 #define A21 44
366 SIG_EXPR_DECL(LHCLK, LPCHC, LPCHC_DESC);
367 SIG_EXPR_DECL(LHCLK, LPCPLUS, LPCPLUS_DESC);
368 SIG_EXPR_LIST_DECL_DUAL(LHCLK, LPCHC, LPCPLUS);
369 SIG_EXPR_LIST_DECL_SINGLE(NDTR4, NDTR4, SIG_DESC_SET(SCU80, 28));
370 MS_PIN_DECL(A21, GPIOF4, LHCLK, NDTR4);
371 FUNC_GROUP_DECL(NDTR4, A21);
372
373 #define H19 45
374 SIG_EXPR_DECL(LHFRAME, LPCHC, LPCHC_DESC);
375 SIG_EXPR_DECL(LHFRAME, LPCPLUS, LPCPLUS_DESC);
376 SIG_EXPR_LIST_DECL_DUAL(LHFRAME, LPCHC, LPCPLUS);
377 SIG_EXPR_LIST_DECL_SINGLE(NRTS4, NRTS4, SIG_DESC_SET(SCU80, 29));
378 MS_PIN_DECL(H19, GPIOF5, LHFRAME, NRTS4);
379 FUNC_GROUP_DECL(NRTS4, H19);
380
381 #define G17 46
382 SIG_EXPR_LIST_DECL_SINGLE(LHSIRQ, LPCHC, LPCHC_DESC);
383 SIG_EXPR_LIST_DECL_SINGLE(TXD4, TXD4, SIG_DESC_SET(SCU80, 30));
384 MS_PIN_DECL(G17, GPIOF6, LHSIRQ, TXD4);
385 FUNC_GROUP_DECL(TXD4, G17);
386
387 #define H18 47
388 SIG_EXPR_DECL(LHRST, LPCHC, LPCHC_DESC);
389 SIG_EXPR_DECL(LHRST, LPCPLUS, LPCPLUS_DESC);
390 SIG_EXPR_LIST_DECL_DUAL(LHRST, LPCHC, LPCPLUS);
391 SIG_EXPR_LIST_DECL_SINGLE(RXD4, RXD4, SIG_DESC_SET(SCU80, 31));
392 MS_PIN_DECL(H18, GPIOF7, LHRST, RXD4);
393 FUNC_GROUP_DECL(RXD4, H18);
394
395 FUNC_GROUP_DECL(LPCHC, J19, J18, B22, B21, A21, H19, G17, H18);
396 FUNC_GROUP_DECL(LPCPLUS, J19, J18, B22, B21, A21, H19, H18);
397
398 #define A19 48
399 SIG_EXPR_LIST_DECL_SINGLE(SGPS1CK, SGPS1, COND1, SIG_DESC_SET(SCU84, 0));
400 SS_PIN_DECL(A19, GPIOG0, SGPS1CK);
401
402 #define E19 49
403 SIG_EXPR_LIST_DECL_SINGLE(SGPS1LD, SGPS1, COND1, SIG_DESC_SET(SCU84, 1));
404 SS_PIN_DECL(E19, GPIOG1, SGPS1LD);
405
406 #define C19 50
407 SIG_EXPR_LIST_DECL_SINGLE(SGPS1I0, SGPS1, COND1, SIG_DESC_SET(SCU84, 2));
408 SS_PIN_DECL(C19, GPIOG2, SGPS1I0);
409
410 #define E16 51
411 SIG_EXPR_LIST_DECL_SINGLE(SGPS1I1, SGPS1, COND1, SIG_DESC_SET(SCU84, 3));
412 SS_PIN_DECL(E16, GPIOG3, SGPS1I1);
413
414 FUNC_GROUP_DECL(SGPS1, A19, E19, C19, E16);
415
416 #define SGPS2_DESC SIG_DESC_SET(SCU94, 12)
417
418 #define E17 52
419 SIG_EXPR_LIST_DECL_SINGLE(SGPS2CK, SGPS2, COND1, SGPS2_DESC);
420 SIG_EXPR_LIST_DECL_SINGLE(SALT1, SALT1, COND1, SIG_DESC_SET(SCU84, 4));
421 MS_PIN_DECL(E17, GPIOG4, SGPS2CK, SALT1);
422 FUNC_GROUP_DECL(SALT1, E17);
423
424 #define D16 53
425 SIG_EXPR_LIST_DECL_SINGLE(SGPS2LD, SGPS2, COND1, SGPS2_DESC);
426 SIG_EXPR_LIST_DECL_SINGLE(SALT2, SALT2, COND1, SIG_DESC_SET(SCU84, 5));
427 MS_PIN_DECL(D16, GPIOG5, SGPS2LD, SALT2);
428 FUNC_GROUP_DECL(SALT2, D16);
429
430 #define D15 54
431 SIG_EXPR_LIST_DECL_SINGLE(SGPS2I0, SGPS2, COND1, SGPS2_DESC);
432 SIG_EXPR_LIST_DECL_SINGLE(SALT3, SALT3, COND1, SIG_DESC_SET(SCU84, 6));
433 MS_PIN_DECL(D15, GPIOG6, SGPS2I0, SALT3);
434 FUNC_GROUP_DECL(SALT3, D15);
435
436 #define E14 55
437 SIG_EXPR_LIST_DECL_SINGLE(SGPS2I1, SGPS2, COND1, SGPS2_DESC);
438 SIG_EXPR_LIST_DECL_SINGLE(SALT4, SALT4, COND1, SIG_DESC_SET(SCU84, 7));
439 MS_PIN_DECL(E14, GPIOG7, SGPS2I1, SALT4);
440 FUNC_GROUP_DECL(SALT4, E14);
441
442 FUNC_GROUP_DECL(SGPS2, E17, D16, D15, E14);
443
444 #define UART6_DESC SIG_DESC_SET(SCU90, 7)
445
446 #define A18 56
447 SIG_EXPR_LIST_DECL_SINGLE(DASHA18, DASHA18, COND1, SIG_DESC_SET(SCU94, 5));
448 SIG_EXPR_LIST_DECL_SINGLE(NCTS6, UART6, COND1, UART6_DESC);
449 MS_PIN_DECL(A18, GPIOH0, DASHA18, NCTS6);
450
451 #define B18 57
452 SIG_EXPR_LIST_DECL_SINGLE(DASHB18, DASHB18, COND1, SIG_DESC_SET(SCU94, 5));
453 SIG_EXPR_LIST_DECL_SINGLE(NDCD6, UART6, COND1, UART6_DESC);
454 MS_PIN_DECL(B18, GPIOH1, DASHB18, NDCD6);
455
456 #define D17 58
457 SIG_EXPR_LIST_DECL_SINGLE(DASHD17, DASHD17, COND1, SIG_DESC_SET(SCU94, 6));
458 SIG_EXPR_LIST_DECL_SINGLE(NDSR6, UART6, COND1, UART6_DESC);
459 MS_PIN_DECL(D17, GPIOH2, DASHD17, NDSR6);
460
461 #define C17 59
462 SIG_EXPR_LIST_DECL_SINGLE(DASHC17, DASHC17, COND1, SIG_DESC_SET(SCU94, 6));
463 SIG_EXPR_LIST_DECL_SINGLE(NRI6, UART6, COND1, UART6_DESC);
464 MS_PIN_DECL(C17, GPIOH3, DASHC17, NRI6);
465
466 #define A17 60
467 SIG_EXPR_LIST_DECL_SINGLE(DASHA17, DASHA17, COND1, SIG_DESC_SET(SCU94, 7));
468 SIG_EXPR_LIST_DECL_SINGLE(NDTR6, UART6, COND1, UART6_DESC);
469 MS_PIN_DECL(A17, GPIOH4, DASHA17, NDTR6);
470
471 #define B17 61
472 SIG_EXPR_LIST_DECL_SINGLE(DASHB17, DASHB17, COND1, SIG_DESC_SET(SCU94, 7));
473 SIG_EXPR_LIST_DECL_SINGLE(NRTS6, UART6, COND1, UART6_DESC);
474 MS_PIN_DECL(B17, GPIOH5, DASHB17, NRTS6);
475
476 #define A16 62
477 SIG_EXPR_LIST_DECL_SINGLE(TXD6, UART6, COND1, UART6_DESC);
478 SS_PIN_DECL(A16, GPIOH6, TXD6);
479
480 #define D18 63
481 SIG_EXPR_LIST_DECL_SINGLE(RXD6, UART6, COND1, UART6_DESC);
482 SS_PIN_DECL(D18, GPIOH7, RXD6);
483
484 FUNC_GROUP_DECL(UART6, A18, B18, D17, C17, A17, B17, A16, D18);
485
486 #define SPI1_DESC \
487 { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 }
488 #define SPI1DEBUG_DESC \
489 { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 }
490 #define SPI1PASSTHRU_DESC \
491 { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 }
492
493 #define C18 64
494 SIG_EXPR_DECL(SYSCS, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
495 SIG_EXPR_DECL(SYSCS, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
496 SIG_EXPR_LIST_DECL_DUAL(SYSCS, SPI1DEBUG, SPI1PASSTHRU);
497 SS_PIN_DECL(C18, GPIOI0, SYSCS);
498
499 #define E15 65
500 SIG_EXPR_DECL(SYSCK, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
501 SIG_EXPR_DECL(SYSCK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
502 SIG_EXPR_LIST_DECL_DUAL(SYSCK, SPI1DEBUG, SPI1PASSTHRU);
503 SS_PIN_DECL(E15, GPIOI1, SYSCK);
504
505 #define B16 66
506 SIG_EXPR_DECL(SYSMOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
507 SIG_EXPR_DECL(SYSMOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
508 SIG_EXPR_LIST_DECL_DUAL(SYSMOSI, SPI1DEBUG, SPI1PASSTHRU);
509 SS_PIN_DECL(B16, GPIOI2, SYSMOSI);
510
511 #define C16 67
512 SIG_EXPR_DECL(SYSMISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
513 SIG_EXPR_DECL(SYSMISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
514 SIG_EXPR_LIST_DECL_DUAL(SYSMISO, SPI1DEBUG, SPI1PASSTHRU);
515 SS_PIN_DECL(C16, GPIOI3, SYSMISO);
516
517 #define VB_DESC SIG_DESC_SET(HW_STRAP1, 5)
518
519 #define B15 68
520 SIG_EXPR_DECL(SPI1CS0, SPI1, COND1, SPI1_DESC);
521 SIG_EXPR_DECL(SPI1CS0, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
522 SIG_EXPR_DECL(SPI1CS0, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
523 SIG_EXPR_LIST_DECL(SPI1CS0, SIG_EXPR_PTR(SPI1CS0, SPI1),
524 SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG),
525 SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU));
526 SIG_EXPR_LIST_DECL_SINGLE(VBCS, VGABIOSROM, COND1, VB_DESC);
527 MS_PIN_DECL(B15, GPIOI4, SPI1CS0, VBCS);
528
529 #define C15 69
530 SIG_EXPR_DECL(SPI1CK, SPI1, COND1, SPI1_DESC);
531 SIG_EXPR_DECL(SPI1CK, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
532 SIG_EXPR_DECL(SPI1CK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
533 SIG_EXPR_LIST_DECL(SPI1CK, SIG_EXPR_PTR(SPI1CK, SPI1),
534 SIG_EXPR_PTR(SPI1CK, SPI1DEBUG),
535 SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU));
536 SIG_EXPR_LIST_DECL_SINGLE(VBCK, VGABIOSROM, COND1, VB_DESC);
537 MS_PIN_DECL(C15, GPIOI5, SPI1CK, VBCK);
538
539 #define A14 70
540 SIG_EXPR_DECL(SPI1MOSI, SPI1, COND1, SPI1_DESC);
541 SIG_EXPR_DECL(SPI1MOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
542 SIG_EXPR_DECL(SPI1MOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
543 SIG_EXPR_LIST_DECL(SPI1MOSI, SIG_EXPR_PTR(SPI1MOSI, SPI1),
544 SIG_EXPR_PTR(SPI1MOSI, SPI1DEBUG),
545 SIG_EXPR_PTR(SPI1MOSI, SPI1PASSTHRU));
546 SIG_EXPR_LIST_DECL_SINGLE(VBMOSI, VGABIOSROM, COND1, VB_DESC);
547 MS_PIN_DECL(A14, GPIOI6, SPI1MOSI, VBMOSI);
548
549 #define A15 71
550 SIG_EXPR_DECL(SPI1MISO, SPI1, COND1, SPI1_DESC);
551 SIG_EXPR_DECL(SPI1MISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
552 SIG_EXPR_DECL(SPI1MISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
553 SIG_EXPR_LIST_DECL(SPI1MISO, SIG_EXPR_PTR(SPI1MISO, SPI1),
554 SIG_EXPR_PTR(SPI1MISO, SPI1DEBUG),
555 SIG_EXPR_PTR(SPI1MISO, SPI1PASSTHRU));
556 SIG_EXPR_LIST_DECL_SINGLE(VBMISO, VGABIOSROM, COND1, VB_DESC);
557 MS_PIN_DECL(A15, GPIOI7, SPI1MISO, VBMISO);
558
559 FUNC_GROUP_DECL(SPI1, B15, C15, A14, A15);
560 FUNC_GROUP_DECL(SPI1DEBUG, C18, E15, B16, C16, B15, C15, A14, A15);
561 FUNC_GROUP_DECL(SPI1PASSTHRU, C18, E15, B16, C16, B15, C15, A14, A15);
562 FUNC_GROUP_DECL(VGABIOSROM, B15, C15, A14, A15);
563
564 #define R2 72
565 SIG_EXPR_LIST_DECL_SINGLE(SGPMCK, SGPM, SIG_DESC_SET(SCU84, 8));
566 SS_PIN_DECL(R2, GPIOJ0, SGPMCK);
567
568 #define L2 73
569 SIG_EXPR_LIST_DECL_SINGLE(SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9));
570 SS_PIN_DECL(L2, GPIOJ1, SGPMLD);
571
572 #define N3 74
573 SIG_EXPR_LIST_DECL_SINGLE(SGPMO, SGPM, SIG_DESC_SET(SCU84, 10));
574 SS_PIN_DECL(N3, GPIOJ2, SGPMO);
575
576 #define N4 75
577 SIG_EXPR_LIST_DECL_SINGLE(SGPMI, SGPM, SIG_DESC_SET(SCU84, 11));
578 SS_PIN_DECL(N4, GPIOJ3, SGPMI);
579
580 #define N5 76
581 SIG_EXPR_LIST_DECL_SINGLE(VGAHS, VGAHS, SIG_DESC_SET(SCU84, 12));
582 SIG_EXPR_LIST_DECL_SINGLE(DASHN5, DASHN5, SIG_DESC_SET(SCU94, 8));
583 MS_PIN_DECL(N5, GPIOJ4, VGAHS, DASHN5);
584 FUNC_GROUP_DECL(VGAHS, N5);
585
586 #define R4 77
587 SIG_EXPR_LIST_DECL_SINGLE(VGAVS, VGAVS, SIG_DESC_SET(SCU84, 13));
588 SIG_EXPR_LIST_DECL_SINGLE(DASHR4, DASHR4, SIG_DESC_SET(SCU94, 8));
589 MS_PIN_DECL(R4, GPIOJ5, VGAVS, DASHR4);
590 FUNC_GROUP_DECL(VGAVS, R4);
591
592 #define R3 78
593 SIG_EXPR_LIST_DECL_SINGLE(DDCCLK, DDCCLK, SIG_DESC_SET(SCU84, 14));
594 SIG_EXPR_LIST_DECL_SINGLE(DASHR3, DASHR3, SIG_DESC_SET(SCU94, 9));
595 MS_PIN_DECL(R3, GPIOJ6, DDCCLK, DASHR3);
596 FUNC_GROUP_DECL(DDCCLK, R3);
597
598 #define T3 79
599 SIG_EXPR_LIST_DECL_SINGLE(DDCDAT, DDCDAT, SIG_DESC_SET(SCU84, 15));
600 SIG_EXPR_LIST_DECL_SINGLE(DASHT3, DASHT3, SIG_DESC_SET(SCU94, 9));
601 MS_PIN_DECL(T3, GPIOJ7, DDCDAT, DASHT3);
602 FUNC_GROUP_DECL(DDCDAT, T3);
603
604 #define I2C5_DESC SIG_DESC_SET(SCU90, 18)
605
606 #define L3 80
607 SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC);
608 SS_PIN_DECL(L3, GPIOK0, SCL5);
609
610 #define L4 81
611 SIG_EXPR_LIST_DECL_SINGLE(SDA5, I2C5, I2C5_DESC);
612 SS_PIN_DECL(L4, GPIOK1, SDA5);
613
614 FUNC_GROUP_DECL(I2C5, L3, L4);
615
616 #define I2C6_DESC SIG_DESC_SET(SCU90, 19)
617
618 #define L1 82
619 SIG_EXPR_LIST_DECL_SINGLE(SCL6, I2C6, I2C6_DESC);
620 SS_PIN_DECL(L1, GPIOK2, SCL6);
621
622 #define N2 83
623 SIG_EXPR_LIST_DECL_SINGLE(SDA6, I2C6, I2C6_DESC);
624 SS_PIN_DECL(N2, GPIOK3, SDA6);
625
626 FUNC_GROUP_DECL(I2C6, L1, N2);
627
628 #define I2C7_DESC SIG_DESC_SET(SCU90, 20)
629
630 #define N1 84
631 SIG_EXPR_LIST_DECL_SINGLE(SCL7, I2C7, I2C7_DESC);
632 SS_PIN_DECL(N1, GPIOK4, SCL7);
633
634 #define P1 85
635 SIG_EXPR_LIST_DECL_SINGLE(SDA7, I2C7, I2C7_DESC);
636 SS_PIN_DECL(P1, GPIOK5, SDA7);
637
638 FUNC_GROUP_DECL(I2C7, N1, P1);
639
640 #define I2C8_DESC SIG_DESC_SET(SCU90, 21)
641
642 #define P2 86
643 SIG_EXPR_LIST_DECL_SINGLE(SCL8, I2C8, I2C8_DESC);
644 SS_PIN_DECL(P2, GPIOK6, SCL8);
645
646 #define R1 87
647 SIG_EXPR_LIST_DECL_SINGLE(SDA8, I2C8, I2C8_DESC);
648 SS_PIN_DECL(R1, GPIOK7, SDA8);
649
650 FUNC_GROUP_DECL(I2C8, P2, R1);
651
652 #define T2 88
653 SSSF_PIN_DECL(T2, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16));
654
655 #define VPIOFF0_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 0, 0 }
656 #define VPIOFF1_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 }
657 #define VPI24_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 }
658 #define VPIRSVD_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 }
659 #define VPI_24_RSVD_DESC SIG_DESC_SET(SCU90, 5)
660
661 #define T1 89
662 #define T1_DESC SIG_DESC_SET(SCU84, 17)
663 SIG_EXPR_LIST_DECL_SINGLE(VPIDE, VPI24, VPI_24_RSVD_DESC, T1_DESC, COND2);
664 SIG_EXPR_LIST_DECL_SINGLE(NDCD1, NDCD1, T1_DESC, COND2);
665 MS_PIN_DECL(T1, GPIOL1, VPIDE, NDCD1);
666 FUNC_GROUP_DECL(NDCD1, T1);
667
668 #define U1 90
669 #define U1_DESC SIG_DESC_SET(SCU84, 18)
670 SIG_EXPR_LIST_DECL_SINGLE(DASHU1, VPI24, VPI_24_RSVD_DESC, U1_DESC);
671 SIG_EXPR_LIST_DECL_SINGLE(NDSR1, NDSR1, U1_DESC);
672 MS_PIN_DECL(U1, GPIOL2, DASHU1, NDSR1);
673 FUNC_GROUP_DECL(NDSR1, U1);
674
675 #define U2 91
676 #define U2_DESC SIG_DESC_SET(SCU84, 19)
677 SIG_EXPR_LIST_DECL_SINGLE(VPIHS, VPI24, VPI_24_RSVD_DESC, U2_DESC, COND2);
678 SIG_EXPR_LIST_DECL_SINGLE(NRI1, NRI1, U2_DESC, COND2);
679 MS_PIN_DECL(U2, GPIOL3, VPIHS, NRI1);
680 FUNC_GROUP_DECL(NRI1, U2);
681
682 #define P4 92
683 #define P4_DESC SIG_DESC_SET(SCU84, 20)
684 SIG_EXPR_LIST_DECL_SINGLE(VPIVS, VPI24, VPI_24_RSVD_DESC, P4_DESC, COND2);
685 SIG_EXPR_LIST_DECL_SINGLE(NDTR1, NDTR1, P4_DESC, COND2);
686 MS_PIN_DECL(P4, GPIOL4, VPIVS, NDTR1);
687 FUNC_GROUP_DECL(NDTR1, P4);
688
689 #define P3 93
690 #define P3_DESC SIG_DESC_SET(SCU84, 21)
691 SIG_EXPR_LIST_DECL_SINGLE(VPICLK, VPI24, VPI_24_RSVD_DESC, P3_DESC, COND2);
692 SIG_EXPR_LIST_DECL_SINGLE(NRTS1, NRTS1, P3_DESC, COND2);
693 MS_PIN_DECL(P3, GPIOL5, VPICLK, NRTS1);
694 FUNC_GROUP_DECL(NRTS1, P3);
695
696 #define V1 94
697 #define V1_DESC SIG_DESC_SET(SCU84, 22)
698 SIG_EXPR_LIST_DECL_SINGLE(DASHV1, DASHV1, VPIRSVD_DESC, V1_DESC);
699 SIG_EXPR_LIST_DECL_SINGLE(TXD1, TXD1, V1_DESC, COND2);
700 MS_PIN_DECL(V1, GPIOL6, DASHV1, TXD1);
701 FUNC_GROUP_DECL(TXD1, V1);
702
703 #define W1 95
704 #define W1_DESC SIG_DESC_SET(SCU84, 23)
705 SIG_EXPR_LIST_DECL_SINGLE(DASHW1, DASHW1, VPIRSVD_DESC, W1_DESC);
706 SIG_EXPR_LIST_DECL_SINGLE(RXD1, RXD1, W1_DESC, COND2);
707 MS_PIN_DECL(W1, GPIOL7, DASHW1, RXD1);
708 FUNC_GROUP_DECL(RXD1, W1);
709
710 #define Y1 96
711 #define Y1_DESC SIG_DESC_SET(SCU84, 24)
712 SIG_EXPR_LIST_DECL_SINGLE(VPIB2, VPI24, VPI_24_RSVD_DESC, Y1_DESC, COND2);
713 SIG_EXPR_LIST_DECL_SINGLE(NCTS2, NCTS2, Y1_DESC, COND2);
714 MS_PIN_DECL(Y1, GPIOM0, VPIB2, NCTS2);
715 FUNC_GROUP_DECL(NCTS2, Y1);
716
717 #define AB2 97
718 #define AB2_DESC SIG_DESC_SET(SCU84, 25)
719 SIG_EXPR_LIST_DECL_SINGLE(VPIB3, VPI24, VPI_24_RSVD_DESC, AB2_DESC, COND2);
720 SIG_EXPR_LIST_DECL_SINGLE(NDCD2, NDCD2, AB2_DESC, COND2);
721 MS_PIN_DECL(AB2, GPIOM1, VPIB3, NDCD2);
722 FUNC_GROUP_DECL(NDCD2, AB2);
723
724 #define AA1 98
725 #define AA1_DESC SIG_DESC_SET(SCU84, 26)
726 SIG_EXPR_LIST_DECL_SINGLE(VPIB4, VPI24, VPI_24_RSVD_DESC, AA1_DESC, COND2);
727 SIG_EXPR_LIST_DECL_SINGLE(NDSR2, NDSR2, AA1_DESC, COND2);
728 MS_PIN_DECL(AA1, GPIOM2, VPIB4, NDSR2);
729 FUNC_GROUP_DECL(NDSR2, AA1);
730
731 #define Y2 99
732 #define Y2_DESC SIG_DESC_SET(SCU84, 27)
733 SIG_EXPR_LIST_DECL_SINGLE(VPIB5, VPI24, VPI_24_RSVD_DESC, Y2_DESC, COND2);
734 SIG_EXPR_LIST_DECL_SINGLE(NRI2, NRI2, Y2_DESC, COND2);
735 MS_PIN_DECL(Y2, GPIOM3, VPIB5, NRI2);
736 FUNC_GROUP_DECL(NRI2, Y2);
737
738 #define AA2 100
739 #define AA2_DESC SIG_DESC_SET(SCU84, 28)
740 SIG_EXPR_LIST_DECL_SINGLE(VPIB6, VPI24, VPI_24_RSVD_DESC, AA2_DESC, COND2);
741 SIG_EXPR_LIST_DECL_SINGLE(NDTR2, NDTR2, AA2_DESC, COND2);
742 MS_PIN_DECL(AA2, GPIOM4, VPIB6, NDTR2);
743 FUNC_GROUP_DECL(NDTR2, AA2);
744
745 #define P5 101
746 #define P5_DESC SIG_DESC_SET(SCU84, 29)
747 SIG_EXPR_LIST_DECL_SINGLE(VPIB7, VPI24, VPI_24_RSVD_DESC, P5_DESC, COND2);
748 SIG_EXPR_LIST_DECL_SINGLE(NRTS2, NRTS2, P5_DESC, COND2);
749 MS_PIN_DECL(P5, GPIOM5, VPIB7, NRTS2);
750 FUNC_GROUP_DECL(NRTS2, P5);
751
752 #define R5 102
753 #define R5_DESC SIG_DESC_SET(SCU84, 30)
754 SIG_EXPR_LIST_DECL_SINGLE(VPIB8, VPI24, VPI_24_RSVD_DESC, R5_DESC, COND2);
755 SIG_EXPR_LIST_DECL_SINGLE(TXD2, TXD2, R5_DESC, COND2);
756 MS_PIN_DECL(R5, GPIOM6, VPIB8, TXD2);
757 FUNC_GROUP_DECL(TXD2, R5);
758
759 #define T5 103
760 #define T5_DESC SIG_DESC_SET(SCU84, 31)
761 SIG_EXPR_LIST_DECL_SINGLE(VPIB9, VPI24, VPI_24_RSVD_DESC, T5_DESC, COND2);
762 SIG_EXPR_LIST_DECL_SINGLE(RXD2, RXD2, T5_DESC, COND2);
763 MS_PIN_DECL(T5, GPIOM7, VPIB9, RXD2);
764 FUNC_GROUP_DECL(RXD2, T5);
765
766 #define V2 104
767 #define V2_DESC SIG_DESC_SET(SCU88, 0)
768 SIG_EXPR_LIST_DECL_SINGLE(DASHN0, DASHN0, VPIRSVD_DESC, V2_DESC);
769 SIG_EXPR_LIST_DECL_SINGLE(PWM0, PWM0, V2_DESC, COND2);
770 MS_PIN_DECL(V2, GPION0, DASHN0, PWM0);
771 FUNC_GROUP_DECL(PWM0, V2);
772
773 #define W2 105
774 #define W2_DESC SIG_DESC_SET(SCU88, 1)
775 SIG_EXPR_LIST_DECL_SINGLE(DASHN1, DASHN1, VPIRSVD_DESC, W2_DESC);
776 SIG_EXPR_LIST_DECL_SINGLE(PWM1, PWM1, W2_DESC, COND2);
777 MS_PIN_DECL(W2, GPION1, DASHN1, PWM1);
778 FUNC_GROUP_DECL(PWM1, W2);
779
780 #define V3 106
781 #define V3_DESC SIG_DESC_SET(SCU88, 2)
782 SIG_EXPR_DECL(VPIG2, VPI24, VPI24_DESC, V3_DESC, COND2);
783 SIG_EXPR_DECL(VPIG2, VPIRSVD, VPIRSVD_DESC, V3_DESC, COND2);
784 SIG_EXPR_LIST_DECL_DUAL(VPIG2, VPI24, VPIRSVD);
785 SIG_EXPR_LIST_DECL_SINGLE(PWM2, PWM2, V3_DESC, COND2);
786 MS_PIN_DECL(V3, GPION2, VPIG2, PWM2);
787 FUNC_GROUP_DECL(PWM2, V3);
788
789 #define U3 107
790 #define U3_DESC SIG_DESC_SET(SCU88, 3)
791 SIG_EXPR_DECL(VPIG3, VPI24, VPI24_DESC, U3_DESC, COND2);
792 SIG_EXPR_DECL(VPIG3, VPIRSVD, VPIRSVD_DESC, U3_DESC, COND2);
793 SIG_EXPR_LIST_DECL_DUAL(VPIG3, VPI24, VPIRSVD);
794 SIG_EXPR_LIST_DECL_SINGLE(PWM3, PWM3, U3_DESC, COND2);
795 MS_PIN_DECL(U3, GPION3, VPIG3, PWM3);
796 FUNC_GROUP_DECL(PWM3, U3);
797
798 #define W3 108
799 #define W3_DESC SIG_DESC_SET(SCU88, 4)
800 SIG_EXPR_DECL(VPIG4, VPI24, VPI24_DESC, W3_DESC, COND2);
801 SIG_EXPR_DECL(VPIG4, VPIRSVD, VPIRSVD_DESC, W3_DESC, COND2);
802 SIG_EXPR_LIST_DECL_DUAL(VPIG4, VPI24, VPIRSVD);
803 SIG_EXPR_LIST_DECL_SINGLE(PWM4, PWM4, W3_DESC, COND2);
804 MS_PIN_DECL(W3, GPION4, VPIG4, PWM4);
805 FUNC_GROUP_DECL(PWM4, W3);
806
807 #define AA3 109
808 #define AA3_DESC SIG_DESC_SET(SCU88, 5)
809 SIG_EXPR_DECL(VPIG5, VPI24, VPI24_DESC, AA3_DESC, COND2);
810 SIG_EXPR_DECL(VPIG5, VPIRSVD, VPIRSVD_DESC, AA3_DESC, COND2);
811 SIG_EXPR_LIST_DECL_DUAL(VPIG5, VPI24, VPIRSVD);
812 SIG_EXPR_LIST_DECL_SINGLE(PWM5, PWM5, AA3_DESC, COND2);
813 MS_PIN_DECL(AA3, GPION5, VPIG5, PWM5);
814 FUNC_GROUP_DECL(PWM5, AA3);
815
816 #define Y3 110
817 #define Y3_DESC SIG_DESC_SET(SCU88, 6)
818 SIG_EXPR_LIST_DECL_SINGLE(VPIG6, VPI24, VPI24_DESC, Y3_DESC);
819 SIG_EXPR_LIST_DECL_SINGLE(PWM6, PWM6, Y3_DESC, COND2);
820 MS_PIN_DECL(Y3, GPION6, VPIG6, PWM6);
821 FUNC_GROUP_DECL(PWM6, Y3);
822
823 #define T4 111
824 #define T4_DESC SIG_DESC_SET(SCU88, 7)
825 SIG_EXPR_LIST_DECL_SINGLE(VPIG7, VPI24, VPI24_DESC, T4_DESC);
826 SIG_EXPR_LIST_DECL_SINGLE(PWM7, PWM7, T4_DESC, COND2);
827 MS_PIN_DECL(T4, GPION7, VPIG7, PWM7);
828 FUNC_GROUP_DECL(PWM7, T4);
829
830 #define U5 112
831 SIG_EXPR_LIST_DECL_SINGLE(VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8),
832 COND2);
833 SS_PIN_DECL(U5, GPIOO0, VPIG8);
834
835 #define U4 113
836 SIG_EXPR_LIST_DECL_SINGLE(VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9),
837 COND2);
838 SS_PIN_DECL(U4, GPIOO1, VPIG9);
839
840 #define V5 114
841 SIG_EXPR_LIST_DECL_SINGLE(DASHV5, DASHV5, VPI_24_RSVD_DESC,
842 SIG_DESC_SET(SCU88, 10));
843 SS_PIN_DECL(V5, GPIOO2, DASHV5);
844
845 #define AB4 115
846 SIG_EXPR_LIST_DECL_SINGLE(DASHAB4, DASHAB4, VPI_24_RSVD_DESC,
847 SIG_DESC_SET(SCU88, 11));
848 SS_PIN_DECL(AB4, GPIOO3, DASHAB4);
849
850 #define AB3 116
851 SIG_EXPR_LIST_DECL_SINGLE(VPIR2, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 12),
852 COND2);
853 SS_PIN_DECL(AB3, GPIOO4, VPIR2);
854
855 #define Y4 117
856 SIG_EXPR_LIST_DECL_SINGLE(VPIR3, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 13),
857 COND2);
858 SS_PIN_DECL(Y4, GPIOO5, VPIR3);
859
860 #define AA4 118
861 SIG_EXPR_LIST_DECL_SINGLE(VPIR4, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 14),
862 COND2);
863 SS_PIN_DECL(AA4, GPIOO6, VPIR4);
864
865 #define W4 119
866 SIG_EXPR_LIST_DECL_SINGLE(VPIR5, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 15),
867 COND2);
868 SS_PIN_DECL(W4, GPIOO7, VPIR5);
869
870 #define V4 120
871 SIG_EXPR_LIST_DECL_SINGLE(VPIR6, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 16),
872 COND2);
873 SS_PIN_DECL(V4, GPIOP0, VPIR6);
874
875 #define W5 121
876 SIG_EXPR_LIST_DECL_SINGLE(VPIR7, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 17),
877 COND2);
878 SS_PIN_DECL(W5, GPIOP1, VPIR7);
879
880 #define AA5 122
881 SIG_EXPR_LIST_DECL_SINGLE(VPIR8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 18),
882 COND2);
883 SS_PIN_DECL(AA5, GPIOP2, VPIR8);
884
885 #define AB5 123
886 SIG_EXPR_LIST_DECL_SINGLE(VPIR9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 19),
887 COND2);
888 SS_PIN_DECL(AB5, GPIOP3, VPIR9);
889
890 FUNC_GROUP_DECL(VPI24, T1, U2, P4, P3, Y1, AB2, AA1, Y2, AA2, P5, R5, T5, V3,
891 U3, W3, AA3, Y3, T4, U5, U4, AB3, Y4, AA4, W4, V4, W5, AA5,
892 AB5);
893
894 #define Y6 124
895 SIG_EXPR_LIST_DECL_SINGLE(DASHY6, DASHY6, SIG_DESC_SET(SCU90, 28),
896 SIG_DESC_SET(SCU88, 20));
897 SS_PIN_DECL(Y6, GPIOP4, DASHY6);
898
899 #define Y5 125
900 SIG_EXPR_LIST_DECL_SINGLE(DASHY5, DASHY5, SIG_DESC_SET(SCU90, 28),
901 SIG_DESC_SET(SCU88, 21));
902 SS_PIN_DECL(Y5, GPIOP5, DASHY5);
903
904 #define W6 126
905 SIG_EXPR_LIST_DECL_SINGLE(DASHW6, DASHW6, SIG_DESC_SET(SCU90, 28),
906 SIG_DESC_SET(SCU88, 22));
907 SS_PIN_DECL(W6, GPIOP6, DASHW6);
908
909 #define V6 127
910 SIG_EXPR_LIST_DECL_SINGLE(DASHV6, DASHV6, SIG_DESC_SET(SCU90, 28),
911 SIG_DESC_SET(SCU88, 23));
912 SS_PIN_DECL(V6, GPIOP7, DASHV6);
913
914 #define I2C3_DESC SIG_DESC_SET(SCU90, 16)
915
916 #define A11 128
917 SIG_EXPR_LIST_DECL_SINGLE(SCL3, I2C3, I2C3_DESC);
918 SS_PIN_DECL(A11, GPIOQ0, SCL3);
919
920 #define A10 129
921 SIG_EXPR_LIST_DECL_SINGLE(SDA3, I2C3, I2C3_DESC);
922 SS_PIN_DECL(A10, GPIOQ1, SDA3);
923
924 FUNC_GROUP_DECL(I2C3, A11, A10);
925
926 #define I2C4_DESC SIG_DESC_SET(SCU90, 17)
927
928 #define A9 130
929 SIG_EXPR_LIST_DECL_SINGLE(SCL4, I2C4, I2C4_DESC);
930 SS_PIN_DECL(A9, GPIOQ2, SCL4);
931
932 #define B9 131
933 SIG_EXPR_LIST_DECL_SINGLE(SDA4, I2C4, I2C4_DESC);
934 SS_PIN_DECL(B9, GPIOQ3, SDA4);
935
936 FUNC_GROUP_DECL(I2C4, A9, B9);
937
938 #define I2C14_DESC SIG_DESC_SET(SCU90, 27)
939
940 #define N21 132
941 SIG_EXPR_LIST_DECL_SINGLE(SCL14, I2C14, I2C14_DESC);
942 SS_PIN_DECL(N21, GPIOQ4, SCL14);
943
944 #define N22 133
945 SIG_EXPR_LIST_DECL_SINGLE(SDA14, I2C14, I2C14_DESC);
946 SS_PIN_DECL(N22, GPIOQ5, SDA14);
947
948 FUNC_GROUP_DECL(I2C14, N21, N22);
949
950 #define B10 134
951 SSSF_PIN_DECL(B10, GPIOQ6, OSCCLK, SIG_DESC_SET(SCU2C, 1));
952
953 #define N20 135
954 SSSF_PIN_DECL(N20, GPIOQ7, PEWAKE, SIG_DESC_SET(SCU2C, 29));
955
956 #define AA19 136
957 SSSF_PIN_DECL(AA19, GPIOR0, FWSPICS1, SIG_DESC_SET(SCU88, 24), COND2);
958
959 #define T19 137
960 SSSF_PIN_DECL(T19, GPIOR1, FWSPICS2, SIG_DESC_SET(SCU88, 25), COND2);
961
962 #define T17 138
963 SSSF_PIN_DECL(T17, GPIOR2, SPI2CS0, SIG_DESC_SET(SCU88, 26), COND2);
964
965 #define Y19 139
966 SSSF_PIN_DECL(Y19, GPIOR3, SPI2CK, SIG_DESC_SET(SCU88, 27), COND2);
967
968 #define W19 140
969 SSSF_PIN_DECL(W19, GPIOR4, SPI2MOSI, SIG_DESC_SET(SCU88, 28), COND2);
970
971 #define V19 141
972 SSSF_PIN_DECL(V19, GPIOR5, SPI2MISO, SIG_DESC_SET(SCU88, 29), COND2);
973
974 #define D8 142
975 SIG_EXPR_LIST_DECL_SINGLE(MDC1, MDIO1, SIG_DESC_SET(SCU88, 30));
976 SS_PIN_DECL(D8, GPIOR6, MDC1);
977
978 #define E10 143
979 SIG_EXPR_LIST_DECL_SINGLE(MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31));
980 SS_PIN_DECL(E10, GPIOR7, MDIO1);
981
982 FUNC_GROUP_DECL(MDIO1, D8, E10);
983
984 #define VPOOFF0_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
985 #define VPO_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 }
986 #define VPOOFF1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 }
987 #define VPOOFF2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 }
988
989 #define CRT_DVO_EN_DESC SIG_DESC_IP_SET(ASPEED_IP_GFX, GFX064, 7)
990
991 #define V20 144
992 #define V20_DESC SIG_DESC_SET(SCU8C, 0)
993 SIG_EXPR_DECL(VPOB2, VPO, V20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
994 SIG_EXPR_DECL(VPOB2, VPOOFF1, V20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
995 SIG_EXPR_DECL(VPOB2, VPOOFF2, V20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
996 SIG_EXPR_LIST_DECL(VPOB2, SIG_EXPR_PTR(VPOB2, VPO),
997 SIG_EXPR_PTR(VPOB2, VPOOFF1), SIG_EXPR_PTR(VPOB2, VPOOFF2));
998 SIG_EXPR_LIST_DECL_SINGLE(SPI2CS1, SPI2CS1, V20_DESC);
999 MS_PIN_DECL(V20, GPIOS0, VPOB2, SPI2CS1);
1000 FUNC_GROUP_DECL(SPI2CS1, V20);
1001
1002 #define U19 145
1003 #define U19_DESC SIG_DESC_SET(SCU8C, 1)
1004 SIG_EXPR_DECL(VPOB3, VPO, U19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1005 SIG_EXPR_DECL(VPOB3, VPOOFF1, U19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1006 SIG_EXPR_DECL(VPOB3, VPOOFF2, U19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1007 SIG_EXPR_LIST_DECL(VPOB3, SIG_EXPR_PTR(VPOB3, VPO),
1008 SIG_EXPR_PTR(VPOB3, VPOOFF1), SIG_EXPR_PTR(VPOB3, VPOOFF2));
1009 SIG_EXPR_LIST_DECL_SINGLE(BMCINT, BMCINT, U19_DESC);
1010 MS_PIN_DECL(U19, GPIOS1, VPOB3, BMCINT);
1011 FUNC_GROUP_DECL(BMCINT, U19);
1012
1013 #define R18 146
1014 #define R18_DESC SIG_DESC_SET(SCU8C, 2)
1015 SIG_EXPR_DECL(VPOB4, VPO, R18_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1016 SIG_EXPR_DECL(VPOB4, VPOOFF1, R18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1017 SIG_EXPR_DECL(VPOB4, VPOOFF2, R18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1018 SIG_EXPR_LIST_DECL(VPOB4, SIG_EXPR_PTR(VPOB4, VPO),
1019 SIG_EXPR_PTR(VPOB4, VPOOFF1), SIG_EXPR_PTR(VPOB4, VPOOFF2));
1020 SIG_EXPR_LIST_DECL_SINGLE(SALT5, SALT5, R18_DESC);
1021 MS_PIN_DECL(R18, GPIOS2, VPOB4, SALT5);
1022 FUNC_GROUP_DECL(SALT5, R18);
1023
1024 #define P18 147
1025 #define P18_DESC SIG_DESC_SET(SCU8C, 3)
1026 SIG_EXPR_DECL(VPOB5, VPO, P18_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1027 SIG_EXPR_DECL(VPOB5, VPOOFF1, P18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1028 SIG_EXPR_DECL(VPOB5, VPOOFF2, P18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1029 SIG_EXPR_LIST_DECL(VPOB5, SIG_EXPR_PTR(VPOB5, VPO),
1030 SIG_EXPR_PTR(VPOB5, VPOOFF1), SIG_EXPR_PTR(VPOB5, VPOOFF2));
1031 SIG_EXPR_LIST_DECL_SINGLE(SALT6, SALT6, P18_DESC);
1032 MS_PIN_DECL(P18, GPIOS3, VPOB5, SALT6);
1033 FUNC_GROUP_DECL(SALT6, P18);
1034
1035 #define R19 148
1036 #define R19_DESC SIG_DESC_SET(SCU8C, 4)
1037 SIG_EXPR_DECL(VPOB6, VPO, R19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1038 SIG_EXPR_DECL(VPOB6, VPOOFF1, R19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1039 SIG_EXPR_DECL(VPOB6, VPOOFF2, R19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1040 SIG_EXPR_LIST_DECL(VPOB6, SIG_EXPR_PTR(VPOB6, VPO),
1041 SIG_EXPR_PTR(VPOB6, VPOOFF1), SIG_EXPR_PTR(VPOB6, VPOOFF2));
1042 SS_PIN_DECL(R19, GPIOS4, VPOB6);
1043
1044 #define W20 149
1045 #define W20_DESC SIG_DESC_SET(SCU8C, 5)
1046 SIG_EXPR_DECL(VPOB7, VPO, W20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1047 SIG_EXPR_DECL(VPOB7, VPOOFF1, W20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1048 SIG_EXPR_DECL(VPOB7, VPOOFF2, W20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1049 SIG_EXPR_LIST_DECL(VPOB7, SIG_EXPR_PTR(VPOB7, VPO),
1050 SIG_EXPR_PTR(VPOB7, VPOOFF1), SIG_EXPR_PTR(VPOB7, VPOOFF2));
1051 SS_PIN_DECL(W20, GPIOS5, VPOB7);
1052
1053 #define U20 150
1054 #define U20_DESC SIG_DESC_SET(SCU8C, 6)
1055 SIG_EXPR_DECL(VPOB8, VPO, U20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1056 SIG_EXPR_DECL(VPOB8, VPOOFF1, U20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1057 SIG_EXPR_DECL(VPOB8, VPOOFF2, U20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1058 SIG_EXPR_LIST_DECL(VPOB8, SIG_EXPR_PTR(VPOB8, VPO),
1059 SIG_EXPR_PTR(VPOB8, VPOOFF1), SIG_EXPR_PTR(VPOB8, VPOOFF2));
1060 SS_PIN_DECL(U20, GPIOS6, VPOB8);
1061
1062 #define AA20 151
1063 #define AA20_DESC SIG_DESC_SET(SCU8C, 7)
1064 SIG_EXPR_DECL(VPOB9, VPO, AA20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1065 SIG_EXPR_DECL(VPOB9, VPOOFF1, AA20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1066 SIG_EXPR_DECL(VPOB9, VPOOFF2, AA20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1067 SIG_EXPR_LIST_DECL(VPOB9, SIG_EXPR_PTR(VPOB9, VPO),
1068 SIG_EXPR_PTR(VPOB9, VPOOFF1), SIG_EXPR_PTR(VPOB9, VPOOFF2));
1069 SS_PIN_DECL(AA20, GPIOS7, VPOB9);
1070
1071 /* RGMII1/RMII1 */
1072
1073 #define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0)
1074 #define RMII2_DESC SIG_DESC_BIT(HW_STRAP1, 7, 0)
1075
1076 #define B5 152
1077 SIG_EXPR_LIST_DECL_SINGLE(GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0));
1078 SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLKO, RMII1, RMII1_DESC,
1079 SIG_DESC_SET(SCU48, 29));
1080 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCK, RGMII1);
1081 MS_PIN_DECL_(B5, SIG_EXPR_LIST_PTR(GPIOT0), SIG_EXPR_LIST_PTR(RMII1RCLKO),
1082 SIG_EXPR_LIST_PTR(RGMII1TXCK));
1083
1084 #define E9 153
1085 SIG_EXPR_LIST_DECL_SINGLE(GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1));
1086 SIG_EXPR_LIST_DECL_SINGLE(RMII1TXEN, RMII1, RMII1_DESC);
1087 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCTL, RGMII1);
1088 MS_PIN_DECL_(E9, SIG_EXPR_LIST_PTR(GPIOT1), SIG_EXPR_LIST_PTR(RMII1TXEN),
1089 SIG_EXPR_LIST_PTR(RGMII1TXCTL));
1090
1091 #define F9 154
1092 SIG_EXPR_LIST_DECL_SINGLE(GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2));
1093 SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD0, RMII1, RMII1_DESC);
1094 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD0, RGMII1);
1095 MS_PIN_DECL_(F9, SIG_EXPR_LIST_PTR(GPIOT2), SIG_EXPR_LIST_PTR(RMII1TXD0),
1096 SIG_EXPR_LIST_PTR(RGMII1TXD0));
1097
1098 #define A5 155
1099 SIG_EXPR_LIST_DECL_SINGLE(GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3));
1100 SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD1, RMII1, RMII1_DESC);
1101 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD1, RGMII1);
1102 MS_PIN_DECL_(A5, SIG_EXPR_LIST_PTR(GPIOT3), SIG_EXPR_LIST_PTR(RMII1TXD1),
1103 SIG_EXPR_LIST_PTR(RGMII1TXD1));
1104
1105 #define E7 156
1106 SIG_EXPR_LIST_DECL_SINGLE(GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4));
1107 SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH0, RMII1, RMII1_DESC);
1108 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD2, RGMII1);
1109 MS_PIN_DECL_(E7, SIG_EXPR_LIST_PTR(GPIOT4), SIG_EXPR_LIST_PTR(RMII1DASH0),
1110 SIG_EXPR_LIST_PTR(RGMII1TXD2));
1111
1112 #define D7 157
1113 SIG_EXPR_LIST_DECL_SINGLE(GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5));
1114 SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH1, RMII1, RMII1_DESC);
1115 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD3, RGMII1);
1116 MS_PIN_DECL_(D7, SIG_EXPR_LIST_PTR(GPIOT5), SIG_EXPR_LIST_PTR(RMII1DASH1),
1117 SIG_EXPR_LIST_PTR(RGMII1TXD3));
1118
1119 #define B2 158
1120 SIG_EXPR_LIST_DECL_SINGLE(GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6));
1121 SIG_EXPR_LIST_DECL_SINGLE(RMII2RCLKO, RMII2, RMII2_DESC,
1122 SIG_DESC_SET(SCU48, 30));
1123 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCK, RGMII2);
1124 MS_PIN_DECL_(B2, SIG_EXPR_LIST_PTR(GPIOT6), SIG_EXPR_LIST_PTR(RMII2RCLKO),
1125 SIG_EXPR_LIST_PTR(RGMII2TXCK));
1126
1127 #define B1 159
1128 SIG_EXPR_LIST_DECL_SINGLE(GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7));
1129 SIG_EXPR_LIST_DECL_SINGLE(RMII2TXEN, RMII2, RMII2_DESC);
1130 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCTL, RGMII2);
1131 MS_PIN_DECL_(B1, SIG_EXPR_LIST_PTR(GPIOT7), SIG_EXPR_LIST_PTR(RMII2TXEN),
1132 SIG_EXPR_LIST_PTR(RGMII2TXCTL));
1133
1134 #define A2 160
1135 SIG_EXPR_LIST_DECL_SINGLE(GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8));
1136 SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD0, RMII2, RMII2_DESC);
1137 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD0, RGMII2);
1138 MS_PIN_DECL_(A2, SIG_EXPR_LIST_PTR(GPIOU0), SIG_EXPR_LIST_PTR(RMII2TXD0),
1139 SIG_EXPR_LIST_PTR(RGMII2TXD0));
1140
1141 #define B3 161
1142 SIG_EXPR_LIST_DECL_SINGLE(GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9));
1143 SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD1, RMII2, RMII2_DESC);
1144 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD1, RGMII2);
1145 MS_PIN_DECL_(B3, SIG_EXPR_LIST_PTR(GPIOU1), SIG_EXPR_LIST_PTR(RMII2TXD1),
1146 SIG_EXPR_LIST_PTR(RGMII2TXD1));
1147
1148 #define D5 162
1149 SIG_EXPR_LIST_DECL_SINGLE(GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10));
1150 SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH0, RMII2, RMII2_DESC);
1151 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD2, RGMII2);
1152 MS_PIN_DECL_(D5, SIG_EXPR_LIST_PTR(GPIOU2), SIG_EXPR_LIST_PTR(RMII2DASH0),
1153 SIG_EXPR_LIST_PTR(RGMII2TXD2));
1154
1155 #define D4 163
1156 SIG_EXPR_LIST_DECL_SINGLE(GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11));
1157 SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH1, RMII2, RMII2_DESC);
1158 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD3, RGMII2);
1159 MS_PIN_DECL_(D4, SIG_EXPR_LIST_PTR(GPIOU3), SIG_EXPR_LIST_PTR(RMII2DASH1),
1160 SIG_EXPR_LIST_PTR(RGMII2TXD3));
1161
1162 #define B4 164
1163 SIG_EXPR_LIST_DECL_SINGLE(GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12));
1164 SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLKI, RMII1, RMII1_DESC);
1165 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCK, RGMII1);
1166 MS_PIN_DECL_(B4, SIG_EXPR_LIST_PTR(GPIOU4), SIG_EXPR_LIST_PTR(RMII1RCLKI),
1167 SIG_EXPR_LIST_PTR(RGMII1RXCK));
1168
1169 #define A4 165
1170 SIG_EXPR_LIST_DECL_SINGLE(GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13));
1171 SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH2, RMII1, RMII1_DESC);
1172 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCTL, RGMII1);
1173 MS_PIN_DECL_(A4, SIG_EXPR_LIST_PTR(GPIOU5), SIG_EXPR_LIST_PTR(RMII1DASH2),
1174 SIG_EXPR_LIST_PTR(RGMII1RXCTL));
1175
1176 #define A3 166
1177 SIG_EXPR_LIST_DECL_SINGLE(GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14));
1178 SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD0, RMII1, RMII1_DESC);
1179 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD0, RGMII1);
1180 MS_PIN_DECL_(A3, SIG_EXPR_LIST_PTR(GPIOU6), SIG_EXPR_LIST_PTR(RMII1RXD0),
1181 SIG_EXPR_LIST_PTR(RGMII1RXD0));
1182
1183 #define D6 167
1184 SIG_EXPR_LIST_DECL_SINGLE(GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15));
1185 SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD1, RMII1, RMII1_DESC);
1186 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD1, RGMII1);
1187 MS_PIN_DECL_(D6, SIG_EXPR_LIST_PTR(GPIOU7), SIG_EXPR_LIST_PTR(RMII1RXD1),
1188 SIG_EXPR_LIST_PTR(RGMII1RXD1));
1189
1190 #define C5 168
1191 SIG_EXPR_LIST_DECL_SINGLE(GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16));
1192 SIG_EXPR_LIST_DECL_SINGLE(RMII1CRSDV, RMII1, RMII1_DESC);
1193 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD2, RGMII1);
1194 MS_PIN_DECL_(C5, SIG_EXPR_LIST_PTR(GPIOV0), SIG_EXPR_LIST_PTR(RMII1CRSDV),
1195 SIG_EXPR_LIST_PTR(RGMII1RXD2));
1196
1197 #define C4 169
1198 SIG_EXPR_LIST_DECL_SINGLE(GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17));
1199 SIG_EXPR_LIST_DECL_SINGLE(RMII1RXER, RMII1, RMII1_DESC);
1200 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD3, RGMII1);
1201 MS_PIN_DECL_(C4, SIG_EXPR_LIST_PTR(GPIOV1), SIG_EXPR_LIST_PTR(RMII1RXER),
1202 SIG_EXPR_LIST_PTR(RGMII1RXD3));
1203
1204 FUNC_GROUP_DECL(RGMII1, B4, A4, A3, D6, C5, C4, B5, E9, F9, A5, E7, D7);
1205 FUNC_GROUP_DECL(RMII1, B4, A3, D6, C5, C4, B5, E9, F9, A5);
1206
1207 #define C2 170
1208 SIG_EXPR_LIST_DECL_SINGLE(GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18));
1209 SIG_EXPR_LIST_DECL_SINGLE(RMII2RCLKI, RMII2, RMII2_DESC);
1210 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCK, RGMII2);
1211 MS_PIN_DECL_(C2, SIG_EXPR_LIST_PTR(GPIOV2), SIG_EXPR_LIST_PTR(RMII2RCLKI),
1212 SIG_EXPR_LIST_PTR(RGMII2RXCK));
1213
1214 #define C1 171
1215 SIG_EXPR_LIST_DECL_SINGLE(GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19));
1216 SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH2, RMII2, RMII2_DESC);
1217 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCTL, RGMII2);
1218 MS_PIN_DECL_(C1, SIG_EXPR_LIST_PTR(GPIOV3), SIG_EXPR_LIST_PTR(RMII2DASH2),
1219 SIG_EXPR_LIST_PTR(RGMII2RXCTL));
1220
1221 #define C3 172
1222 SIG_EXPR_LIST_DECL_SINGLE(GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20));
1223 SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD0, RMII2, RMII2_DESC);
1224 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD0, RGMII2);
1225 MS_PIN_DECL_(C3, SIG_EXPR_LIST_PTR(GPIOV4), SIG_EXPR_LIST_PTR(RMII2RXD0),
1226 SIG_EXPR_LIST_PTR(RGMII2RXD0));
1227
1228 #define D1 173
1229 SIG_EXPR_LIST_DECL_SINGLE(GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21));
1230 SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD1, RMII2, RMII2_DESC);
1231 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD1, RGMII2);
1232 MS_PIN_DECL_(D1, SIG_EXPR_LIST_PTR(GPIOV5), SIG_EXPR_LIST_PTR(RMII2RXD1),
1233 SIG_EXPR_LIST_PTR(RGMII2RXD1));
1234
1235 #define D2 174
1236 SIG_EXPR_LIST_DECL_SINGLE(GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22));
1237 SIG_EXPR_LIST_DECL_SINGLE(RMII2CRSDV, RMII2, RMII2_DESC);
1238 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD2, RGMII2);
1239 MS_PIN_DECL_(D2, SIG_EXPR_LIST_PTR(GPIOV6), SIG_EXPR_LIST_PTR(RMII2CRSDV),
1240 SIG_EXPR_LIST_PTR(RGMII2RXD2));
1241
1242 #define E6 175
1243 SIG_EXPR_LIST_DECL_SINGLE(GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23));
1244 SIG_EXPR_LIST_DECL_SINGLE(RMII2RXER, RMII2, RMII2_DESC);
1245 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD3, RGMII2);
1246 MS_PIN_DECL_(E6, SIG_EXPR_LIST_PTR(GPIOV7), SIG_EXPR_LIST_PTR(RMII2RXER),
1247 SIG_EXPR_LIST_PTR(RGMII2RXD3));
1248
1249 FUNC_GROUP_DECL(RGMII2, B2, B1, A2, B3, D5, D4, C2, C1, C3, D1, D2, E6);
1250 FUNC_GROUP_DECL(RMII2, B2, B1, A2, B3, C2, C3, D1, D2, E6);
1251
1252 #define F4 176
1253 SIG_EXPR_LIST_DECL_SINGLE(GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24));
1254 SIG_EXPR_LIST_DECL_SINGLE(ADC0, ADC0);
1255 MS_PIN_DECL_(F4, SIG_EXPR_LIST_PTR(GPIOW0), SIG_EXPR_LIST_PTR(ADC0));
1256 FUNC_GROUP_DECL(ADC0, F4);
1257
1258 #define F5 177
1259 SIG_EXPR_LIST_DECL_SINGLE(GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25));
1260 SIG_EXPR_LIST_DECL_SINGLE(ADC1, ADC1);
1261 MS_PIN_DECL_(F5, SIG_EXPR_LIST_PTR(GPIOW1), SIG_EXPR_LIST_PTR(ADC1));
1262 FUNC_GROUP_DECL(ADC1, F5);
1263
1264 #define E2 178
1265 SIG_EXPR_LIST_DECL_SINGLE(GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26));
1266 SIG_EXPR_LIST_DECL_SINGLE(ADC2, ADC2);
1267 MS_PIN_DECL_(E2, SIG_EXPR_LIST_PTR(GPIOW2), SIG_EXPR_LIST_PTR(ADC2));
1268 FUNC_GROUP_DECL(ADC2, E2);
1269
1270 #define E1 179
1271 SIG_EXPR_LIST_DECL_SINGLE(GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27));
1272 SIG_EXPR_LIST_DECL_SINGLE(ADC3, ADC3);
1273 MS_PIN_DECL_(E1, SIG_EXPR_LIST_PTR(GPIOW3), SIG_EXPR_LIST_PTR(ADC3));
1274 FUNC_GROUP_DECL(ADC3, E1);
1275
1276 #define F3 180
1277 SIG_EXPR_LIST_DECL_SINGLE(GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28));
1278 SIG_EXPR_LIST_DECL_SINGLE(ADC4, ADC4);
1279 MS_PIN_DECL_(F3, SIG_EXPR_LIST_PTR(GPIOW4), SIG_EXPR_LIST_PTR(ADC4));
1280 FUNC_GROUP_DECL(ADC4, F3);
1281
1282 #define E3 181
1283 SIG_EXPR_LIST_DECL_SINGLE(GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29));
1284 SIG_EXPR_LIST_DECL_SINGLE(ADC5, ADC5);
1285 MS_PIN_DECL_(E3, SIG_EXPR_LIST_PTR(GPIOW5), SIG_EXPR_LIST_PTR(ADC5));
1286 FUNC_GROUP_DECL(ADC5, E3);
1287
1288 #define G5 182
1289 SIG_EXPR_LIST_DECL_SINGLE(GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30));
1290 SIG_EXPR_LIST_DECL_SINGLE(ADC6, ADC6);
1291 MS_PIN_DECL_(G5, SIG_EXPR_LIST_PTR(GPIOW6), SIG_EXPR_LIST_PTR(ADC6));
1292 FUNC_GROUP_DECL(ADC6, G5);
1293
1294 #define G4 183
1295 SIG_EXPR_LIST_DECL_SINGLE(GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31));
1296 SIG_EXPR_LIST_DECL_SINGLE(ADC7, ADC7);
1297 MS_PIN_DECL_(G4, SIG_EXPR_LIST_PTR(GPIOW7), SIG_EXPR_LIST_PTR(ADC7));
1298 FUNC_GROUP_DECL(ADC7, G4);
1299
1300 #define F2 184
1301 SIG_EXPR_LIST_DECL_SINGLE(GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0));
1302 SIG_EXPR_LIST_DECL_SINGLE(ADC8, ADC8);
1303 MS_PIN_DECL_(F2, SIG_EXPR_LIST_PTR(GPIOX0), SIG_EXPR_LIST_PTR(ADC8));
1304 FUNC_GROUP_DECL(ADC8, F2);
1305
1306 #define G3 185
1307 SIG_EXPR_LIST_DECL_SINGLE(GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1));
1308 SIG_EXPR_LIST_DECL_SINGLE(ADC9, ADC9);
1309 MS_PIN_DECL_(G3, SIG_EXPR_LIST_PTR(GPIOX1), SIG_EXPR_LIST_PTR(ADC9));
1310 FUNC_GROUP_DECL(ADC9, G3);
1311
1312 #define G2 186
1313 SIG_EXPR_LIST_DECL_SINGLE(GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2));
1314 SIG_EXPR_LIST_DECL_SINGLE(ADC10, ADC10);
1315 MS_PIN_DECL_(G2, SIG_EXPR_LIST_PTR(GPIOX2), SIG_EXPR_LIST_PTR(ADC10));
1316 FUNC_GROUP_DECL(ADC10, G2);
1317
1318 #define F1 187
1319 SIG_EXPR_LIST_DECL_SINGLE(GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3));
1320 SIG_EXPR_LIST_DECL_SINGLE(ADC11, ADC11);
1321 MS_PIN_DECL_(F1, SIG_EXPR_LIST_PTR(GPIOX3), SIG_EXPR_LIST_PTR(ADC11));
1322 FUNC_GROUP_DECL(ADC11, F1);
1323
1324 #define H5 188
1325 SIG_EXPR_LIST_DECL_SINGLE(GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4));
1326 SIG_EXPR_LIST_DECL_SINGLE(ADC12, ADC12);
1327 MS_PIN_DECL_(H5, SIG_EXPR_LIST_PTR(GPIOX4), SIG_EXPR_LIST_PTR(ADC12));
1328 FUNC_GROUP_DECL(ADC12, H5);
1329
1330 #define G1 189
1331 SIG_EXPR_LIST_DECL_SINGLE(GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5));
1332 SIG_EXPR_LIST_DECL_SINGLE(ADC13, ADC13);
1333 MS_PIN_DECL_(G1, SIG_EXPR_LIST_PTR(GPIOX5), SIG_EXPR_LIST_PTR(ADC13));
1334 FUNC_GROUP_DECL(ADC13, G1);
1335
1336 #define H3 190
1337 SIG_EXPR_LIST_DECL_SINGLE(GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6));
1338 SIG_EXPR_LIST_DECL_SINGLE(ADC14, ADC14);
1339 MS_PIN_DECL_(H3, SIG_EXPR_LIST_PTR(GPIOX6), SIG_EXPR_LIST_PTR(ADC14));
1340 FUNC_GROUP_DECL(ADC14, H3);
1341
1342 #define H4 191
1343 SIG_EXPR_LIST_DECL_SINGLE(GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7));
1344 SIG_EXPR_LIST_DECL_SINGLE(ADC15, ADC15);
1345 MS_PIN_DECL_(H4, SIG_EXPR_LIST_PTR(GPIOX7), SIG_EXPR_LIST_PTR(ADC15));
1346 FUNC_GROUP_DECL(ADC15, H4);
1347
1348 #define ACPI_DESC SIG_DESC_SET(HW_STRAP1, 19)
1349
1350 #define R22 192
1351 SIG_EXPR_DECL(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8));
1352 SIG_EXPR_DECL(SIOS3, ACPI, ACPI_DESC);
1353 SIG_EXPR_LIST_DECL_DUAL(SIOS3, SIOS3, ACPI);
1354 SIG_EXPR_LIST_DECL_SINGLE(DASHR22, DASHR22, SIG_DESC_SET(SCU94, 10));
1355 MS_PIN_DECL(R22, GPIOY0, SIOS3, DASHR22);
1356 FUNC_GROUP_DECL(SIOS3, R22);
1357
1358 #define R21 193
1359 SIG_EXPR_DECL(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9));
1360 SIG_EXPR_DECL(SIOS5, ACPI, ACPI_DESC);
1361 SIG_EXPR_LIST_DECL_DUAL(SIOS5, SIOS5, ACPI);
1362 SIG_EXPR_LIST_DECL_SINGLE(DASHR21, DASHR21, SIG_DESC_SET(SCU94, 10));
1363 MS_PIN_DECL(R21, GPIOY1, SIOS5, DASHR21);
1364 FUNC_GROUP_DECL(SIOS5, R21);
1365
1366 #define P22 194
1367 SIG_EXPR_DECL(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10));
1368 SIG_EXPR_DECL(SIOPWREQ, ACPI, ACPI_DESC);
1369 SIG_EXPR_LIST_DECL_DUAL(SIOPWREQ, SIOPWREQ, ACPI);
1370 SIG_EXPR_LIST_DECL_SINGLE(DASHP22, DASHP22, SIG_DESC_SET(SCU94, 11));
1371 MS_PIN_DECL(P22, GPIOY2, SIOPWREQ, DASHP22);
1372 FUNC_GROUP_DECL(SIOPWREQ, P22);
1373
1374 #define P21 195
1375 SIG_EXPR_DECL(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11));
1376 SIG_EXPR_DECL(SIOONCTRL, ACPI, ACPI_DESC);
1377 SIG_EXPR_LIST_DECL_DUAL(SIOONCTRL, SIOONCTRL, ACPI);
1378 SIG_EXPR_LIST_DECL_SINGLE(DASHP21, DASHP21, SIG_DESC_SET(SCU94, 11));
1379 MS_PIN_DECL(P21, GPIOY3, SIOONCTRL, DASHP21);
1380 FUNC_GROUP_DECL(SIOONCTRL, P21);
1381
1382 #define M18 196
1383 SSSF_PIN_DECL(M18, GPIOY4, SCL1, SIG_DESC_SET(SCUA4, 12));
1384
1385 #define M19 197
1386 SSSF_PIN_DECL(M19, GPIOY5, SDA1, SIG_DESC_SET(SCUA4, 13));
1387
1388 #define M20 198
1389 SSSF_PIN_DECL(M20, GPIOY6, SCL2, SIG_DESC_SET(SCUA4, 14));
1390
1391 #define P20 199
1392 SSSF_PIN_DECL(P20, GPIOY7, SDA2, SIG_DESC_SET(SCUA4, 15));
1393
1394 #define PNOR_DESC SIG_DESC_SET(SCU90, 31)
1395
1396 #define Y20 200
1397 #define Y20_DESC SIG_DESC_SET(SCUA4, 16)
1398 SIG_EXPR_DECL(VPOG2, VPO, Y20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1399 SIG_EXPR_DECL(VPOG2, VPOOFF1, Y20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1400 SIG_EXPR_DECL(VPOG2, VPOOFF2, Y20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1401 SIG_EXPR_LIST_DECL(VPOG2, SIG_EXPR_PTR(VPOG2, VPO),
1402 SIG_EXPR_PTR(VPOG2, VPOOFF1), SIG_EXPR_PTR(VPOG2, VPOOFF2));
1403 SIG_EXPR_DECL(SIOPBI, SIOPBI, Y20_DESC);
1404 SIG_EXPR_DECL(SIOPBI, ACPI, Y20_DESC);
1405 SIG_EXPR_LIST_DECL_DUAL(SIOPBI, SIOPBI, ACPI);
1406 SIG_EXPR_LIST_DECL_SINGLE(NORA0, PNOR, PNOR_DESC);
1407 SIG_EXPR_LIST_DECL_SINGLE(GPIOZ0, GPIOZ0);
1408 MS_PIN_DECL_(Y20, SIG_EXPR_LIST_PTR(VPOG2), SIG_EXPR_LIST_PTR(SIOPBI),
1409 SIG_EXPR_LIST_PTR(NORA0), SIG_EXPR_LIST_PTR(GPIOZ0));
1410 FUNC_GROUP_DECL(SIOPBI, Y20);
1411
1412 #define AB20 201
1413 #define AB20_DESC SIG_DESC_SET(SCUA4, 17)
1414 SIG_EXPR_DECL(VPOG3, VPO, AB20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1415 SIG_EXPR_DECL(VPOG3, VPOOFF1, AB20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1416 SIG_EXPR_DECL(VPOG3, VPOOFF2, AB20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1417 SIG_EXPR_LIST_DECL(VPOG3, SIG_EXPR_PTR(VPOG3, VPO),
1418 SIG_EXPR_PTR(VPOG3, VPOOFF1), SIG_EXPR_PTR(VPOG3, VPOOFF2));
1419 SIG_EXPR_DECL(SIOPWRGD, SIOPWRGD, AB20_DESC);
1420 SIG_EXPR_DECL(SIOPWRGD, ACPI, AB20_DESC);
1421 SIG_EXPR_LIST_DECL_DUAL(SIOPWRGD, SIOPWRGD, ACPI);
1422 SIG_EXPR_LIST_DECL_SINGLE(NORA1, PNOR, PNOR_DESC);
1423 SIG_EXPR_LIST_DECL_SINGLE(GPIOZ1, GPIOZ1);
1424 MS_PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(VPOG3), SIG_EXPR_LIST_PTR(SIOPWRGD),
1425 SIG_EXPR_LIST_PTR(NORA1), SIG_EXPR_LIST_PTR(GPIOZ1));
1426 FUNC_GROUP_DECL(SIOPWRGD, AB20);
1427
1428 #define AB21 202
1429 #define AB21_DESC SIG_DESC_SET(SCUA4, 18)
1430 SIG_EXPR_DECL(VPOG4, VPO, AB21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1431 SIG_EXPR_DECL(VPOG4, VPOOFF1, AB21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1432 SIG_EXPR_DECL(VPOG4, VPOOFF2, AB21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1433 SIG_EXPR_LIST_DECL(VPOG4, SIG_EXPR_PTR(VPOG4, VPO),
1434 SIG_EXPR_PTR(VPOG4, VPOOFF1), SIG_EXPR_PTR(VPOG4, VPOOFF2));
1435 SIG_EXPR_DECL(SIOPBO, SIOPBO, AB21_DESC);
1436 SIG_EXPR_DECL(SIOPBO, ACPI, AB21_DESC);
1437 SIG_EXPR_LIST_DECL_DUAL(SIOPBO, SIOPBO, ACPI);
1438 SIG_EXPR_LIST_DECL_SINGLE(NORA2, PNOR, PNOR_DESC);
1439 SIG_EXPR_LIST_DECL_SINGLE(GPIOZ2, GPIOZ2);
1440 MS_PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(VPOG4), SIG_EXPR_LIST_PTR(SIOPBO),
1441 SIG_EXPR_LIST_PTR(NORA2), SIG_EXPR_LIST_PTR(GPIOZ2));
1442 FUNC_GROUP_DECL(SIOPBO, AB21);
1443
1444 #define AA21 203
1445 #define AA21_DESC SIG_DESC_SET(SCUA4, 19)
1446 SIG_EXPR_DECL(VPOG5, VPO, AA21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1447 SIG_EXPR_DECL(VPOG5, VPOOFF1, AA21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1448 SIG_EXPR_DECL(VPOG5, VPOOFF2, AA21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1449 SIG_EXPR_LIST_DECL(VPOG5, SIG_EXPR_PTR(VPOG5, VPO),
1450 SIG_EXPR_PTR(VPOG5, VPOOFF1), SIG_EXPR_PTR(VPOG5, VPOOFF2));
1451 SIG_EXPR_DECL(SIOSCI, SIOSCI, AA21_DESC);
1452 SIG_EXPR_DECL(SIOSCI, ACPI, AA21_DESC);
1453 SIG_EXPR_LIST_DECL_DUAL(SIOSCI, SIOSCI, ACPI);
1454 SIG_EXPR_LIST_DECL_SINGLE(NORA3, PNOR, PNOR_DESC);
1455 SIG_EXPR_LIST_DECL_SINGLE(GPIOZ3, GPIOZ3);
1456 MS_PIN_DECL_(AA21, SIG_EXPR_LIST_PTR(VPOG5), SIG_EXPR_LIST_PTR(SIOSCI),
1457 SIG_EXPR_LIST_PTR(NORA3), SIG_EXPR_LIST_PTR(GPIOZ3));
1458 FUNC_GROUP_DECL(SIOSCI, AA21);
1459
1460 FUNC_GROUP_DECL(ACPI, R22, R21, P22, P21, Y20, AB20, AB21, AA21);
1461
1462 /* CRT DVO disabled, configured for single-edge mode */
1463 #define CRT_DVO_DS_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 0, 0 }
1464
1465 /* CRT DVO disabled, configured for dual-edge mode */
1466 #define CRT_DVO_DD_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 1, 1 }
1467
1468 /* CRT DVO enabled, configured for single-edge mode */
1469 #define CRT_DVO_ES_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 2, 2 }
1470
1471 /* CRT DVO enabled, configured for dual-edge mode */
1472 #define CRT_DVO_ED_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 3, 3 }
1473
1474 #define U21 204
1475 #define U21_DESC SIG_DESC_SET(SCUA4, 20)
1476 SIG_EXPR_DECL(VPOG6, VPO, U21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1477 SIG_EXPR_DECL(VPOG6, VPOOFF1, U21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1478 SIG_EXPR_DECL(VPOG6, VPOOFF2, U21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1479 SIG_EXPR_LIST_DECL(VPOG6, SIG_EXPR_PTR(VPOG6, VPO),
1480 SIG_EXPR_PTR(VPOG6, VPOOFF1), SIG_EXPR_PTR(VPOG6, VPOOFF2));
1481 SIG_EXPR_LIST_DECL_SINGLE(NORA4, PNOR, PNOR_DESC);
1482 MS_PIN_DECL(U21, GPIOZ4, VPOG6, NORA4);
1483
1484 #define W22 205
1485 #define W22_DESC SIG_DESC_SET(SCUA4, 21)
1486 SIG_EXPR_DECL(VPOG7, VPO, W22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1487 SIG_EXPR_DECL(VPOG7, VPOOFF1, W22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1488 SIG_EXPR_DECL(VPOG7, VPOOFF2, W22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1489 SIG_EXPR_LIST_DECL(VPOG7, SIG_EXPR_PTR(VPOG7, VPO),
1490 SIG_EXPR_PTR(VPOG7, VPOOFF1), SIG_EXPR_PTR(VPOG7, VPOOFF2));
1491 SIG_EXPR_LIST_DECL_SINGLE(NORA5, PNOR, PNOR_DESC);
1492 MS_PIN_DECL(W22, GPIOZ5, VPOG7, NORA5);
1493
1494 #define V22 206
1495 #define V22_DESC SIG_DESC_SET(SCUA4, 22)
1496 SIG_EXPR_DECL(VPOG8, VPO, V22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1497 SIG_EXPR_DECL(VPOG8, VPOOFF1, V22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1498 SIG_EXPR_DECL(VPOG8, VPOOFF2, V22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1499 SIG_EXPR_LIST_DECL(VPOG8, SIG_EXPR_PTR(VPOG8, VPO),
1500 SIG_EXPR_PTR(VPOG8, VPOOFF1), SIG_EXPR_PTR(VPOG8, VPOOFF2));
1501 SIG_EXPR_LIST_DECL_SINGLE(NORA6, PNOR, PNOR_DESC);
1502 MS_PIN_DECL(V22, GPIOZ6, VPOG8, NORA6);
1503
1504 #define W21 207
1505 #define W21_DESC SIG_DESC_SET(SCUA4, 23)
1506 SIG_EXPR_DECL(VPOG9, VPO, W21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1507 SIG_EXPR_DECL(VPOG9, VPOOFF1, W21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1508 SIG_EXPR_DECL(VPOG9, VPOOFF2, W21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1509 SIG_EXPR_LIST_DECL(VPOG9, SIG_EXPR_PTR(VPOG9, VPO),
1510 SIG_EXPR_PTR(VPOG9, VPOOFF1), SIG_EXPR_PTR(VPOG9, VPOOFF2));
1511 SIG_EXPR_LIST_DECL_SINGLE(NORA7, PNOR, PNOR_DESC);
1512 MS_PIN_DECL(W21, GPIOZ7, VPOG9, NORA7);
1513
1514 #define Y21 208
1515 #define Y21_DESC SIG_DESC_SET(SCUA4, 24)
1516 SIG_EXPR_DECL(VPOR2, VPO, Y21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1517 SIG_EXPR_DECL(VPOR2, VPOOFF1, Y21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1518 SIG_EXPR_DECL(VPOR2, VPOOFF2, Y21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1519 SIG_EXPR_LIST_DECL(VPOR2, SIG_EXPR_PTR(VPOR2, VPO),
1520 SIG_EXPR_PTR(VPOR2, VPOOFF1), SIG_EXPR_PTR(VPOR2, VPOOFF2));
1521 SIG_EXPR_LIST_DECL_SINGLE(SALT7, SALT7, Y21_DESC);
1522 SIG_EXPR_LIST_DECL_SINGLE(NORD0, PNOR, PNOR_DESC);
1523 SIG_EXPR_LIST_DECL_SINGLE(GPIOAA0, GPIOAA0);
1524 MS_PIN_DECL_(Y21, SIG_EXPR_LIST_PTR(VPOR2), SIG_EXPR_LIST_PTR(SALT7),
1525 SIG_EXPR_LIST_PTR(NORD0), SIG_EXPR_LIST_PTR(GPIOAA0));
1526 FUNC_GROUP_DECL(SALT7, Y21);
1527
1528 #define V21 209
1529 #define V21_DESC SIG_DESC_SET(SCUA4, 25)
1530 SIG_EXPR_DECL(VPOR3, VPO, V21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1531 SIG_EXPR_DECL(VPOR3, VPOOFF1, V21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1532 SIG_EXPR_DECL(VPOR3, VPOOFF2, V21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1533 SIG_EXPR_LIST_DECL(VPOR3, SIG_EXPR_PTR(VPOR3, VPO),
1534 SIG_EXPR_PTR(VPOR3, VPOOFF1), SIG_EXPR_PTR(VPOR3, VPOOFF2));
1535 SIG_EXPR_LIST_DECL_SINGLE(SALT8, SALT8, V21_DESC);
1536 SIG_EXPR_LIST_DECL_SINGLE(NORD1, PNOR, PNOR_DESC);
1537 SIG_EXPR_LIST_DECL_SINGLE(GPIOAA1, GPIOAA1);
1538 MS_PIN_DECL_(V21, SIG_EXPR_LIST_PTR(VPOR3), SIG_EXPR_LIST_PTR(SALT8),
1539 SIG_EXPR_LIST_PTR(NORD1), SIG_EXPR_LIST_PTR(GPIOAA1));
1540 FUNC_GROUP_DECL(SALT8, V21);
1541
1542 #define Y22 210
1543 #define Y22_DESC SIG_DESC_SET(SCUA4, 26)
1544 SIG_EXPR_DECL(VPOR4, VPO, Y22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1545 SIG_EXPR_DECL(VPOR4, VPOOFF1, Y22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1546 SIG_EXPR_DECL(VPOR4, VPOOFF2, Y22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1547 SIG_EXPR_LIST_DECL(VPOR4, SIG_EXPR_PTR(VPOR4, VPO),
1548 SIG_EXPR_PTR(VPOR4, VPOOFF1), SIG_EXPR_PTR(VPOR4, VPOOFF2));
1549 SIG_EXPR_LIST_DECL_SINGLE(SALT9, SALT9, Y22_DESC);
1550 SIG_EXPR_LIST_DECL_SINGLE(NORD2, PNOR, PNOR_DESC);
1551 SIG_EXPR_LIST_DECL_SINGLE(GPIOAA2, GPIOAA2);
1552 MS_PIN_DECL_(Y22, SIG_EXPR_LIST_PTR(VPOR4), SIG_EXPR_LIST_PTR(SALT9),
1553 SIG_EXPR_LIST_PTR(NORD2), SIG_EXPR_LIST_PTR(GPIOAA2));
1554 FUNC_GROUP_DECL(SALT9, Y22);
1555
1556 #define AA22 211
1557 #define AA22_DESC SIG_DESC_SET(SCUA4, 27)
1558 SIG_EXPR_DECL(VPOR5, VPO, AA22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1559 SIG_EXPR_DECL(VPOR5, VPOOFF1, AA22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1560 SIG_EXPR_DECL(VPOR5, VPOOFF2, AA22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1561 SIG_EXPR_LIST_DECL(VPOR5, SIG_EXPR_PTR(VPOR5, VPO),
1562 SIG_EXPR_PTR(VPOR5, VPOOFF1), SIG_EXPR_PTR(VPOR5, VPOOFF2));
1563 SIG_EXPR_LIST_DECL_SINGLE(SALT10, SALT10, AA22_DESC);
1564 SIG_EXPR_LIST_DECL_SINGLE(NORD3, PNOR, PNOR_DESC);
1565 SIG_EXPR_LIST_DECL_SINGLE(GPIOAA3, GPIOAA3);
1566 MS_PIN_DECL_(AA22, SIG_EXPR_LIST_PTR(VPOR5), SIG_EXPR_LIST_PTR(SALT10),
1567 SIG_EXPR_LIST_PTR(NORD3), SIG_EXPR_LIST_PTR(GPIOAA3));
1568 FUNC_GROUP_DECL(SALT10, AA22);
1569
1570 #define U22 212
1571 #define U22_DESC SIG_DESC_SET(SCUA4, 28)
1572 SIG_EXPR_DECL(VPOR6, VPO, U22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1573 SIG_EXPR_DECL(VPOR6, VPOOFF1, U22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1574 SIG_EXPR_DECL(VPOR6, VPOOFF2, U22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1575 SIG_EXPR_LIST_DECL(VPOR6, SIG_EXPR_PTR(VPOR6, VPO),
1576 SIG_EXPR_PTR(VPOR6, VPOOFF1), SIG_EXPR_PTR(VPOR6, VPOOFF2));
1577 SIG_EXPR_LIST_DECL_SINGLE(SALT11, SALT11, U22_DESC);
1578 SIG_EXPR_LIST_DECL_SINGLE(NORD4, PNOR, PNOR_DESC);
1579 SIG_EXPR_LIST_DECL_SINGLE(GPIOAA4, GPIOAA4);
1580 MS_PIN_DECL_(U22, SIG_EXPR_LIST_PTR(VPOR6), SIG_EXPR_LIST_PTR(SALT11),
1581 SIG_EXPR_LIST_PTR(NORD4), SIG_EXPR_LIST_PTR(GPIOAA4));
1582 FUNC_GROUP_DECL(SALT11, U22);
1583
1584 #define T20 213
1585 #define T20_DESC SIG_DESC_SET(SCUA4, 29)
1586 SIG_EXPR_DECL(VPOR7, VPO, T20_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1587 SIG_EXPR_DECL(VPOR7, VPOOFF1, T20_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1588 SIG_EXPR_DECL(VPOR7, VPOOFF2, T20_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1589 SIG_EXPR_LIST_DECL(VPOR7, SIG_EXPR_PTR(VPOR7, VPO),
1590 SIG_EXPR_PTR(VPOR7, VPOOFF1), SIG_EXPR_PTR(VPOR7, VPOOFF2));
1591 SIG_EXPR_LIST_DECL_SINGLE(SALT12, SALT12, T20_DESC);
1592 SIG_EXPR_LIST_DECL_SINGLE(NORD5, PNOR, PNOR_DESC);
1593 SIG_EXPR_LIST_DECL_SINGLE(GPIOAA5, GPIOAA5);
1594 MS_PIN_DECL_(T20, SIG_EXPR_LIST_PTR(VPOR7), SIG_EXPR_LIST_PTR(SALT12),
1595 SIG_EXPR_LIST_PTR(NORD5), SIG_EXPR_LIST_PTR(GPIOAA5));
1596 FUNC_GROUP_DECL(SALT12, T20);
1597
1598 #define N18 214
1599 #define N18_DESC SIG_DESC_SET(SCUA4, 30)
1600 SIG_EXPR_DECL(VPOR8, VPO, N18_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1601 SIG_EXPR_DECL(VPOR8, VPOOFF1, N18_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1602 SIG_EXPR_DECL(VPOR8, VPOOFF2, N18_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1603 SIG_EXPR_LIST_DECL(VPOR8, SIG_EXPR_PTR(VPOR8, VPO),
1604 SIG_EXPR_PTR(VPOR8, VPOOFF1), SIG_EXPR_PTR(VPOR8, VPOOFF2));
1605 SIG_EXPR_LIST_DECL_SINGLE(SALT13, SALT13, N18_DESC);
1606 SIG_EXPR_LIST_DECL_SINGLE(NORD6, PNOR, PNOR_DESC);
1607 SIG_EXPR_LIST_DECL_SINGLE(GPIOAA6, GPIOAA6);
1608 MS_PIN_DECL_(N18, SIG_EXPR_LIST_PTR(VPOR8), SIG_EXPR_LIST_PTR(SALT13),
1609 SIG_EXPR_LIST_PTR(NORD6), SIG_EXPR_LIST_PTR(GPIOAA6));
1610 FUNC_GROUP_DECL(SALT13, N18);
1611
1612 #define P19 215
1613 #define P19_DESC SIG_DESC_SET(SCUA4, 31)
1614 SIG_EXPR_DECL(VPOR9, VPO, P19_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1615 SIG_EXPR_DECL(VPOR9, VPOOFF1, P19_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1616 SIG_EXPR_DECL(VPOR9, VPOOFF2, P19_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1617 SIG_EXPR_LIST_DECL(VPOR9, SIG_EXPR_PTR(VPOR9, VPO),
1618 SIG_EXPR_PTR(VPOR9, VPOOFF1), SIG_EXPR_PTR(VPOR9, VPOOFF2));
1619 SIG_EXPR_LIST_DECL_SINGLE(SALT14, SALT14, P19_DESC);
1620 SIG_EXPR_LIST_DECL_SINGLE(NORD7, PNOR, PNOR_DESC);
1621 SIG_EXPR_LIST_DECL_SINGLE(GPIOAA7, GPIOAA7);
1622 MS_PIN_DECL_(P19, SIG_EXPR_LIST_PTR(VPOR9), SIG_EXPR_LIST_PTR(SALT14),
1623 SIG_EXPR_LIST_PTR(NORD7), SIG_EXPR_LIST_PTR(GPIOAA7));
1624 FUNC_GROUP_DECL(SALT14, P19);
1625
1626 #define N19 216
1627 #define N19_DESC SIG_DESC_SET(SCUA8, 0)
1628 SIG_EXPR_DECL(VPODE, VPO, N19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1629 SIG_EXPR_DECL(VPODE, VPOOFF1, N19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1630 SIG_EXPR_DECL(VPODE, VPOOFF2, N19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1631 SIG_EXPR_LIST_DECL(VPODE, SIG_EXPR_PTR(VPODE, VPO),
1632 SIG_EXPR_PTR(VPODE, VPOOFF1), SIG_EXPR_PTR(VPODE, VPOOFF2));
1633 SIG_EXPR_LIST_DECL_SINGLE(NOROE, PNOR, PNOR_DESC);
1634 MS_PIN_DECL(N19, GPIOAB0, VPODE, NOROE);
1635
1636 #define T21 217
1637 #define T21_DESC SIG_DESC_SET(SCUA8, 1)
1638 SIG_EXPR_DECL(VPOHS, VPO, T21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1639 SIG_EXPR_DECL(VPOHS, VPOOFF1, T21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1640 SIG_EXPR_DECL(VPOHS, VPOOFF2, T21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1641 SIG_EXPR_LIST_DECL(VPOHS, SIG_EXPR_PTR(VPOHS, VPO),
1642 SIG_EXPR_PTR(VPOHS, VPOOFF1), SIG_EXPR_PTR(VPOHS, VPOOFF2));
1643 SIG_EXPR_LIST_DECL_SINGLE(NORWE, PNOR, PNOR_DESC);
1644 MS_PIN_DECL(T21, GPIOAB1, VPOHS, NORWE);
1645
1646 FUNC_GROUP_DECL(PNOR, Y20, AB20, AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22,
1647 AA22, U22, T20, N18, P19, N19, T21);
1648
1649 #define T22 218
1650 #define T22_DESC SIG_DESC_SET(SCUA8, 2)
1651 SIG_EXPR_DECL(VPOVS, VPO, T22_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1652 SIG_EXPR_DECL(VPOVS, VPOOFF1, T22_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1653 SIG_EXPR_DECL(VPOVS, VPOOFF2, T22_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1654 SIG_EXPR_LIST_DECL(VPOVS, SIG_EXPR_PTR(VPOVS, VPO),
1655 SIG_EXPR_PTR(VPOVS, VPOOFF1), SIG_EXPR_PTR(VPOVS, VPOOFF2));
1656 SIG_EXPR_LIST_DECL_SINGLE(WDTRST1, WDTRST1, T22_DESC);
1657 MS_PIN_DECL(T22, GPIOAB2, VPOVS, WDTRST1);
1658 FUNC_GROUP_DECL(WDTRST1, T22);
1659
1660 #define R20 219
1661 #define R20_DESC SIG_DESC_SET(SCUA8, 3)
1662 SIG_EXPR_DECL(VPOCLK, VPO, R20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1663 SIG_EXPR_DECL(VPOCLK, VPOOFF1, R20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1664 SIG_EXPR_DECL(VPOCLK, VPOOFF2, R20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1665 SIG_EXPR_LIST_DECL(VPOCLK, SIG_EXPR_PTR(VPOCLK, VPO),
1666 SIG_EXPR_PTR(VPOCLK, VPOOFF1), SIG_EXPR_PTR(VPOCLK, VPOOFF2));
1667 SIG_EXPR_LIST_DECL_SINGLE(WDTRST2, WDTRST2, R20_DESC);
1668 MS_PIN_DECL(R20, GPIOAB3, VPOCLK, WDTRST2);
1669 FUNC_GROUP_DECL(WDTRST2, R20);
1670
1671 FUNC_GROUP_DECL(VPO, V20, U19, R18, P18, R19, W20, U20, AA20, Y20, AB20,
1672 AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22, AA22, U22, T20,
1673 N18, P19, N19, T21, T22, R20);
1674
1675 #define ESPI_DESC SIG_DESC_SET(HW_STRAP1, 25)
1676
1677 #define G21 224
1678 SIG_EXPR_LIST_DECL_SINGLE(ESPID0, ESPI, ESPI_DESC);
1679 SIG_EXPR_LIST_DECL_SINGLE(LAD0, LAD0, SIG_DESC_SET(SCUAC, 0));
1680 MS_PIN_DECL(G21, GPIOAC0, ESPID0, LAD0);
1681 FUNC_GROUP_DECL(LAD0, G21);
1682
1683 #define G20 225
1684 SIG_EXPR_LIST_DECL_SINGLE(ESPID1, ESPI, ESPI_DESC);
1685 SIG_EXPR_LIST_DECL_SINGLE(LAD1, LAD1, SIG_DESC_SET(SCUAC, 1));
1686 MS_PIN_DECL(G20, GPIOAC1, ESPID1, LAD1);
1687 FUNC_GROUP_DECL(LAD1, G20);
1688
1689 #define D22 226
1690 SIG_EXPR_LIST_DECL_SINGLE(ESPID2, ESPI, ESPI_DESC);
1691 SIG_EXPR_LIST_DECL_SINGLE(LAD2, LAD2, SIG_DESC_SET(SCUAC, 2));
1692 MS_PIN_DECL(D22, GPIOAC2, ESPID2, LAD2);
1693 FUNC_GROUP_DECL(LAD2, D22);
1694
1695 #define E22 227
1696 SIG_EXPR_LIST_DECL_SINGLE(ESPID3, ESPI, ESPI_DESC);
1697 SIG_EXPR_LIST_DECL_SINGLE(LAD3, LAD3, SIG_DESC_SET(SCUAC, 3));
1698 MS_PIN_DECL(E22, GPIOAC3, ESPID3, LAD3);
1699 FUNC_GROUP_DECL(LAD3, E22);
1700
1701 #define C22 228
1702 SIG_EXPR_LIST_DECL_SINGLE(ESPICK, ESPI, ESPI_DESC);
1703 SIG_EXPR_LIST_DECL_SINGLE(LCLK, LCLK, SIG_DESC_SET(SCUAC, 4));
1704 MS_PIN_DECL(C22, GPIOAC4, ESPICK, LCLK);
1705 FUNC_GROUP_DECL(LCLK, C22);
1706
1707 #define F21 229
1708 SIG_EXPR_LIST_DECL_SINGLE(ESPICS, ESPI, ESPI_DESC);
1709 SIG_EXPR_LIST_DECL_SINGLE(LFRAME, LFRAME, SIG_DESC_SET(SCUAC, 5));
1710 MS_PIN_DECL(F21, GPIOAC5, ESPICS, LFRAME);
1711 FUNC_GROUP_DECL(LFRAME, F21);
1712
1713 #define F22 230
1714 SIG_EXPR_LIST_DECL_SINGLE(ESPIALT, ESPI, ESPI_DESC);
1715 SIG_EXPR_LIST_DECL_SINGLE(LSIRQ, LSIRQ, SIG_DESC_SET(SCUAC, 6));
1716 MS_PIN_DECL(F22, GPIOAC6, ESPIALT, LSIRQ);
1717 FUNC_GROUP_DECL(LSIRQ, F22);
1718
1719 #define G22 231
1720 SIG_EXPR_LIST_DECL_SINGLE(ESPIRST, ESPI, ESPI_DESC);
1721 SIG_EXPR_LIST_DECL_SINGLE(LPCRST, LPCRST, SIG_DESC_SET(SCUAC, 7));
1722 MS_PIN_DECL(G22, GPIOAC7, ESPIRST, LPCRST);
1723 FUNC_GROUP_DECL(LPCRST, G22);
1724
1725 FUNC_GROUP_DECL(ESPI, G21, G20, D22, E22, C22, F21, F22, G22);
1726
1727 #define A7 232
1728 SIG_EXPR_LIST_DECL_SINGLE(USB2AHDP, USB2AH, SIG_DESC_SET(SCU90, 29));
1729 SIG_EXPR_LIST_DECL_SINGLE(USB2ADDP, USB2AD, SIG_DESC_BIT(SCU90, 29, 0));
1730 MS_PIN_DECL_(A7, SIG_EXPR_LIST_PTR(USB2AHDP), SIG_EXPR_LIST_PTR(USB2ADDP));
1731
1732 #define A8 233
1733 SIG_EXPR_LIST_DECL_SINGLE(USB2AHDN, USB2AH, SIG_DESC_SET(SCU90, 29));
1734 SIG_EXPR_LIST_DECL_SINGLE(USB2ADDN, USB2AD, SIG_DESC_BIT(SCU90, 29, 0));
1735 MS_PIN_DECL_(A8, SIG_EXPR_LIST_PTR(USB2AHDN), SIG_EXPR_LIST_PTR(USB2ADDN));
1736
1737 FUNC_GROUP_DECL(USB2AH, A7, A8);
1738 FUNC_GROUP_DECL(USB2AD, A7, A8);
1739
1740 #define USB11BHID_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 0, 0 }
1741 #define USB2BD_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 1, 0 }
1742 #define USB2BH1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 2, 0 }
1743 #define USB2BH2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 3, 0 }
1744
1745 #define B6 234
1746 SIG_EXPR_LIST_DECL_SINGLE(USB11BDP, USB11BHID, USB11BHID_DESC);
1747 SIG_EXPR_LIST_DECL_SINGLE(USB2BDDP, USB2BD, USB2BD_DESC);
1748 SIG_EXPR_DECL(USB2BHDP1, USB2BH, USB2BH1_DESC);
1749 SIG_EXPR_DECL(USB2BHDP2, USB2BH, USB2BH2_DESC);
1750 SIG_EXPR_LIST_DECL(USB2BHDP, SIG_EXPR_PTR(USB2BHDP1, USB2BH),
1751 SIG_EXPR_PTR(USB2BHDP2, USB2BH));
1752 MS_PIN_DECL_(B6, SIG_EXPR_LIST_PTR(USB11BDP), SIG_EXPR_LIST_PTR(USB2BDDP),
1753 SIG_EXPR_LIST_PTR(USB2BHDP));
1754
1755 #define A6 235
1756 SIG_EXPR_LIST_DECL_SINGLE(USB11BDN, USB11BHID, USB11BHID_DESC);
1757 SIG_EXPR_LIST_DECL_SINGLE(USB2BDN, USB2BD, USB2BD_DESC);
1758 SIG_EXPR_DECL(USB2BHDN1, USB2BH, USB2BH1_DESC);
1759 SIG_EXPR_DECL(USB2BHDN2, USB2BH, USB2BH2_DESC);
1760 SIG_EXPR_LIST_DECL(USB2BHDN, SIG_EXPR_PTR(USB2BHDN1, USB2BH),
1761 SIG_EXPR_PTR(USB2BHDN2, USB2BH));
1762 MS_PIN_DECL_(A6, SIG_EXPR_LIST_PTR(USB11BDN), SIG_EXPR_LIST_PTR(USB2BDN),
1763 SIG_EXPR_LIST_PTR(USB2BHDN));
1764
1765 FUNC_GROUP_DECL(USB11BHID, B6, A6);
1766 FUNC_GROUP_DECL(USB2BD, B6, A6);
1767 FUNC_GROUP_DECL(USB2BH, B6, A6);
1768
1769 /* Pins, groups and functions are sort(1):ed alphabetically for sanity */
1770
1771 static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
1772 ASPEED_PINCTRL_PIN(A10),
1773 ASPEED_PINCTRL_PIN(A11),
1774 ASPEED_PINCTRL_PIN(A12),
1775 ASPEED_PINCTRL_PIN(A13),
1776 ASPEED_PINCTRL_PIN(A14),
1777 ASPEED_PINCTRL_PIN(A15),
1778 ASPEED_PINCTRL_PIN(A16),
1779 ASPEED_PINCTRL_PIN(A17),
1780 ASPEED_PINCTRL_PIN(A18),
1781 ASPEED_PINCTRL_PIN(A19),
1782 ASPEED_PINCTRL_PIN(A2),
1783 ASPEED_PINCTRL_PIN(A20),
1784 ASPEED_PINCTRL_PIN(A21),
1785 ASPEED_PINCTRL_PIN(A3),
1786 ASPEED_PINCTRL_PIN(A4),
1787 ASPEED_PINCTRL_PIN(A5),
1788 ASPEED_PINCTRL_PIN(A6),
1789 ASPEED_PINCTRL_PIN(A7),
1790 ASPEED_PINCTRL_PIN(A8),
1791 ASPEED_PINCTRL_PIN(A9),
1792 ASPEED_PINCTRL_PIN(AA1),
1793 ASPEED_PINCTRL_PIN(AA19),
1794 ASPEED_PINCTRL_PIN(AA2),
1795 ASPEED_PINCTRL_PIN(AA20),
1796 ASPEED_PINCTRL_PIN(AA21),
1797 ASPEED_PINCTRL_PIN(AA22),
1798 ASPEED_PINCTRL_PIN(AA3),
1799 ASPEED_PINCTRL_PIN(AA4),
1800 ASPEED_PINCTRL_PIN(AA5),
1801 ASPEED_PINCTRL_PIN(AB2),
1802 ASPEED_PINCTRL_PIN(AB20),
1803 ASPEED_PINCTRL_PIN(AB21),
1804 ASPEED_PINCTRL_PIN(AB3),
1805 ASPEED_PINCTRL_PIN(AB4),
1806 ASPEED_PINCTRL_PIN(AB5),
1807 ASPEED_PINCTRL_PIN(B1),
1808 ASPEED_PINCTRL_PIN(B10),
1809 ASPEED_PINCTRL_PIN(B11),
1810 ASPEED_PINCTRL_PIN(B12),
1811 ASPEED_PINCTRL_PIN(B13),
1812 ASPEED_PINCTRL_PIN(B14),
1813 ASPEED_PINCTRL_PIN(B15),
1814 ASPEED_PINCTRL_PIN(B16),
1815 ASPEED_PINCTRL_PIN(B17),
1816 ASPEED_PINCTRL_PIN(B18),
1817 ASPEED_PINCTRL_PIN(B19),
1818 ASPEED_PINCTRL_PIN(B2),
1819 ASPEED_PINCTRL_PIN(B20),
1820 ASPEED_PINCTRL_PIN(B21),
1821 ASPEED_PINCTRL_PIN(B22),
1822 ASPEED_PINCTRL_PIN(B3),
1823 ASPEED_PINCTRL_PIN(B4),
1824 ASPEED_PINCTRL_PIN(B5),
1825 ASPEED_PINCTRL_PIN(B6),
1826 ASPEED_PINCTRL_PIN(B9),
1827 ASPEED_PINCTRL_PIN(C1),
1828 ASPEED_PINCTRL_PIN(C11),
1829 ASPEED_PINCTRL_PIN(C12),
1830 ASPEED_PINCTRL_PIN(C13),
1831 ASPEED_PINCTRL_PIN(C14),
1832 ASPEED_PINCTRL_PIN(C15),
1833 ASPEED_PINCTRL_PIN(C16),
1834 ASPEED_PINCTRL_PIN(C17),
1835 ASPEED_PINCTRL_PIN(C18),
1836 ASPEED_PINCTRL_PIN(C19),
1837 ASPEED_PINCTRL_PIN(C2),
1838 ASPEED_PINCTRL_PIN(C20),
1839 ASPEED_PINCTRL_PIN(C21),
1840 ASPEED_PINCTRL_PIN(C22),
1841 ASPEED_PINCTRL_PIN(C3),
1842 ASPEED_PINCTRL_PIN(C4),
1843 ASPEED_PINCTRL_PIN(C5),
1844 ASPEED_PINCTRL_PIN(D1),
1845 ASPEED_PINCTRL_PIN(D10),
1846 ASPEED_PINCTRL_PIN(D13),
1847 ASPEED_PINCTRL_PIN(D14),
1848 ASPEED_PINCTRL_PIN(D15),
1849 ASPEED_PINCTRL_PIN(D16),
1850 ASPEED_PINCTRL_PIN(D17),
1851 ASPEED_PINCTRL_PIN(D18),
1852 ASPEED_PINCTRL_PIN(D19),
1853 ASPEED_PINCTRL_PIN(D2),
1854 ASPEED_PINCTRL_PIN(D20),
1855 ASPEED_PINCTRL_PIN(D21),
1856 ASPEED_PINCTRL_PIN(D22),
1857 ASPEED_PINCTRL_PIN(D4),
1858 ASPEED_PINCTRL_PIN(D5),
1859 ASPEED_PINCTRL_PIN(D6),
1860 ASPEED_PINCTRL_PIN(D7),
1861 ASPEED_PINCTRL_PIN(D8),
1862 ASPEED_PINCTRL_PIN(D9),
1863 ASPEED_PINCTRL_PIN(E1),
1864 ASPEED_PINCTRL_PIN(E10),
1865 ASPEED_PINCTRL_PIN(E12),
1866 ASPEED_PINCTRL_PIN(E13),
1867 ASPEED_PINCTRL_PIN(E14),
1868 ASPEED_PINCTRL_PIN(E15),
1869 ASPEED_PINCTRL_PIN(E16),
1870 ASPEED_PINCTRL_PIN(E17),
1871 ASPEED_PINCTRL_PIN(E18),
1872 ASPEED_PINCTRL_PIN(E19),
1873 ASPEED_PINCTRL_PIN(E2),
1874 ASPEED_PINCTRL_PIN(E20),
1875 ASPEED_PINCTRL_PIN(E21),
1876 ASPEED_PINCTRL_PIN(E22),
1877 ASPEED_PINCTRL_PIN(E3),
1878 ASPEED_PINCTRL_PIN(E6),
1879 ASPEED_PINCTRL_PIN(E7),
1880 ASPEED_PINCTRL_PIN(E9),
1881 ASPEED_PINCTRL_PIN(F1),
1882 ASPEED_PINCTRL_PIN(F17),
1883 ASPEED_PINCTRL_PIN(F18),
1884 ASPEED_PINCTRL_PIN(F19),
1885 ASPEED_PINCTRL_PIN(F2),
1886 ASPEED_PINCTRL_PIN(F20),
1887 ASPEED_PINCTRL_PIN(F21),
1888 ASPEED_PINCTRL_PIN(F22),
1889 ASPEED_PINCTRL_PIN(F3),
1890 ASPEED_PINCTRL_PIN(F4),
1891 ASPEED_PINCTRL_PIN(F5),
1892 ASPEED_PINCTRL_PIN(F9),
1893 ASPEED_PINCTRL_PIN(G1),
1894 ASPEED_PINCTRL_PIN(G17),
1895 ASPEED_PINCTRL_PIN(G18),
1896 ASPEED_PINCTRL_PIN(G2),
1897 ASPEED_PINCTRL_PIN(G20),
1898 ASPEED_PINCTRL_PIN(G21),
1899 ASPEED_PINCTRL_PIN(G22),
1900 ASPEED_PINCTRL_PIN(G3),
1901 ASPEED_PINCTRL_PIN(G4),
1902 ASPEED_PINCTRL_PIN(G5),
1903 ASPEED_PINCTRL_PIN(H18),
1904 ASPEED_PINCTRL_PIN(H19),
1905 ASPEED_PINCTRL_PIN(H20),
1906 ASPEED_PINCTRL_PIN(H21),
1907 ASPEED_PINCTRL_PIN(H22),
1908 ASPEED_PINCTRL_PIN(H3),
1909 ASPEED_PINCTRL_PIN(H4),
1910 ASPEED_PINCTRL_PIN(H5),
1911 ASPEED_PINCTRL_PIN(J18),
1912 ASPEED_PINCTRL_PIN(J19),
1913 ASPEED_PINCTRL_PIN(J20),
1914 ASPEED_PINCTRL_PIN(K18),
1915 ASPEED_PINCTRL_PIN(K19),
1916 ASPEED_PINCTRL_PIN(L1),
1917 ASPEED_PINCTRL_PIN(L18),
1918 ASPEED_PINCTRL_PIN(L19),
1919 ASPEED_PINCTRL_PIN(L2),
1920 ASPEED_PINCTRL_PIN(L3),
1921 ASPEED_PINCTRL_PIN(L4),
1922 ASPEED_PINCTRL_PIN(M18),
1923 ASPEED_PINCTRL_PIN(M19),
1924 ASPEED_PINCTRL_PIN(M20),
1925 ASPEED_PINCTRL_PIN(N1),
1926 ASPEED_PINCTRL_PIN(N18),
1927 ASPEED_PINCTRL_PIN(N19),
1928 ASPEED_PINCTRL_PIN(N2),
1929 ASPEED_PINCTRL_PIN(N20),
1930 ASPEED_PINCTRL_PIN(N21),
1931 ASPEED_PINCTRL_PIN(N22),
1932 ASPEED_PINCTRL_PIN(N3),
1933 ASPEED_PINCTRL_PIN(N4),
1934 ASPEED_PINCTRL_PIN(N5),
1935 ASPEED_PINCTRL_PIN(P1),
1936 ASPEED_PINCTRL_PIN(P18),
1937 ASPEED_PINCTRL_PIN(P19),
1938 ASPEED_PINCTRL_PIN(P2),
1939 ASPEED_PINCTRL_PIN(P20),
1940 ASPEED_PINCTRL_PIN(P21),
1941 ASPEED_PINCTRL_PIN(P22),
1942 ASPEED_PINCTRL_PIN(P3),
1943 ASPEED_PINCTRL_PIN(P4),
1944 ASPEED_PINCTRL_PIN(P5),
1945 ASPEED_PINCTRL_PIN(R1),
1946 ASPEED_PINCTRL_PIN(R18),
1947 ASPEED_PINCTRL_PIN(R19),
1948 ASPEED_PINCTRL_PIN(R2),
1949 ASPEED_PINCTRL_PIN(R20),
1950 ASPEED_PINCTRL_PIN(R21),
1951 ASPEED_PINCTRL_PIN(R22),
1952 ASPEED_PINCTRL_PIN(R3),
1953 ASPEED_PINCTRL_PIN(R4),
1954 ASPEED_PINCTRL_PIN(R5),
1955 ASPEED_PINCTRL_PIN(T1),
1956 ASPEED_PINCTRL_PIN(T17),
1957 ASPEED_PINCTRL_PIN(T19),
1958 ASPEED_PINCTRL_PIN(T2),
1959 ASPEED_PINCTRL_PIN(T20),
1960 ASPEED_PINCTRL_PIN(T21),
1961 ASPEED_PINCTRL_PIN(T22),
1962 ASPEED_PINCTRL_PIN(T3),
1963 ASPEED_PINCTRL_PIN(T4),
1964 ASPEED_PINCTRL_PIN(T5),
1965 ASPEED_PINCTRL_PIN(U1),
1966 ASPEED_PINCTRL_PIN(U19),
1967 ASPEED_PINCTRL_PIN(U2),
1968 ASPEED_PINCTRL_PIN(U20),
1969 ASPEED_PINCTRL_PIN(U21),
1970 ASPEED_PINCTRL_PIN(U22),
1971 ASPEED_PINCTRL_PIN(U3),
1972 ASPEED_PINCTRL_PIN(U4),
1973 ASPEED_PINCTRL_PIN(U5),
1974 ASPEED_PINCTRL_PIN(V1),
1975 ASPEED_PINCTRL_PIN(V19),
1976 ASPEED_PINCTRL_PIN(V2),
1977 ASPEED_PINCTRL_PIN(V20),
1978 ASPEED_PINCTRL_PIN(V21),
1979 ASPEED_PINCTRL_PIN(V22),
1980 ASPEED_PINCTRL_PIN(V3),
1981 ASPEED_PINCTRL_PIN(V4),
1982 ASPEED_PINCTRL_PIN(V5),
1983 ASPEED_PINCTRL_PIN(V6),
1984 ASPEED_PINCTRL_PIN(W1),
1985 ASPEED_PINCTRL_PIN(W19),
1986 ASPEED_PINCTRL_PIN(W2),
1987 ASPEED_PINCTRL_PIN(W20),
1988 ASPEED_PINCTRL_PIN(W21),
1989 ASPEED_PINCTRL_PIN(W22),
1990 ASPEED_PINCTRL_PIN(W3),
1991 ASPEED_PINCTRL_PIN(W4),
1992 ASPEED_PINCTRL_PIN(W5),
1993 ASPEED_PINCTRL_PIN(W6),
1994 ASPEED_PINCTRL_PIN(Y1),
1995 ASPEED_PINCTRL_PIN(Y19),
1996 ASPEED_PINCTRL_PIN(Y2),
1997 ASPEED_PINCTRL_PIN(Y20),
1998 ASPEED_PINCTRL_PIN(Y21),
1999 ASPEED_PINCTRL_PIN(Y22),
2000 ASPEED_PINCTRL_PIN(Y3),
2001 ASPEED_PINCTRL_PIN(Y4),
2002 ASPEED_PINCTRL_PIN(Y5),
2003 ASPEED_PINCTRL_PIN(Y6),
2004 };
2005
2006 static const struct aspeed_pin_group aspeed_g5_groups[] = {
2007 ASPEED_PINCTRL_GROUP(ACPI),
2008 ASPEED_PINCTRL_GROUP(ADC0),
2009 ASPEED_PINCTRL_GROUP(ADC1),
2010 ASPEED_PINCTRL_GROUP(ADC10),
2011 ASPEED_PINCTRL_GROUP(ADC11),
2012 ASPEED_PINCTRL_GROUP(ADC12),
2013 ASPEED_PINCTRL_GROUP(ADC13),
2014 ASPEED_PINCTRL_GROUP(ADC14),
2015 ASPEED_PINCTRL_GROUP(ADC15),
2016 ASPEED_PINCTRL_GROUP(ADC2),
2017 ASPEED_PINCTRL_GROUP(ADC3),
2018 ASPEED_PINCTRL_GROUP(ADC4),
2019 ASPEED_PINCTRL_GROUP(ADC5),
2020 ASPEED_PINCTRL_GROUP(ADC6),
2021 ASPEED_PINCTRL_GROUP(ADC7),
2022 ASPEED_PINCTRL_GROUP(ADC8),
2023 ASPEED_PINCTRL_GROUP(ADC9),
2024 ASPEED_PINCTRL_GROUP(BMCINT),
2025 ASPEED_PINCTRL_GROUP(DDCCLK),
2026 ASPEED_PINCTRL_GROUP(DDCDAT),
2027 ASPEED_PINCTRL_GROUP(ESPI),
2028 ASPEED_PINCTRL_GROUP(FWSPICS1),
2029 ASPEED_PINCTRL_GROUP(FWSPICS2),
2030 ASPEED_PINCTRL_GROUP(GPID0),
2031 ASPEED_PINCTRL_GROUP(GPID2),
2032 ASPEED_PINCTRL_GROUP(GPID4),
2033 ASPEED_PINCTRL_GROUP(GPID6),
2034 ASPEED_PINCTRL_GROUP(GPIE0),
2035 ASPEED_PINCTRL_GROUP(GPIE2),
2036 ASPEED_PINCTRL_GROUP(GPIE4),
2037 ASPEED_PINCTRL_GROUP(GPIE6),
2038 ASPEED_PINCTRL_GROUP(I2C10),
2039 ASPEED_PINCTRL_GROUP(I2C11),
2040 ASPEED_PINCTRL_GROUP(I2C12),
2041 ASPEED_PINCTRL_GROUP(I2C13),
2042 ASPEED_PINCTRL_GROUP(I2C14),
2043 ASPEED_PINCTRL_GROUP(I2C3),
2044 ASPEED_PINCTRL_GROUP(I2C4),
2045 ASPEED_PINCTRL_GROUP(I2C5),
2046 ASPEED_PINCTRL_GROUP(I2C6),
2047 ASPEED_PINCTRL_GROUP(I2C7),
2048 ASPEED_PINCTRL_GROUP(I2C8),
2049 ASPEED_PINCTRL_GROUP(I2C9),
2050 ASPEED_PINCTRL_GROUP(LAD0),
2051 ASPEED_PINCTRL_GROUP(LAD1),
2052 ASPEED_PINCTRL_GROUP(LAD2),
2053 ASPEED_PINCTRL_GROUP(LAD3),
2054 ASPEED_PINCTRL_GROUP(LCLK),
2055 ASPEED_PINCTRL_GROUP(LFRAME),
2056 ASPEED_PINCTRL_GROUP(LPCHC),
2057 ASPEED_PINCTRL_GROUP(LPCPD),
2058 ASPEED_PINCTRL_GROUP(LPCPLUS),
2059 ASPEED_PINCTRL_GROUP(LPCPME),
2060 ASPEED_PINCTRL_GROUP(LPCRST),
2061 ASPEED_PINCTRL_GROUP(LPCSMI),
2062 ASPEED_PINCTRL_GROUP(LSIRQ),
2063 ASPEED_PINCTRL_GROUP(MAC1LINK),
2064 ASPEED_PINCTRL_GROUP(MAC2LINK),
2065 ASPEED_PINCTRL_GROUP(MDIO1),
2066 ASPEED_PINCTRL_GROUP(MDIO2),
2067 ASPEED_PINCTRL_GROUP(NCTS1),
2068 ASPEED_PINCTRL_GROUP(NCTS2),
2069 ASPEED_PINCTRL_GROUP(NCTS3),
2070 ASPEED_PINCTRL_GROUP(NCTS4),
2071 ASPEED_PINCTRL_GROUP(NDCD1),
2072 ASPEED_PINCTRL_GROUP(NDCD2),
2073 ASPEED_PINCTRL_GROUP(NDCD3),
2074 ASPEED_PINCTRL_GROUP(NDCD4),
2075 ASPEED_PINCTRL_GROUP(NDSR1),
2076 ASPEED_PINCTRL_GROUP(NDSR2),
2077 ASPEED_PINCTRL_GROUP(NDSR3),
2078 ASPEED_PINCTRL_GROUP(NDSR4),
2079 ASPEED_PINCTRL_GROUP(NDTR1),
2080 ASPEED_PINCTRL_GROUP(NDTR2),
2081 ASPEED_PINCTRL_GROUP(NDTR3),
2082 ASPEED_PINCTRL_GROUP(NDTR4),
2083 ASPEED_PINCTRL_GROUP(NRI1),
2084 ASPEED_PINCTRL_GROUP(NRI2),
2085 ASPEED_PINCTRL_GROUP(NRI3),
2086 ASPEED_PINCTRL_GROUP(NRI4),
2087 ASPEED_PINCTRL_GROUP(NRTS1),
2088 ASPEED_PINCTRL_GROUP(NRTS2),
2089 ASPEED_PINCTRL_GROUP(NRTS3),
2090 ASPEED_PINCTRL_GROUP(NRTS4),
2091 ASPEED_PINCTRL_GROUP(OSCCLK),
2092 ASPEED_PINCTRL_GROUP(PEWAKE),
2093 ASPEED_PINCTRL_GROUP(PNOR),
2094 ASPEED_PINCTRL_GROUP(PWM0),
2095 ASPEED_PINCTRL_GROUP(PWM1),
2096 ASPEED_PINCTRL_GROUP(PWM2),
2097 ASPEED_PINCTRL_GROUP(PWM3),
2098 ASPEED_PINCTRL_GROUP(PWM4),
2099 ASPEED_PINCTRL_GROUP(PWM5),
2100 ASPEED_PINCTRL_GROUP(PWM6),
2101 ASPEED_PINCTRL_GROUP(PWM7),
2102 ASPEED_PINCTRL_GROUP(RGMII1),
2103 ASPEED_PINCTRL_GROUP(RGMII2),
2104 ASPEED_PINCTRL_GROUP(RMII1),
2105 ASPEED_PINCTRL_GROUP(RMII2),
2106 ASPEED_PINCTRL_GROUP(RXD1),
2107 ASPEED_PINCTRL_GROUP(RXD2),
2108 ASPEED_PINCTRL_GROUP(RXD3),
2109 ASPEED_PINCTRL_GROUP(RXD4),
2110 ASPEED_PINCTRL_GROUP(SALT1),
2111 ASPEED_PINCTRL_GROUP(SALT10),
2112 ASPEED_PINCTRL_GROUP(SALT11),
2113 ASPEED_PINCTRL_GROUP(SALT12),
2114 ASPEED_PINCTRL_GROUP(SALT13),
2115 ASPEED_PINCTRL_GROUP(SALT14),
2116 ASPEED_PINCTRL_GROUP(SALT2),
2117 ASPEED_PINCTRL_GROUP(SALT3),
2118 ASPEED_PINCTRL_GROUP(SALT4),
2119 ASPEED_PINCTRL_GROUP(SALT5),
2120 ASPEED_PINCTRL_GROUP(SALT6),
2121 ASPEED_PINCTRL_GROUP(SALT7),
2122 ASPEED_PINCTRL_GROUP(SALT8),
2123 ASPEED_PINCTRL_GROUP(SALT9),
2124 ASPEED_PINCTRL_GROUP(SCL1),
2125 ASPEED_PINCTRL_GROUP(SCL2),
2126 ASPEED_PINCTRL_GROUP(SD1),
2127 ASPEED_PINCTRL_GROUP(SD2),
2128 ASPEED_PINCTRL_GROUP(SDA1),
2129 ASPEED_PINCTRL_GROUP(SDA2),
2130 ASPEED_PINCTRL_GROUP(SGPS1),
2131 ASPEED_PINCTRL_GROUP(SGPS2),
2132 ASPEED_PINCTRL_GROUP(SIOONCTRL),
2133 ASPEED_PINCTRL_GROUP(SIOPBI),
2134 ASPEED_PINCTRL_GROUP(SIOPBO),
2135 ASPEED_PINCTRL_GROUP(SIOPWREQ),
2136 ASPEED_PINCTRL_GROUP(SIOPWRGD),
2137 ASPEED_PINCTRL_GROUP(SIOS3),
2138 ASPEED_PINCTRL_GROUP(SIOS5),
2139 ASPEED_PINCTRL_GROUP(SIOSCI),
2140 ASPEED_PINCTRL_GROUP(SPI1),
2141 ASPEED_PINCTRL_GROUP(SPI1CS1),
2142 ASPEED_PINCTRL_GROUP(SPI1DEBUG),
2143 ASPEED_PINCTRL_GROUP(SPI1PASSTHRU),
2144 ASPEED_PINCTRL_GROUP(SPI2CK),
2145 ASPEED_PINCTRL_GROUP(SPI2CS0),
2146 ASPEED_PINCTRL_GROUP(SPI2CS1),
2147 ASPEED_PINCTRL_GROUP(SPI2MISO),
2148 ASPEED_PINCTRL_GROUP(SPI2MOSI),
2149 ASPEED_PINCTRL_GROUP(TIMER3),
2150 ASPEED_PINCTRL_GROUP(TIMER4),
2151 ASPEED_PINCTRL_GROUP(TIMER5),
2152 ASPEED_PINCTRL_GROUP(TIMER6),
2153 ASPEED_PINCTRL_GROUP(TIMER7),
2154 ASPEED_PINCTRL_GROUP(TIMER8),
2155 ASPEED_PINCTRL_GROUP(TXD1),
2156 ASPEED_PINCTRL_GROUP(TXD2),
2157 ASPEED_PINCTRL_GROUP(TXD3),
2158 ASPEED_PINCTRL_GROUP(TXD4),
2159 ASPEED_PINCTRL_GROUP(UART6),
2160 ASPEED_PINCTRL_GROUP(USB11BHID),
2161 ASPEED_PINCTRL_GROUP(USB2AD),
2162 ASPEED_PINCTRL_GROUP(USB2AH),
2163 ASPEED_PINCTRL_GROUP(USB2BD),
2164 ASPEED_PINCTRL_GROUP(USB2BH),
2165 ASPEED_PINCTRL_GROUP(USBCKI),
2166 ASPEED_PINCTRL_GROUP(VGABIOSROM),
2167 ASPEED_PINCTRL_GROUP(VGAHS),
2168 ASPEED_PINCTRL_GROUP(VGAVS),
2169 ASPEED_PINCTRL_GROUP(VPI24),
2170 ASPEED_PINCTRL_GROUP(VPO),
2171 ASPEED_PINCTRL_GROUP(WDTRST1),
2172 ASPEED_PINCTRL_GROUP(WDTRST2),
2173 };
2174
2175 static const struct aspeed_pin_function aspeed_g5_functions[] = {
2176 ASPEED_PINCTRL_FUNC(ACPI),
2177 ASPEED_PINCTRL_FUNC(ADC0),
2178 ASPEED_PINCTRL_FUNC(ADC1),
2179 ASPEED_PINCTRL_FUNC(ADC10),
2180 ASPEED_PINCTRL_FUNC(ADC11),
2181 ASPEED_PINCTRL_FUNC(ADC12),
2182 ASPEED_PINCTRL_FUNC(ADC13),
2183 ASPEED_PINCTRL_FUNC(ADC14),
2184 ASPEED_PINCTRL_FUNC(ADC15),
2185 ASPEED_PINCTRL_FUNC(ADC2),
2186 ASPEED_PINCTRL_FUNC(ADC3),
2187 ASPEED_PINCTRL_FUNC(ADC4),
2188 ASPEED_PINCTRL_FUNC(ADC5),
2189 ASPEED_PINCTRL_FUNC(ADC6),
2190 ASPEED_PINCTRL_FUNC(ADC7),
2191 ASPEED_PINCTRL_FUNC(ADC8),
2192 ASPEED_PINCTRL_FUNC(ADC9),
2193 ASPEED_PINCTRL_FUNC(BMCINT),
2194 ASPEED_PINCTRL_FUNC(DDCCLK),
2195 ASPEED_PINCTRL_FUNC(DDCDAT),
2196 ASPEED_PINCTRL_FUNC(ESPI),
2197 ASPEED_PINCTRL_FUNC(FWSPICS1),
2198 ASPEED_PINCTRL_FUNC(FWSPICS2),
2199 ASPEED_PINCTRL_FUNC(GPID0),
2200 ASPEED_PINCTRL_FUNC(GPID2),
2201 ASPEED_PINCTRL_FUNC(GPID4),
2202 ASPEED_PINCTRL_FUNC(GPID6),
2203 ASPEED_PINCTRL_FUNC(GPIE0),
2204 ASPEED_PINCTRL_FUNC(GPIE2),
2205 ASPEED_PINCTRL_FUNC(GPIE4),
2206 ASPEED_PINCTRL_FUNC(GPIE6),
2207 ASPEED_PINCTRL_FUNC(I2C10),
2208 ASPEED_PINCTRL_FUNC(I2C11),
2209 ASPEED_PINCTRL_FUNC(I2C12),
2210 ASPEED_PINCTRL_FUNC(I2C13),
2211 ASPEED_PINCTRL_FUNC(I2C14),
2212 ASPEED_PINCTRL_FUNC(I2C3),
2213 ASPEED_PINCTRL_FUNC(I2C4),
2214 ASPEED_PINCTRL_FUNC(I2C5),
2215 ASPEED_PINCTRL_FUNC(I2C6),
2216 ASPEED_PINCTRL_FUNC(I2C7),
2217 ASPEED_PINCTRL_FUNC(I2C8),
2218 ASPEED_PINCTRL_FUNC(I2C9),
2219 ASPEED_PINCTRL_FUNC(LAD0),
2220 ASPEED_PINCTRL_FUNC(LAD1),
2221 ASPEED_PINCTRL_FUNC(LAD2),
2222 ASPEED_PINCTRL_FUNC(LAD3),
2223 ASPEED_PINCTRL_FUNC(LCLK),
2224 ASPEED_PINCTRL_FUNC(LFRAME),
2225 ASPEED_PINCTRL_FUNC(LPCHC),
2226 ASPEED_PINCTRL_FUNC(LPCPD),
2227 ASPEED_PINCTRL_FUNC(LPCPLUS),
2228 ASPEED_PINCTRL_FUNC(LPCPME),
2229 ASPEED_PINCTRL_FUNC(LPCRST),
2230 ASPEED_PINCTRL_FUNC(LPCSMI),
2231 ASPEED_PINCTRL_FUNC(LSIRQ),
2232 ASPEED_PINCTRL_FUNC(MAC1LINK),
2233 ASPEED_PINCTRL_FUNC(MAC2LINK),
2234 ASPEED_PINCTRL_FUNC(MDIO1),
2235 ASPEED_PINCTRL_FUNC(MDIO2),
2236 ASPEED_PINCTRL_FUNC(NCTS1),
2237 ASPEED_PINCTRL_FUNC(NCTS2),
2238 ASPEED_PINCTRL_FUNC(NCTS3),
2239 ASPEED_PINCTRL_FUNC(NCTS4),
2240 ASPEED_PINCTRL_FUNC(NDCD1),
2241 ASPEED_PINCTRL_FUNC(NDCD2),
2242 ASPEED_PINCTRL_FUNC(NDCD3),
2243 ASPEED_PINCTRL_FUNC(NDCD4),
2244 ASPEED_PINCTRL_FUNC(NDSR1),
2245 ASPEED_PINCTRL_FUNC(NDSR2),
2246 ASPEED_PINCTRL_FUNC(NDSR3),
2247 ASPEED_PINCTRL_FUNC(NDSR4),
2248 ASPEED_PINCTRL_FUNC(NDTR1),
2249 ASPEED_PINCTRL_FUNC(NDTR2),
2250 ASPEED_PINCTRL_FUNC(NDTR3),
2251 ASPEED_PINCTRL_FUNC(NDTR4),
2252 ASPEED_PINCTRL_FUNC(NRI1),
2253 ASPEED_PINCTRL_FUNC(NRI2),
2254 ASPEED_PINCTRL_FUNC(NRI3),
2255 ASPEED_PINCTRL_FUNC(NRI4),
2256 ASPEED_PINCTRL_FUNC(NRTS1),
2257 ASPEED_PINCTRL_FUNC(NRTS2),
2258 ASPEED_PINCTRL_FUNC(NRTS3),
2259 ASPEED_PINCTRL_FUNC(NRTS4),
2260 ASPEED_PINCTRL_FUNC(OSCCLK),
2261 ASPEED_PINCTRL_FUNC(PEWAKE),
2262 ASPEED_PINCTRL_FUNC(PNOR),
2263 ASPEED_PINCTRL_FUNC(PWM0),
2264 ASPEED_PINCTRL_FUNC(PWM1),
2265 ASPEED_PINCTRL_FUNC(PWM2),
2266 ASPEED_PINCTRL_FUNC(PWM3),
2267 ASPEED_PINCTRL_FUNC(PWM4),
2268 ASPEED_PINCTRL_FUNC(PWM5),
2269 ASPEED_PINCTRL_FUNC(PWM6),
2270 ASPEED_PINCTRL_FUNC(PWM7),
2271 ASPEED_PINCTRL_FUNC(RGMII1),
2272 ASPEED_PINCTRL_FUNC(RGMII2),
2273 ASPEED_PINCTRL_FUNC(RMII1),
2274 ASPEED_PINCTRL_FUNC(RMII2),
2275 ASPEED_PINCTRL_FUNC(RXD1),
2276 ASPEED_PINCTRL_FUNC(RXD2),
2277 ASPEED_PINCTRL_FUNC(RXD3),
2278 ASPEED_PINCTRL_FUNC(RXD4),
2279 ASPEED_PINCTRL_FUNC(SALT1),
2280 ASPEED_PINCTRL_FUNC(SALT10),
2281 ASPEED_PINCTRL_FUNC(SALT11),
2282 ASPEED_PINCTRL_FUNC(SALT12),
2283 ASPEED_PINCTRL_FUNC(SALT13),
2284 ASPEED_PINCTRL_FUNC(SALT14),
2285 ASPEED_PINCTRL_FUNC(SALT2),
2286 ASPEED_PINCTRL_FUNC(SALT3),
2287 ASPEED_PINCTRL_FUNC(SALT4),
2288 ASPEED_PINCTRL_FUNC(SALT5),
2289 ASPEED_PINCTRL_FUNC(SALT6),
2290 ASPEED_PINCTRL_FUNC(SALT7),
2291 ASPEED_PINCTRL_FUNC(SALT8),
2292 ASPEED_PINCTRL_FUNC(SALT9),
2293 ASPEED_PINCTRL_FUNC(SCL1),
2294 ASPEED_PINCTRL_FUNC(SCL2),
2295 ASPEED_PINCTRL_FUNC(SD1),
2296 ASPEED_PINCTRL_FUNC(SD2),
2297 ASPEED_PINCTRL_FUNC(SDA1),
2298 ASPEED_PINCTRL_FUNC(SDA2),
2299 ASPEED_PINCTRL_FUNC(SGPS1),
2300 ASPEED_PINCTRL_FUNC(SGPS2),
2301 ASPEED_PINCTRL_FUNC(SIOONCTRL),
2302 ASPEED_PINCTRL_FUNC(SIOPBI),
2303 ASPEED_PINCTRL_FUNC(SIOPBO),
2304 ASPEED_PINCTRL_FUNC(SIOPWREQ),
2305 ASPEED_PINCTRL_FUNC(SIOPWRGD),
2306 ASPEED_PINCTRL_FUNC(SIOS3),
2307 ASPEED_PINCTRL_FUNC(SIOS5),
2308 ASPEED_PINCTRL_FUNC(SIOSCI),
2309 ASPEED_PINCTRL_FUNC(SPI1),
2310 ASPEED_PINCTRL_FUNC(SPI1CS1),
2311 ASPEED_PINCTRL_FUNC(SPI1DEBUG),
2312 ASPEED_PINCTRL_FUNC(SPI1PASSTHRU),
2313 ASPEED_PINCTRL_FUNC(SPI2CK),
2314 ASPEED_PINCTRL_FUNC(SPI2CS0),
2315 ASPEED_PINCTRL_FUNC(SPI2CS1),
2316 ASPEED_PINCTRL_FUNC(SPI2MISO),
2317 ASPEED_PINCTRL_FUNC(SPI2MOSI),
2318 ASPEED_PINCTRL_FUNC(TIMER3),
2319 ASPEED_PINCTRL_FUNC(TIMER4),
2320 ASPEED_PINCTRL_FUNC(TIMER5),
2321 ASPEED_PINCTRL_FUNC(TIMER6),
2322 ASPEED_PINCTRL_FUNC(TIMER7),
2323 ASPEED_PINCTRL_FUNC(TIMER8),
2324 ASPEED_PINCTRL_FUNC(TXD1),
2325 ASPEED_PINCTRL_FUNC(TXD2),
2326 ASPEED_PINCTRL_FUNC(TXD3),
2327 ASPEED_PINCTRL_FUNC(TXD4),
2328 ASPEED_PINCTRL_FUNC(UART6),
2329 ASPEED_PINCTRL_FUNC(USB11BHID),
2330 ASPEED_PINCTRL_FUNC(USB2AD),
2331 ASPEED_PINCTRL_FUNC(USB2AH),
2332 ASPEED_PINCTRL_FUNC(USB2BD),
2333 ASPEED_PINCTRL_FUNC(USB2BH),
2334 ASPEED_PINCTRL_FUNC(USBCKI),
2335 ASPEED_PINCTRL_FUNC(VGABIOSROM),
2336 ASPEED_PINCTRL_FUNC(VGAHS),
2337 ASPEED_PINCTRL_FUNC(VGAVS),
2338 ASPEED_PINCTRL_FUNC(VPI24),
2339 ASPEED_PINCTRL_FUNC(VPO),
2340 ASPEED_PINCTRL_FUNC(WDTRST1),
2341 ASPEED_PINCTRL_FUNC(WDTRST2),
2342 };
2343
2344 static struct aspeed_pin_config aspeed_g5_configs[] = {
2345 /* GPIOA, GPIOQ */
2346 { PIN_CONFIG_BIAS_PULL_DOWN, { B14, B13 }, SCU8C, 16 },
2347 { PIN_CONFIG_BIAS_DISABLE, { B14, B13 }, SCU8C, 16 },
2348 { PIN_CONFIG_BIAS_PULL_DOWN, { A11, N20 }, SCU8C, 16 },
2349 { PIN_CONFIG_BIAS_DISABLE, { A11, N20 }, SCU8C, 16 },
2350
2351 /* GPIOB, GPIOR */
2352 { PIN_CONFIG_BIAS_PULL_DOWN, { K19, H20 }, SCU8C, 17 },
2353 { PIN_CONFIG_BIAS_DISABLE, { K19, H20 }, SCU8C, 17 },
2354 { PIN_CONFIG_BIAS_PULL_DOWN, { AA19, E10 }, SCU8C, 17 },
2355 { PIN_CONFIG_BIAS_DISABLE, { AA19, E10 }, SCU8C, 17 },
2356
2357 /* GPIOC, GPIOS*/
2358 { PIN_CONFIG_BIAS_PULL_DOWN, { C12, B11 }, SCU8C, 18 },
2359 { PIN_CONFIG_BIAS_DISABLE, { C12, B11 }, SCU8C, 18 },
2360 { PIN_CONFIG_BIAS_PULL_DOWN, { V20, AA20 }, SCU8C, 18 },
2361 { PIN_CONFIG_BIAS_DISABLE, { V20, AA20 }, SCU8C, 18 },
2362
2363 /* GPIOD, GPIOY */
2364 { PIN_CONFIG_BIAS_PULL_DOWN, { F19, C21 }, SCU8C, 19 },
2365 { PIN_CONFIG_BIAS_DISABLE, { F19, C21 }, SCU8C, 19 },
2366 { PIN_CONFIG_BIAS_PULL_DOWN, { R22, P20 }, SCU8C, 19 },
2367 { PIN_CONFIG_BIAS_DISABLE, { R22, P20 }, SCU8C, 19 },
2368
2369 /* GPIOE, GPIOZ */
2370 { PIN_CONFIG_BIAS_PULL_DOWN, { B20, B19 }, SCU8C, 20 },
2371 { PIN_CONFIG_BIAS_DISABLE, { B20, B19 }, SCU8C, 20 },
2372 { PIN_CONFIG_BIAS_PULL_DOWN, { Y20, W21 }, SCU8C, 20 },
2373 { PIN_CONFIG_BIAS_DISABLE, { Y20, W21 }, SCU8C, 20 },
2374
2375 /* GPIOF, GPIOAA */
2376 { PIN_CONFIG_BIAS_PULL_DOWN, { J19, H18 }, SCU8C, 21 },
2377 { PIN_CONFIG_BIAS_DISABLE, { J19, H18 }, SCU8C, 21 },
2378 { PIN_CONFIG_BIAS_PULL_DOWN, { Y21, P19 }, SCU8C, 21 },
2379 { PIN_CONFIG_BIAS_DISABLE, { Y21, P19 }, SCU8C, 21 },
2380
2381 /* GPIOG, GPIOAB */
2382 { PIN_CONFIG_BIAS_PULL_DOWN, { A19, E14 }, SCU8C, 22 },
2383 { PIN_CONFIG_BIAS_DISABLE, { A19, E14 }, SCU8C, 22 },
2384 { PIN_CONFIG_BIAS_PULL_DOWN, { N19, R20 }, SCU8C, 22 },
2385 { PIN_CONFIG_BIAS_DISABLE, { N19, R20 }, SCU8C, 22 },
2386
2387 /* GPIOH, GPIOAC */
2388 { PIN_CONFIG_BIAS_PULL_DOWN, { A18, D18 }, SCU8C, 23 },
2389 { PIN_CONFIG_BIAS_DISABLE, { A18, D18 }, SCU8C, 23 },
2390 { PIN_CONFIG_BIAS_PULL_DOWN, { G21, G22 }, SCU8C, 23 },
2391 { PIN_CONFIG_BIAS_DISABLE, { G21, G22 }, SCU8C, 23 },
2392
2393 /* GPIOs [I, P] */
2394 { PIN_CONFIG_BIAS_PULL_DOWN, { C18, A15 }, SCU8C, 24 },
2395 { PIN_CONFIG_BIAS_DISABLE, { C18, A15 }, SCU8C, 24 },
2396 { PIN_CONFIG_BIAS_PULL_DOWN, { R2, T3 }, SCU8C, 25 },
2397 { PIN_CONFIG_BIAS_DISABLE, { R2, T3 }, SCU8C, 25 },
2398 { PIN_CONFIG_BIAS_PULL_DOWN, { L3, R1 }, SCU8C, 26 },
2399 { PIN_CONFIG_BIAS_DISABLE, { L3, R1 }, SCU8C, 26 },
2400 { PIN_CONFIG_BIAS_PULL_DOWN, { T2, W1 }, SCU8C, 27 },
2401 { PIN_CONFIG_BIAS_DISABLE, { T2, W1 }, SCU8C, 27 },
2402 { PIN_CONFIG_BIAS_PULL_DOWN, { Y1, T5 }, SCU8C, 28 },
2403 { PIN_CONFIG_BIAS_DISABLE, { Y1, T5 }, SCU8C, 28 },
2404 { PIN_CONFIG_BIAS_PULL_DOWN, { V2, T4 }, SCU8C, 29 },
2405 { PIN_CONFIG_BIAS_DISABLE, { V2, T4 }, SCU8C, 29 },
2406 { PIN_CONFIG_BIAS_PULL_DOWN, { U5, W4 }, SCU8C, 30 },
2407 { PIN_CONFIG_BIAS_DISABLE, { U5, W4 }, SCU8C, 30 },
2408 { PIN_CONFIG_BIAS_PULL_DOWN, { V4, V6 }, SCU8C, 31 },
2409 { PIN_CONFIG_BIAS_DISABLE, { V4, V6 }, SCU8C, 31 },
2410
2411 /* GPIOs T[0-5] (RGMII1 Tx pins) */
2412 { PIN_CONFIG_DRIVE_STRENGTH, { B5, B5 }, SCU90, 8 },
2413 { PIN_CONFIG_DRIVE_STRENGTH, { E9, A5 }, SCU90, 9 },
2414 { PIN_CONFIG_BIAS_PULL_DOWN, { B5, D7 }, SCU90, 12 },
2415 { PIN_CONFIG_BIAS_DISABLE, { B5, D7 }, SCU90, 12 },
2416
2417 /* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */
2418 { PIN_CONFIG_DRIVE_STRENGTH, { B2, B2 }, SCU90, 10 },
2419 { PIN_CONFIG_DRIVE_STRENGTH, { B1, B3 }, SCU90, 11 },
2420 { PIN_CONFIG_BIAS_PULL_DOWN, { B2, D4 }, SCU90, 14 },
2421 { PIN_CONFIG_BIAS_DISABLE, { B2, D4 }, SCU90, 14 },
2422
2423 /* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */
2424 { PIN_CONFIG_BIAS_PULL_DOWN, { B4, C4 }, SCU90, 13 },
2425 { PIN_CONFIG_BIAS_DISABLE, { B4, C4 }, SCU90, 13 },
2426
2427 /* GPIOs V[2-7] (RGMII2 Rx pins) */
2428 { PIN_CONFIG_BIAS_PULL_DOWN, { C2, E6 }, SCU90, 15 },
2429 { PIN_CONFIG_BIAS_DISABLE, { C2, E6 }, SCU90, 15 },
2430
2431 /* ADC pull-downs (SCUA8[19:4]) */
2432 { PIN_CONFIG_BIAS_PULL_DOWN, { F4, F4 }, SCUA8, 4 },
2433 { PIN_CONFIG_BIAS_DISABLE, { F4, F4 }, SCUA8, 4 },
2434 { PIN_CONFIG_BIAS_PULL_DOWN, { F5, F5 }, SCUA8, 5 },
2435 { PIN_CONFIG_BIAS_DISABLE, { F5, F5 }, SCUA8, 5 },
2436 { PIN_CONFIG_BIAS_PULL_DOWN, { E2, E2 }, SCUA8, 6 },
2437 { PIN_CONFIG_BIAS_DISABLE, { E2, E2 }, SCUA8, 6 },
2438 { PIN_CONFIG_BIAS_PULL_DOWN, { E1, E1 }, SCUA8, 7 },
2439 { PIN_CONFIG_BIAS_DISABLE, { E1, E1 }, SCUA8, 7 },
2440 { PIN_CONFIG_BIAS_PULL_DOWN, { F3, F3 }, SCUA8, 8 },
2441 { PIN_CONFIG_BIAS_DISABLE, { F3, F3 }, SCUA8, 8 },
2442 { PIN_CONFIG_BIAS_PULL_DOWN, { E3, E3 }, SCUA8, 9 },
2443 { PIN_CONFIG_BIAS_DISABLE, { E3, E3 }, SCUA8, 9 },
2444 { PIN_CONFIG_BIAS_PULL_DOWN, { G5, G5 }, SCUA8, 10 },
2445 { PIN_CONFIG_BIAS_DISABLE, { G5, G5 }, SCUA8, 10 },
2446 { PIN_CONFIG_BIAS_PULL_DOWN, { G4, G4 }, SCUA8, 11 },
2447 { PIN_CONFIG_BIAS_DISABLE, { G4, G4 }, SCUA8, 11 },
2448 { PIN_CONFIG_BIAS_PULL_DOWN, { F2, F2 }, SCUA8, 12 },
2449 { PIN_CONFIG_BIAS_DISABLE, { F2, F2 }, SCUA8, 12 },
2450 { PIN_CONFIG_BIAS_PULL_DOWN, { G3, G3 }, SCUA8, 13 },
2451 { PIN_CONFIG_BIAS_DISABLE, { G3, G3 }, SCUA8, 13 },
2452 { PIN_CONFIG_BIAS_PULL_DOWN, { G2, G2 }, SCUA8, 14 },
2453 { PIN_CONFIG_BIAS_DISABLE, { G2, G2 }, SCUA8, 14 },
2454 { PIN_CONFIG_BIAS_PULL_DOWN, { F1, F1 }, SCUA8, 15 },
2455 { PIN_CONFIG_BIAS_DISABLE, { F1, F1 }, SCUA8, 15 },
2456 { PIN_CONFIG_BIAS_PULL_DOWN, { H5, H5 }, SCUA8, 16 },
2457 { PIN_CONFIG_BIAS_DISABLE, { H5, H5 }, SCUA8, 16 },
2458 { PIN_CONFIG_BIAS_PULL_DOWN, { G1, G1 }, SCUA8, 17 },
2459 { PIN_CONFIG_BIAS_DISABLE, { G1, G1 }, SCUA8, 17 },
2460 { PIN_CONFIG_BIAS_PULL_DOWN, { H3, H3 }, SCUA8, 18 },
2461 { PIN_CONFIG_BIAS_DISABLE, { H3, H3 }, SCUA8, 18 },
2462 { PIN_CONFIG_BIAS_PULL_DOWN, { H4, H4 }, SCUA8, 19 },
2463 { PIN_CONFIG_BIAS_DISABLE, { H4, H4 }, SCUA8, 19 },
2464
2465 /*
2466 * Debounce settings for GPIOs D and E passthrough mode are in
2467 * SCUA8[27:20] and so are managed by pinctrl. Normal GPIO debounce for
2468 * banks D and E is handled by the GPIO driver - GPIO passthrough is
2469 * treated like any other non-GPIO mux function. There is a catch
2470 * however, in that the debounce period is configured in the GPIO
2471 * controller. Due to this tangle between GPIO and pinctrl we don't yet
2472 * fully support pass-through debounce.
2473 */
2474 { PIN_CONFIG_INPUT_DEBOUNCE, { F19, E21 }, SCUA8, 20 },
2475 { PIN_CONFIG_INPUT_DEBOUNCE, { F20, D20 }, SCUA8, 21 },
2476 { PIN_CONFIG_INPUT_DEBOUNCE, { D21, E20 }, SCUA8, 22 },
2477 { PIN_CONFIG_INPUT_DEBOUNCE, { G18, C21 }, SCUA8, 23 },
2478 { PIN_CONFIG_INPUT_DEBOUNCE, { B20, C20 }, SCUA8, 24 },
2479 { PIN_CONFIG_INPUT_DEBOUNCE, { F18, F17 }, SCUA8, 25 },
2480 { PIN_CONFIG_INPUT_DEBOUNCE, { E18, D19 }, SCUA8, 26 },
2481 { PIN_CONFIG_INPUT_DEBOUNCE, { A20, B19 }, SCUA8, 27 },
2482 };
2483
2484 static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = {
2485 .pins = aspeed_g5_pins,
2486 .npins = ARRAY_SIZE(aspeed_g5_pins),
2487 .groups = aspeed_g5_groups,
2488 .ngroups = ARRAY_SIZE(aspeed_g5_groups),
2489 .functions = aspeed_g5_functions,
2490 .nfunctions = ARRAY_SIZE(aspeed_g5_functions),
2491 .configs = aspeed_g5_configs,
2492 .nconfigs = ARRAY_SIZE(aspeed_g5_configs),
2493 };
2494
2495 static const struct pinmux_ops aspeed_g5_pinmux_ops = {
2496 .get_functions_count = aspeed_pinmux_get_fn_count,
2497 .get_function_name = aspeed_pinmux_get_fn_name,
2498 .get_function_groups = aspeed_pinmux_get_fn_groups,
2499 .set_mux = aspeed_pinmux_set_mux,
2500 .gpio_request_enable = aspeed_gpio_request_enable,
2501 .strict = true,
2502 };
2503
2504 static const struct pinctrl_ops aspeed_g5_pinctrl_ops = {
2505 .get_groups_count = aspeed_pinctrl_get_groups_count,
2506 .get_group_name = aspeed_pinctrl_get_group_name,
2507 .get_group_pins = aspeed_pinctrl_get_group_pins,
2508 .pin_dbg_show = aspeed_pinctrl_pin_dbg_show,
2509 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
2510 .dt_free_map = pinctrl_utils_free_map,
2511 };
2512
2513 static const struct pinconf_ops aspeed_g5_conf_ops = {
2514 .is_generic = true,
2515 .pin_config_get = aspeed_pin_config_get,
2516 .pin_config_set = aspeed_pin_config_set,
2517 .pin_config_group_get = aspeed_pin_config_group_get,
2518 .pin_config_group_set = aspeed_pin_config_group_set,
2519 };
2520
2521 static struct pinctrl_desc aspeed_g5_pinctrl_desc = {
2522 .name = "aspeed-g5-pinctrl",
2523 .pins = aspeed_g5_pins,
2524 .npins = ARRAY_SIZE(aspeed_g5_pins),
2525 .pctlops = &aspeed_g5_pinctrl_ops,
2526 .pmxops = &aspeed_g5_pinmux_ops,
2527 .confops = &aspeed_g5_conf_ops,
2528 };
2529
aspeed_g5_pinctrl_probe(struct platform_device * pdev)2530 static int aspeed_g5_pinctrl_probe(struct platform_device *pdev)
2531 {
2532 int i;
2533 struct regmap *map;
2534 struct device_node *node;
2535
2536 for (i = 0; i < ARRAY_SIZE(aspeed_g5_pins); i++)
2537 aspeed_g5_pins[i].number = i;
2538
2539 node = of_parse_phandle(pdev->dev.of_node, "aspeed,external-nodes", 0);
2540 map = syscon_node_to_regmap(node);
2541 of_node_put(node);
2542 if (IS_ERR(map)) {
2543 dev_warn(&pdev->dev, "No GFX phandle found, some mux configurations may fail\n");
2544 map = NULL;
2545 }
2546 aspeed_g5_pinctrl_data.maps[ASPEED_IP_GFX] = map;
2547
2548 node = of_parse_phandle(pdev->dev.of_node, "aspeed,external-nodes", 1);
2549 if (node) {
2550 map = syscon_node_to_regmap(node->parent);
2551 if (IS_ERR(map)) {
2552 dev_warn(&pdev->dev, "LHC parent is not a syscon, some mux configurations may fail\n");
2553 map = NULL;
2554 }
2555 } else {
2556 dev_warn(&pdev->dev, "No LHC phandle found, some mux configurations may fail\n");
2557 map = NULL;
2558 }
2559 of_node_put(node);
2560 aspeed_g5_pinctrl_data.maps[ASPEED_IP_LPC] = map;
2561
2562 return aspeed_pinctrl_probe(pdev, &aspeed_g5_pinctrl_desc,
2563 &aspeed_g5_pinctrl_data);
2564 }
2565
2566 static const struct of_device_id aspeed_g5_pinctrl_of_match[] = {
2567 { .compatible = "aspeed,ast2500-pinctrl", },
2568 { .compatible = "aspeed,g5-pinctrl", },
2569 { },
2570 };
2571
2572 static struct platform_driver aspeed_g5_pinctrl_driver = {
2573 .probe = aspeed_g5_pinctrl_probe,
2574 .driver = {
2575 .name = "aspeed-g5-pinctrl",
2576 .of_match_table = aspeed_g5_pinctrl_of_match,
2577 },
2578 };
2579
aspeed_g5_pinctrl_init(void)2580 static int aspeed_g5_pinctrl_init(void)
2581 {
2582 return platform_driver_register(&aspeed_g5_pinctrl_driver);
2583 }
2584
2585 arch_initcall(aspeed_g5_pinctrl_init);
2586
