Lines Matching full:were
26 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
35 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM at…
44 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on…
62 "BriefDescription": "Counts demand data reads that were supplied by DRAM.",
71 …"BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, …
80 …"BriefDescription": "Counts demand data reads that were supplied by PMM attached to this socket, w…
89 "BriefDescription": "Counts demand data reads that were supplied by PMM.",
98 …"BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socke…
107 …"BriefDescription": "Counts demand data reads that were supplied by PMM attached to another socket…
116 …"BriefDescription": "Counts demand data reads that were supplied by DRAM on a distant memory contr…
134 … requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
143 …requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM at…
152 …requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on…
188 …"BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local…
215 …quests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.",
224 …uests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM at…
233 …uests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM at…
242 …uests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM att…
251 …etches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 ca…
260 …uests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM at…
269 …uests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or…
278 …uests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM att…
287 …uests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on…