Lines Matching +full:max +full:- +full:reason

21 …MAX. The reset value to the counter is not clocked immediately so the overflow status bit will fli…
29 …MAX. The reset value to the counter is not clocked immediately so the overflow status bit will fli…
36 …ons associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may hav…
44 …ay change from time to time due to power or thermal throttling. For this reason, this event may ha…
48         "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
51 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
56         "BriefDescription": "Number of instructions retired. General Counter - architectural event",
60 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
72 … the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end r…
75 …-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution…
80 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
82 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
87 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
90 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. Th…
95 …orrelates with higher performance  for example, as measured by the instructions-per-cycle metric.",
98 …e instructions-per-cycle metric.\nSoftware can use this event as the numerator for the Retiring me…