Lines Matching +full:instruction +full:- +full:fetch
11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to …
17 …cles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong …
23 …prediction=correct) for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
24 …(prediction=correct) for all data types ( demand load,data,inst prefetch,inst fetch,xlate (I or d)"
29 …cope was group pump for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
30 …group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
35 … Initial Pump Scope for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
41 …l Pump Scope (Chip) for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
42 …s chip pumpfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
47 … all types of pumps for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
48 …es of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
53 … all types of pumps for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
54 …es of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
59 …ope was system pump for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
60 …ystem pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
65 …een smaller. Counts for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
71 … Scope (Chip/Group) for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
72 … or Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
113 …to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that re…
161 …ed. I-form branches do not set this event. In addition, B-form branches which do not use the BHT d…
167 …ed. I-form branches do not set this event. In addition, B-form branches which do not use the BHT d…
197 …ional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set thi…
203 …ional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set thi…
215 …t used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch …
221 …t used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch …
305 "BriefDescription": "Completion stall due to VSU scalar instruction",
311 "BriefDescription": "Completion stall due to VSU scalar long latency instruction",
323 "BriefDescription": "Completion stall due to VSU vector instruction",
329 "BriefDescription": "Completion stall due to VSU vector long instruction",
335 "BriefDescription": "Completion stall due to VSU instruction",
359 "BriefDescription": "IFU Finished a (non-branch) instruction",
683 "BriefDescription": "BCD->DPD opcode finish (denbcd, denbcdq)",
713 "BriefDescription": "Dispatch/CLB Hold: Sync type instruction",
803 …"BriefDescription": "XL-form branch was mispredicted due to the predicted target address missing f…
887 "BriefDescription": "Convert instruction executed",
893 "BriefDescription": "Estimate instruction executed",
899 "BriefDescription": "Round to single precision instruction executed",
905 "BriefDescription": "Convert instruction executed",
911 "BriefDescription": "Estimate instruction executed",
917 "BriefDescription": "Round to single precision instruction executed",
977 …"BriefDescription": "The fixed point unit Unit 0 finished an instruction. Instructions that finish…
1061 "BriefDescription": "GCT Utilization 11-14 entries",
1067 "BriefDescription": "GCT Utilization 15-17 entries",
1079 "BriefDescription": "GCT Utilization 1-2 entries",
1085 "BriefDescription": "GCT Utilization 3-6 entries",
1091 "BriefDescription": "GCT Utilization 7-10 entries",
1097 "BriefDescription": "Group experienced non-speculative branch redirect",
1098 "PublicDescription": "Group experienced Non-speculative br mispredicct"
1115 "BriefDescription": "Group experienced non-speculative I cache miss",
1116 "PublicDescription": "Group experi enced Non-specu lative I cache miss"
1121 "BriefDescription": "Instruction Marked",
1122 "PublicDescription": "Instruction marked in idu"
1181 "BriefDescription": "Demand Instruction fetch request",
1211 "BriefDescription": "Instruction prefetch requests",
1217 "BriefDescription": "Instruction prefetch written into IL1",
1235 …: "Initial and Final Pump Scope was chip pump (prediction=correct) for instruction fetches and pre…
1236 …ope and data sourced across this scope was chip pump (prediction=correct) for an instruction fetch"
1241 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different …
1242 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different …
1247 …Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different No…
1248 …Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different No…
1253 …n": "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or …
1254 …s Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due…
1259 …": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or …
1260 …s Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) du…
1265 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to in…
1266 …ion": "The processor's Instruction cache was reloaded from local core's L2 due to either an instru…
1271 …": "The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 o…
1272 …s Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip du…
1277 …n": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on…
1278 …'s Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due…
1283 …cription": "The processor's Instruction cache was reloaded from a location other than the local co…
1284 …ocessor's Instruction cache was reloaded from a location other than the local core's L2 due to eit…
1289 …ription": "The processor's Instruction cache was reloaded from local core's L2 with load hit store…
1290 …essor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to ei…
1295 …escription": "The processor's Instruction cache was reloaded from local core's L2 with dispatch co…
1296 …rocessor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to eithe…
1301 … "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflic…
1302 …Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. …
1307 …efDescription": "The processor's Instruction cache was reloaded from local core's L2 without confl…
1308 …e processor's Instruction cache was reloaded from local core's L2 without conflict due to either a…
1313 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to in…
1314 …ion": "The processor's Instruction cache was reloaded from local core's L3 due to either an instru…
1319 … "The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3…
1320 …Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip …
1325 …: "The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 …
1326 … Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip d…
1331 …": "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 o…
1332 …s Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip du…
1337 …n": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on…
1338 …'s Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due…
1343 …tion": "The processor's Instruction cache was reloaded from a location other than the local core's…
1344 …ocessor's Instruction cache was reloaded from a location other than the local core's L3 due to eit…
1349 …escription": "The processor's Instruction cache was reloaded from local core's L3 with dispatch co…
1350 …rocessor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to eithe…
1355 … "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts h…
1356 …Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. …
1361 …efDescription": "The processor's Instruction cache was reloaded from local core's L3 without confl…
1362 …e processor's Instruction cache was reloaded from local core's L3 without conflict due to either a…
1367 …BriefDescription": "The processor's Instruction cache was reloaded from the local chip's L4 cache …
1368 … "The processor's Instruction cache was reloaded from the local chip's L4 cache due to either an i…
1373 …"BriefDescription": "The processor's Instruction cache was reloaded from the local chip's Memory d…
1374 …: "The processor's Instruction cache was reloaded from the local chip's Memory due to either an in…
1379 …: "The processor's Instruction cache was reloaded from a memory location including L4 from local r…
1380 … Instruction cache was reloaded from a memory location including L4 from local remote or distant d…
1385 …'s Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a di…
1386 …Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a diffe…
1391 …he processor's Instruction cache was reloaded either shared or modified data from another core's L…
1392 …Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the sam…
1397 … Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same No…
1398 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Nod…
1403 …s Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Nod…
1404 …Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node …
1409 …on": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Gr…
1410 …r's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due …
1415 …": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or …
1416 …s Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) du…
1421 … "Initial and Final Pump Scope was group pump (prediction=correct) for instruction fetches and pre…
1422 …al and Final Pump Scope and data sourced across this scope was group pump for an instruction fetch"
1427 … (Group) ended up either larger or smaller than Initial Pump Scope for instruction fetches and pre…
1433 … Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for instruction fetches and pre…
1434 …Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor an instruction fetch"
1439 …"BriefDescription": "Pump prediction correct. Counts across all types of pumps for instruction fet…
1440 …icDescription": "Pump prediction correct. Counts across all types of pumpsfor an instruction fetch"
1445 …"BriefDescription": "Pump misprediction. Counts across all types of pumps for instruction fetches …
1446 …"PublicDescription": "Pump Mis prediction Counts across all types of pumpsfor an instruction fetch"
1451 …"Initial and Final Pump Scope was system pump (prediction=correct) for instruction fetches and pre…
1452 …l and Final Pump Scope and data sourced across this scope was system pump for an instruction fetch"
1457 … original scope was System and it should have been smaller. Counts for instruction fetches and pre…
1463 …cope (system) ended up larger than Initial Pump Scope (Chip/Group) for instruction fetches and pre…
1464 …get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for an instruction fetch"
1469 "BriefDescription": "Instruction fetches from L1",
1475 …The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on th…
1476 …s Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip du…
1481 …"The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the…
1482 …'s Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due…
1487 …e processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on …
1488 …Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip …
1493 …he processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on t…
1494 … Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip d…
1499 …The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on th…
1500 …s Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip du…
1505 …"The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the…
1506 …'s Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due…
1523 … with Modified (M) data from another core's L2 on the same chip due to a instruction side request",
1529 …LB with Shared (S) data from another core's L2 on the same chip due to a instruction side request",
1535 … into the TLB from local core's L2 with load hit store conflict due to a instruction side request",
1541 …loaded into the TLB from local core's L2 with dispatch conflict due to a instruction side request",
1547 …h Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request",
1553 …ith Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request",
1559 … with Modified (M) data from another core's L3 on the same chip due to a instruction side request",
1565 …LB with Shared (S) data from another core's L3 on the same chip due to a instruction side request",
1571 …"BriefDescription": "valid when first beat of data comes in for an i-side fetch where data came fr…
1697 "BriefDescription": "Instruction Demand sectors wriittent into IL1",
1721 "BriefDescription": "All successful D-side store dispatches for this thread",
1727 "BriefDescription": "All successful D-side store dispatches for this thread that were L2 Miss",
2003 "BriefDescription": "LS0 Non-cachable Loads counted at finish",
2004 "PublicDescription": "LS0 Non-cachable Loads counted at finishLSU0 non-cacheable loads"
2093 "BriefDescription": "LS1 Non-cachable Loads counted at finish",
2094 "PublicDescription": "LS1 Non-cachable Loads counted at finishLSU1 non-cacheable loads"
2363 …"BriefDescription": "Per thread - use edge detect to count allocates On a per thread basis, level …
2381 …"BriefDescription": "Per thread - use edge detect to count allocates On a per thread basis, level …
2417 "BriefDescription": "Non-cachable Stores sent to nest",
2418 "PublicDescription": "Non-cachable Stores sent to nest42"
2441 …"BriefDescription": "Per thread - use edge detect to count allocates On a per thread basis, level …
2501 "BriefDescription": "IFU non-branch finished",
2502 "PublicDescription": "IFU non-branch marked instruction finished"
2651 …"BriefDescription": "Marked instruction Finish Stall cycles (marked finish after NTC) (use edge de…
2652 …"PublicDescription": "Marked instruction Finish Stall cycles (marked finish after NTC) (use edge d…
2657 "BriefDescription": "marked instruction finished (completed)",
2867 …"BriefDescription": "Number of times the RC machine for a sampled instruction was active for more …
2873 …"BriefDescription": "Number of times the RC machine for a sampled instruction was active for more …
2879 …"BriefDescription": "Number of times the RC machine for a sampled instruction was active for more …
2885 …"BriefDescription": "Number of times the RC machine for a sampled instruction was active for more …
2904 "PublicDescription": "Cycles run latch is set and core is in SMT2-shared mode"
2909 "BriefDescription": "Cycles run latch is set and core is in SMT2-split mode",
2927 "BriefDescription": "Store-Hit-Load Table Entry Created",
2933 "BriefDescription": "Store-Hit-Load Table Read Hit with entry Enabled",
2939 …"BriefDescription": "Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to …
3179 "BriefDescription": "Complex VMX instruction issued",
3185 "BriefDescription": "Cryptographic instruction RFC02196 Issued",
3227 "BriefDescription": "VSU0 Finished an instruction",
3239 "BriefDescription": "Move to/from FPSCR type instruction issued on Pipe 0",
3251 "BriefDescription": "Permute VMX Instruction Issued",
3257 "BriefDescription": "Double Precision scalar instruction issued on Pipe0",
3263 "BriefDescription": "Simple VMX instruction issued",
3287 "BriefDescription": "Double Precision vector instruction issued on Pipe0",
3293 "BriefDescription": "Single Precision vector instruction issued (executed)",
3329 "BriefDescription": "Complex VMX instruction issued",
3335 "BriefDescription": "Cryptographic instruction RFC02196 Issued",
3377 "BriefDescription": "VSU1 Finished an instruction",
3389 "BriefDescription": "Move to/from FPSCR type instruction issued on Pipe 0",
3401 "BriefDescription": "Permute VMX Instruction Issued",
3407 "BriefDescription": "Double Precision scalar instruction issued on Pipe1",
3413 "BriefDescription": "Simple VMX instruction issued",
3437 "BriefDescription": "Double Precision vector instruction issued on Pipe1",
3443 "BriefDescription": "Single Precision vector instruction issued (executed)",