Lines Matching refs:P1
122 P1()
133 CPU and P1() represents the read() routine running on another. The
135 Thus, P0 stores the data in buf and then sets flag. Meanwhile, P1
154 A memory model will predict what values P1 might obtain for its loads
163 instance, P1 might run entirely before P0 begins, in which case r1 and
164 r2 will both be 0 at the end. Or P0 might run entirely before P1
168 routines run concurrently. One possibility is that P1 runs after P0's
170 will again both be 0. (If P1 had been designed to read buf
197 Since r1 = 1, P0 must store 1 to flag before P1 loads 1 from
200 P1 loads from flag before loading from buf, since CPUs execute
203 P1 must load 0 from buf before P0 stores 1 to it; otherwise r2
236 P1()
272 X: P1 loads 1 from flag executes before
273 Y: P1 loads 0 from buf executes before
570 P1()
594 P1()
601 If r1 = 0x56781234 (little-endian!) at the end, then P1 must have read
702 P1()
717 READ_ONCE() in P1, on Itanium it sometimes could end up with r1 = 5
1172 P1()
1181 can malfunction on Alpha systems (notice that P1 uses an ordinary load
1186 smp_wmb() forces P0's store to x to propagate to P1 before the store
1187 to ptr does. And since P1 can't execute its second load
1189 first load, the value x = 1 must have propagated to P1 before the
1193 stores do reach P1's local cache in the proper order, it can happen
1196 value may not become available for P1's CPU to read until after the
1206 between P1's two loads when the kernel is compiled for the Alpha
1213 P1()
1222 then we would never get r1 = &x and r2 = 0. By the time P1 executed
1294 P1()
1304 event, because P1's store came after P0's store in x's coherence
1305 order, and P1's store propagated to P0 before P0's load executed.
1320 P1()
1330 because P1's store overwrote the value read by P0's first load, and
1331 P1's store propagated to P0 before P0's second load executed.
1346 P1()
1357 from P1's second load to its first (backwards!). The reason is
1358 similar to the previous examples: The value P1 loads from buf gets
1360 to buf will propagate to P1 before the store to flag does, and the
1361 store to flag propagates to P1 before P1 reads flag.
1364 P1 must execute its second load before the first. Indeed, if the load
1366 have propagated to P1 by the time P1's load from buf executed, so r2
1371 But what if we put an smp_rmb() fence between P1's loads? The fence
1398 P1()
1415 overwritten by P1's store since x = 2 at the end (a coe link), the
1416 smp_wmb() ensures that P1's store to x propagates to P2 before the
1486 P1()
1495 If r0 = 0 at the end then there is a pb link from P0's load to P1's
1496 load: an fre link from P0's load to P1's store (which overwrites the
1497 value read by P0), and a strong fence between P1's store and its load.
1502 Similarly, if r1 = 0 at the end then there is a pb link from P1's load
1555 P1()
1566 means that P0's store to x propagated to P1 before P1 called
1568 P1's grace period, contrary to part (2) of the Guarantee. On the
1570 end of the critical section, did not propagate to P1 before the end of
1765 P1()
1776 P1's load at W reads from, so we have W ->fre Y. Since S ->po W and
1780 If r1 = 1 at the end then P1's load at Z reads from P0's store at X,
1803 P1()
1830 P0 P1 P2
1848 section in P0 both starts before P1's grace period does and ends
1849 before it does, and the critical section in P2 both starts after P1's
1974 P1()
1982 Assuming that P1 executes after P0 and does read the index value
2077 P1()
2129 P1()
2148 If r1 = 1 at the end then the spin_lock() in P1 must have read from
2151 if P1 had used a lock variable different from s, the writes could have
2153 P1 had all executed on a single CPU, as in the example before this
2195 P1()
2202 P1's store to x propagates to P0 before P0's load from x executes.
2218 NULL pointer, because P1's store to x might propagate to P0 after the
2330 P1()
2342 means that the store to buf must propagate from P0 to P1 before Z
2411 P1()
2432 at the machine level, must propagate to P1 before X's store to
2436 Y is a valid indicator that X propagated to P1 before Y
2441 The smp_rmb() fence in P1 is a compiler barrier as well as a
2447 Thus U's store to buf is forced to propagate to P1 before V's load
2528 P1()
2546 stores will propagate to P1 in that order. However, rcu_dereference()
2549 that the load of ptr in P1 is r-pre-bounded before the load of *p
2594 P1()
2602 Do the plain stores to y race? Clearly not if P1 reads a non-zero
2604 means that the read-side critical section in P1 must finish executing
2607 P1 before the critical section started and so would have been visible
2612 This means there is an rcu-fence link from P1's "y = 2" store to P0's
2613 "y = 3" store, and consequently the first must propagate from P1 to P0
2615 concurrent and there is no race, even though P1's plain store to y
2798 P1()
2809 you it is not, but the model won't mention that this is because P1