Lines Matching +full:1 +full:- +full:7
8 1, 0, EAX, 3:0, stepping, Stepping ID
9 1, 0, EAX, 7:4, model, Model
10 1, 0, EAX, 11:8, family, Family ID
11 1, 0, EAX, 13:12, processor, Processor Type
12 1, 0, EAX, 19:16, model_ext, Extended Model ID
13 1, 0, EAX, 27:20, family_ext, Extended Family ID
15 1, 0, EBX, 7:0, brand, Brand Index
16 1, 0, EBX, 15:8, clflush_size, CLFLUSH line size (value * 8) in bytes
17 1, 0, EBX, 23:16, max_cpu_id, Maxim number of addressable logic cpu in this package
18 1, 0, EBX, 31:24, apic_id, Initial APIC ID
20 1, 0, ECX, 0, sse3, Streaming SIMD Extensions 3(SSE3)
21 1, 0, ECX, 1, pclmulqdq, PCLMULQDQ instruction supported
22 1, 0, ECX, 2, dtes64, DS area uses 64-bit layout
23 1, 0, ECX, 3, mwait, MONITOR/MWAIT supported
24 …1, 0, ECX, 4, ds_cpl, CPL Qualified Debug Store which allows for branch message storage q…
25 1, 0, ECX, 5, vmx, Virtual Machine Extensions supported
26 1, 0, ECX, 6, smx, Safer Mode Extension supported
27 1, 0, ECX, 7, eist, Enhanced Intel SpeedStep Technology
28 1, 0, ECX, 8, tm2, Thermal Monitor 2
29 1, 0, ECX, 9, ssse3, Supplemental Streaming SIMD Extensions 3 (SSSE3)
30 …1, 0, ECX, 10, l1_ctx_id, L1 data cache could be set to either adaptive mode or shared mod…
31 1, 0, ECX, 11, sdbg, IA32_DEBUG_INTERFACE MSR for silicon debug supported
32 1, 0, ECX, 12, fma, FMA extensions using YMM state supported
33 1, 0, ECX, 13, cmpxchg16b, 'CMPXCHG16B - Compare and Exchange Bytes' supported
34 1, 0, ECX, 14, xtpr_update, xTPR Update Control supported
35 1, 0, ECX, 15, pdcm, Perfmon and Debug Capability present
36 1, 0, ECX, 17, pcid, Process-Context Identifiers feature present
37 1, 0, ECX, 18, dca, Prefetching data from a memory mapped device supported
38 1, 0, ECX, 19, sse4_1, SSE4.1 feature present
39 1, 0, ECX, 20, sse4_2, SSE4.2 feature present
40 1, 0, ECX, 21, x2apic, x2APIC supported
41 1, 0, ECX, 22, movbe, MOVBE instruction supported
42 1, 0, ECX, 23, popcnt, POPCNT instruction supported
43 …1, 0, ECX, 24, tsc_deadline_timer, LAPIC supports one-shot operation using a TSC deadline …
44 1, 0, ECX, 25, aesni, AESNI instruction supported
45 1, 0, ECX, 26, xsave, XSAVE/XRSTOR processor extended states (XSETBV/XGETBV/XCR0)
46 1, 0, ECX, 27, osxsave, OS has set CR4.OSXSAVE bit to enable XSETBV/XGETBV/XCR0
47 1, 0, ECX, 28, avx, AVX instruction supported
48 1, 0, ECX, 29, f16c, 16-bit floating-point conversion instruction supported
49 1, 0, ECX, 30, rdrand, RDRAND instruction supported
51 1, 0, EDX, 0, fpu, x87 FPU on chip
52 1, 0, EDX, 1, vme, Virtual-8086 Mode Enhancement
53 1, 0, EDX, 2, de, Debugging Extensions
54 1, 0, EDX, 3, pse, Page Size Extensions
55 1, 0, EDX, 4, tsc, Time Stamp Counter
56 1, 0, EDX, 5, msr, RDMSR and WRMSR Support
57 1, 0, EDX, 6, pae, Physical Address Extensions
58 1, 0, EDX, 7, mce, Machine Check Exception
59 1, 0, EDX, 8, cx8, CMPXCHG8B instr
60 1, 0, EDX, 9, apic, APIC on Chip
61 1, 0, EDX, 11, sep, SYSENTER and SYSEXIT instrs
62 1, 0, EDX, 12, mtrr, Memory Type Range Registers
63 1, 0, EDX, 13, pge, Page Global Bit
64 1, 0, EDX, 14, mca, Machine Check Architecture
65 1, 0, EDX, 15, cmov, Conditional Move Instrs
66 1, 0, EDX, 16, pat, Page Attribute Table
67 1, 0, EDX, 17, pse36, 36-Bit Page Size Extension
68 1, 0, EDX, 18, psn, Processor Serial Number
69 1, 0, EDX, 19, clflush, CLFLUSH instr
70 # 1, 0, EDX, 20,
71 1, 0, EDX, 21, ds, Debug Store
72 1, 0, EDX, 22, acpi, Thermal Monitor and Software Controlled Clock Facilities
73 1, 0, EDX, 23, mmx, Intel MMX Technology
74 1, 0, EDX, 24, fxsr, XSAVE and FXRSTOR Instrs
75 1, 0, EDX, 25, sse, SSE
76 1, 0, EDX, 26, sse2, SSE2
77 1, 0, EDX, 27, ss, Self Snoop
78 1, 0, EDX, 28, hit, Max APIC IDs
79 1, 0, EDX, 29, tm, Thermal Monitor
80 # 1, 0, EDX, 30,
81 1, 0, EDX, 31, pbe, Pending Break Enable
93 4, 0, EAX, 7:5, cache_level, Cache Level (starts at 1)
103 4, 0, ECX, 31:0, cache_sets, Number of Sets - 1
104 …4, 0, EDX, 0, c_wbinvd, 1 means WBINVD/INVD is not ganranteed to act upon lower level cac…
105 4, 0, EDX, 1, c_incl, Whether cache is inclusive of lower cache level
112 5, 0, ECX, 0, mwait_ext, Enum of Monitor-Mwait extensions supported
113 5, 0, ECX, 1, mwait_irq_break, Largest monitor line size in bytes
114 5, 0, EDX, 3:0, c0_sub_stats, Number of C0* sub C-states supported using MWAIT
115 5, 0, EDX, 7:4, c1_sub_stats, Number of C1* sub C-states supported using MWAIT
116 5, 0, EDX, 11:8, c2_sub_stats, Number of C2* sub C-states supported using MWAIT
117 5, 0, EDX, 15:12, c3_sub_stats, Number of C3* sub C-states supported using MWAIT
118 5, 0, EDX, 19:16, c4_sub_stats, Number of C4* sub C-states supported using MWAIT
119 5, 0, EDX, 23:20, c5_sub_stats, Number of C5* sub C-states supported using MWAIT
120 5, 0, EDX, 27:24, c6_sub_stats, Number of C6* sub C-states supported using MWAIT
121 5, 0, EDX, 31:28, c7_sub_stats, Number of C7* sub C-states supported using MWAIT
127 6, 0, EAX, 1, turbo, Intel Turbo Boost
133 6, 0, EAX, 7, hwp, HWP base register
150 6, 0, ECX, 3, energ_bias, Performance-energy bias preference supported
154 # AVX512 refers to https://en.wikipedia.org/wiki/AVX-512
157 7, 0, EBX, 0, fsgsbase, RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE supported
158 7, 0, EBX, 1, tsc_adjust, TSC_ADJUST MSR supported
159 7, 0, EBX, 2, sgx, Software Guard Extensions
160 7, 0, EBX, 3, bmi1, BMI1
161 7, 0, EBX, 4, hle, Hardware Lock Elision
162 7, 0, EBX, 5, avx2, AVX2
163 # 7, 0, EBX, 6, fdp_excp_only, x87 FPU Data Pointer updated only on x87 exceptions
164 7, 0, EBX, 7, smep, Supervisor-Mode Execution Prevention
165 7, 0, EBX, 8, bmi2, BMI2
166 7, 0, EBX, 9, rep_movsb, Enhanced REP MOVSB/STOSB
167 7, 0, EBX, 10, invpcid, INVPCID instruction
168 7, 0, EBX, 11, rtm, Restricted Transactional Memory
169 7, 0, EBX, 12, rdt_m, Intel RDT Monitoring capability
170 7, 0, EBX, 13, depc_fpu_cs_ds, Deprecates FPU CS and FPU DS
171 7, 0, EBX, 14, mpx, Memory Protection Extensions
172 7, 0, EBX, 15, rdt_a, Intel RDT Allocation capability
173 7, 0, EBX, 16, avx512f, AVX512 Foundation instr
174 7, 0, EBX, 17, avx512dq, AVX512 Double and Quadword AVX512 instr
175 7, 0, EBX, 18, rdseed, RDSEED instr
176 7, 0, EBX, 19, adx, ADX instr
177 7, 0, EBX, 20, smap, Supervisor Mode Access Prevention
178 7, 0, EBX, 21, avx512ifma, AVX512 Integer Fused Multiply Add
179 # 7, 0, EBX, 22, resvd, resvd
180 7, 0, EBX, 23, clflushopt, CLFLUSHOPT instr
181 7, 0, EBX, 24, clwb, CLWB instr
182 7, 0, EBX, 25, intel_pt, Intel Processor Trace instr
183 7, 0, EBX, 26, avx512pf, Prefetch
184 7, 0, EBX, 27, avx512er, AVX512 Exponent Reciproca instr
185 7, 0, EBX, 28, avx512cd, AVX512 Conflict Detection instr
186 7, 0, EBX, 29, sha, Intel Secure Hash Algorithm Extensions instr
187 7, 0, EBX, 30, avx512bw, AVX512 Byte & Word instr
188 7, 0, EBX, 31, avx512vl, AVX512 Vector Length Extentions (VL)
189 7, 0, ECX, 0, prefetchwt1, X
190 7, 0, ECX, 1, avx512vbmi, AVX512 Vector Byte Manipulation Instructions
191 7, 0, ECX, 2, umip, User-mode Instruction Prevention
193 7, 0, ECX, 3, pku, Protection Keys for User-mode pages
194 7, 0, ECX, 4, ospke, CR4 PKE set to enable protection keys
195 # 7, 0, ECX, 16:5, resvd, resvd
196 …7, 0, ECX, 21:17, mawau, The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-…
197 7, 0, ECX, 22, rdpid, RDPID and IA32_TSC_AUX
198 # 7, 0, ECX, 29:23, resvd, resvd
199 7, 0, ECX, 30, sgx_lc, SGX Launch Configuration
200 # 7, 0, ECX, 31, resvd, resvd
216 0xA, 0, EAX, 7:0, pmu_ver, Performance Monitoring Unit version
217 0xA, 0, EAX, 15:8, pmu_gp_cnt_num, Numer of general-purose PMU counters per logical CPU
222 0xA, 0, EBX, 1, pmu_no_instr_ret_evt, Instruction retired event not available
224 0xA, 0, EBX, 3, pmu_no_llc_ref_evt, Last-level cache reference event not available
225 0xA, 0, EBX, 4, pmu_no_llc_mis_evt, Last-level cache misses event not available
238 0xB, 0, ECX, 15:8, lvl_type, 0-Invalid 1-SMT 2-Core
246 0xD, 0, EAX, 1, sse, SSE state
249 0xD, 0, EAX, 7:5, avx512, AVX-512 state
255 0xD, 1, EAX, 0, xsaveopt, XSAVEOPT available
256 0xD, 1, EAX, 1, xsavec, XSAVEC and compacted form supported
257 0xD, 1, EAX, 2, xgetbv, XGETBV supported
258 0xD, 1, EAX, 3, xsaves, XSAVES/XRSTORS and IA32_XSS supported
260 … 0xD, 1, EBX, 31:0, max_sz_xcr0, Maximum size (bytes) required by enabled features in XCR0
261 0xD, 1, ECX, 8, pt, PT state
262 0xD, 1, ECX, 11, cet_usr, CET user state
263 0xD, 1, ECX, 12, cet_supv, CET supervisor state
264 0xD, 1, ECX, 13, hdc, HDC state
265 0xD, 1, ECX, 16, hwp, HWP state
270 …0xF, 0, EBX, 31:0, rmid_range, Maximum range (zero-based) of RMID within this physical proce…
271 0xF, 0, EDX, 1, l3c_rdt_mon, L3 Cache RDT Monitoring supported
273 0xF, 1, ECX, 31:0, rmid_range, Maximum range (zero-based) of RMID of this types
274 0xF, 1, EDX, 0, l3c_ocp_mon, L3 Cache occupancy Monitoring supported
275 0xF, 1, EDX, 1, l3c_tbw_mon, L3 Cache Total Bandwidth Monitoring supported
276 0xF, 1, EDX, 2, l3c_lbw_mon, L3 Cache Local Bandwidth Monitoring supported
281 0x10, 0, EBX, 1, l3c_rdt_alloc, L3 Cache Allocation supported
292 0x12, 1, EAX, 0, sgx2, L3 Cache Allocation supported
314 # System-On-Chip Vendor Attribute
316 0x17, 0, EAX, 31:0, max_socid, Maximum input value of supported sub-leaf
330 # Leaf 1AH
333 0x1A, 0, EAX, 31:24, core_type, 20H-Intel_Atom 40H-Intel_Core
336 # Leaf 1FH
337 # V2 Extended Topology - A preferred superset to leaf 0BH
341 # 40000000H - 4FFFFFFFH is invalid range
354 0x80000001, 0, ECX, 0, lahf_lm, LAHF/SAHF available in 64-bit mode
355 0x80000001, 0, ECX, 1, cmplegacy, Core multi-processing legacy mode
361 0x80000001, 0, ECX, 7, misalignsse, Misaligned SSE Mode
363 0x80000001, 0, ECX, 9, osvw, OS Visible Work-around support
369 0x80000001, 0, ECX, 16, fma4, Four-operand FMA instruction support
372 0x80000001, 0, ECX, 23, perfctrextcore, Indicates support for Core::X86::Msr::PERF_CTL0 - 5…
375 0x80000001, 0, ECX, 27, perftsc, Performance time-stamp counter supported
380 0x80000001, 0, EDX, 0, fpu, x87 floating point unit on-chip
381 0x80000001, 0, EDX, 1, vme, Virtual-mode enhancements
383 0x80000001, 0, EDX, 3, pse, Page-size extensions (4 MB pages)
385 0x80000001, 0, EDX, 5, msr, Model-specific registers (MSRs), with RDMSR and WRMSR instruct…
386 0x80000001, 0, EDX, 6, pae, Physical-address extensions (PAE)
387 0x80000001, 0, EDX, 7, mce, Machine Check Exception, CR4.MCE
391 0x80000001, 0, EDX, 12, mtrr, Memory-type range registers
396 0x80000001, 0, EDX, 17, pse36, Page-size extensions
402 0x80000001, 0, EDX, 26, 1gb_page, 1GB page supported
417 0x80000006, 0, ECX, 7:0, clsize, Cache Line size in bytes
419 0x80000006, 0, ECX, 31:16, csize, Cache size in 1K units
429 0x80000008, 0, EAX, 7:0, phy_adr_bits, Physical Address Bits
437 0x8000001E, 0, EBX, 7:0, core_id, Identifies the logical core ID
438 0x8000001E, 0, EBX, 15:8, threads_per_core, The number of threads per core is threads_per_core + 1
440 0x8000001E, 0, ECX, 7:0, node_id, Node ID
441 0x8000001E, 0, ECX, 10:8, nodes_per_processor, Nodes per processor { 0: 1 node, else reserved }
445 0x8000001F, 0, EAX, 1, sev, Secure Encrypted Virtualization
448 0x8000001F, 0, EBX, 5:0, c-bit, Page table bit number used to enable memory encryption
450 0x8000001F, 0, ECX, 31:0, num_encrypted_guests, Maximum ASID value that may be used for an SEV-en…
451 …0, minimum_sev_asid, Minimum ASID value that must be used for an SEV-enabled, SEV-ES-disabled guest