Lines Matching refs:swm
205 regmap_write(r, A2RBNMAPCTR0(sub->swm->rb.hw), in aio_init()
206 MAPCTR0_EN | sub->swm->rb.map); in aio_init()
207 regmap_write(r, A2CHNMAPCTR0(sub->swm->ch.hw), in aio_init()
208 MAPCTR0_EN | sub->swm->ch.map); in aio_init()
210 switch (sub->swm->type) { in aio_init()
214 if (sub->swm->dir == PORT_DIR_INPUT) { in aio_init()
215 regmap_write(r, A2IIFNMAPCTR0(sub->swm->iif.hw), in aio_init()
216 MAPCTR0_EN | sub->swm->iif.map); in aio_init()
217 regmap_write(r, A2IPORTNMAPCTR0(sub->swm->iport.hw), in aio_init()
218 MAPCTR0_EN | sub->swm->iport.map); in aio_init()
220 regmap_write(r, A2OIFNMAPCTR0(sub->swm->oif.hw), in aio_init()
221 MAPCTR0_EN | sub->swm->oif.map); in aio_init()
222 regmap_write(r, A2OPORTNMAPCTR0(sub->swm->oport.hw), in aio_init()
223 MAPCTR0_EN | sub->swm->oport.map); in aio_init()
227 regmap_write(r, A2OIFNMAPCTR0(sub->swm->oif.hw), in aio_init()
228 MAPCTR0_EN | sub->swm->oif.map); in aio_init()
229 regmap_write(r, A2OPORTNMAPCTR0(sub->swm->oport.hw), in aio_init()
230 MAPCTR0_EN | sub->swm->oport.map); in aio_init()
231 regmap_write(r, A2CHNMAPCTR0(sub->swm->och.hw), in aio_init()
232 MAPCTR0_EN | sub->swm->och.map); in aio_init()
233 regmap_write(r, A2IIFNMAPCTR0(sub->swm->iif.hw), in aio_init()
234 MAPCTR0_EN | sub->swm->iif.map); in aio_init()
237 dev_err(dev, "Unknown port type %d.\n", sub->swm->type); in aio_init()
254 if (sub->swm->dir == PORT_DIR_OUTPUT) { in aio_port_reset()
255 regmap_write(r, AOUTRSTCTR0, BIT(sub->swm->oport.map)); in aio_port_reset()
256 regmap_write(r, AOUTRSTCTR1, BIT(sub->swm->oport.map)); in aio_port_reset()
258 regmap_update_bits(r, IPORTMXRSTCTR(sub->swm->iport.map), in aio_port_reset()
261 regmap_update_bits(r, IPORTMXRSTCTR(sub->swm->iport.map), in aio_port_reset()
309 regmap_update_bits(r, OPORTMXTYSLOTCTR(sub->swm->oport.map, i), in aio_port_set_ch()
311 regmap_update_bits(r, OPORTMXTYSLOTCTR(sub->swm->oport.map, i), in aio_port_set_ch()
336 if (sub->swm->dir == PORT_DIR_OUTPUT) { in aio_port_set_rate()
382 regmap_update_bits(r, OPORTMXCTR1(sub->swm->oport.map), in aio_port_set_rate()
430 regmap_update_bits(r, IPORTMXCTR1(sub->swm->iport.map), in aio_port_set_rate()
455 if (sub->swm->dir == PORT_DIR_OUTPUT) { in aio_port_set_fmt()
473 regmap_update_bits(r, OPORTMXCTR1(sub->swm->oport.map), in aio_port_set_fmt()
495 regmap_update_bits(r, IPORTMXCTR1(sub->swm->iport.map), in aio_port_set_fmt()
531 if (sub->swm->dir == PORT_DIR_OUTPUT) { in aio_port_set_clk()
532 if (sub->swm->type == PORT_TYPE_I2S) { in aio_port_set_clk()
558 } else if (sub->swm->type == PORT_TYPE_EVE) { in aio_port_set_clk()
563 } else if (sub->swm->type == PORT_TYPE_SPDIF) { in aio_port_set_clk()
589 regmap_write(r, OPORTMXCTR2(sub->swm->oport.map), v); in aio_port_set_clk()
595 regmap_write(r, IPORTMXCTR2(sub->swm->iport.map), v); in aio_port_set_clk()
622 if (sub->swm->type == PORT_TYPE_EVE || in aio_port_set_param()
623 sub->swm->type == PORT_TYPE_CONV) { in aio_port_set_param()
646 if (sub->swm->dir == PORT_DIR_OUTPUT) { in aio_port_set_param()
657 regmap_write(r, OPORTMXCTR3(sub->swm->oport.map), v); in aio_port_set_param()
659 regmap_write(r, IPORTMXACLKSEL0EX(sub->swm->iport.map), in aio_port_set_param()
661 regmap_write(r, IPORTMXEXNOE(sub->swm->iport.map), in aio_port_set_param()
679 if (sub->swm->dir == PORT_DIR_OUTPUT) { in aio_port_set_enable()
680 regmap_write(r, OPORTMXPATH(sub->swm->oport.map), in aio_port_set_enable()
681 sub->swm->oif.map); in aio_port_set_enable()
683 regmap_update_bits(r, OPORTMXMASK(sub->swm->oport.map), in aio_port_set_enable()
694 regmap_write(r, AOUTENCTR0, BIT(sub->swm->oport.map)); in aio_port_set_enable()
696 regmap_write(r, AOUTENCTR1, BIT(sub->swm->oport.map)); in aio_port_set_enable()
698 regmap_update_bits(r, IPORTMXMASK(sub->swm->iport.map), in aio_port_set_enable()
706 IPORTMXCTR2(sub->swm->iport.map), in aio_port_set_enable()
711 IPORTMXCTR2(sub->swm->iport.map), in aio_port_set_enable()
728 regmap_read(r, OPORTMXTYVOLGAINSTATUS(sub->swm->oport.map, 0), &v); in aio_port_get_volume()
745 int oport_map = sub->swm->oport.map; in aio_port_set_volume()
748 if (sub->swm->dir == PORT_DIR_INPUT) in aio_port_set_volume()
791 if (sub->swm->dir == PORT_DIR_OUTPUT) { in aio_if_set_param()
812 regmap_write(r, PBOUTMXCTR0(sub->swm->oif.map), v); in aio_if_set_param()
813 regmap_write(r, PBOUTMXCTR1(sub->swm->oif.map), 0); in aio_if_set_param()
815 regmap_write(r, PBINMXCTR(sub->swm->iif.map), in aio_if_set_param()
818 (sub->swm->iport.map << PBINMXCTR_PBINSEL_SHIFT) | in aio_if_set_param()
883 regmap_write(r, OPORTMXREPET(sub->swm->oport.map), repet); in aio_oport_set_stream_type()
884 regmap_write(r, OPORTMXPAUDAT(sub->swm->oport.map), pause); in aio_oport_set_stream_type()
901 if (sub->swm->dir != PORT_DIR_OUTPUT) in aio_src_reset()
904 regmap_write(r, AOUTSRCRSTCTR0, BIT(sub->swm->oport.map)); in aio_src_reset()
905 regmap_write(r, AOUTSRCRSTCTR1, BIT(sub->swm->oport.map)); in aio_src_reset()
925 if (sub->swm->dir != PORT_DIR_OUTPUT) in aio_src_set_param()
928 regmap_write(r, OPORTMXSRC1CTR(sub->swm->oport.map), in aio_src_set_param()
954 regmap_write(r, OPORTMXRATE_I(sub->swm->oport.map), in aio_src_set_param()
957 regmap_update_bits(r, OPORTMXRATE_I(sub->swm->oport.map), in aio_src_set_param()
968 regmap_write(r, PBINMXCTR(sub->swm->iif.map), in aio_srcif_set_param()
971 (sub->swm->oport.map << PBINMXCTR_PBINSEL_SHIFT) | in aio_srcif_set_param()
982 regmap_write(r, CDA2D_CHMXCTRL1(sub->swm->och.map), in aio_srcch_set_param()
985 regmap_write(r, CDA2D_CHMXSRCAMODE(sub->swm->och.map), in aio_srcch_set_param()
990 regmap_write(r, CDA2D_CHMXDSTAMODE(sub->swm->och.map), in aio_srcch_set_param()
994 (sub->swm->och.map << CDA2D_CHMXAMODE_RSSEL_SHIFT)); in aio_srcch_set_param()
1010 v | BIT(sub->swm->och.map)); in aio_srcch_set_enable()
1018 regmap_write(r, CDA2D_CHMXCTRL1(sub->swm->ch.map), in aiodma_ch_set_param()
1024 (sub->swm->rb.map << CDA2D_CHMXAMODE_RSSEL_SHIFT); in aiodma_ch_set_param()
1025 if (sub->swm->dir == PORT_DIR_OUTPUT) in aiodma_ch_set_param()
1026 regmap_write(r, CDA2D_CHMXSRCAMODE(sub->swm->ch.map), v); in aiodma_ch_set_param()
1028 regmap_write(r, CDA2D_CHMXDSTAMODE(sub->swm->ch.map), v); in aiodma_ch_set_param()
1039 CDA2D_STRT0_STOP_START | BIT(sub->swm->ch.map)); in aiodma_ch_set_enable()
1042 BIT(sub->swm->rb.map), in aiodma_ch_set_enable()
1043 BIT(sub->swm->rb.map)); in aiodma_ch_set_enable()
1046 CDA2D_STRT0_STOP_STOP | BIT(sub->swm->ch.map)); in aiodma_ch_set_enable()
1049 BIT(sub->swm->rb.map), in aiodma_ch_set_enable()
1061 CDA2D_RDPTRLOAD_LSFLAG_STORE | BIT(sub->swm->rb.map)); in aiodma_rb_get_rp()
1064 regmap_read(r, CDA2D_RBMXRDPTR(sub->swm->rb.map), &pos_l); in aiodma_rb_get_rp()
1066 regmap_read(r, CDA2D_RBMXRDPTR(sub->swm->rb.map), &pos_l); in aiodma_rb_get_rp()
1067 regmap_read(r, CDA2D_RBMXRDPTRU(sub->swm->rb.map), &pos_u); in aiodma_rb_get_rp()
1079 regmap_write(r, CDA2D_RBMXRDPTR(sub->swm->rb.map), (u32)pos); in aiodma_rb_set_rp()
1080 regmap_write(r, CDA2D_RBMXRDPTRU(sub->swm->rb.map), (u32)(pos >> 32)); in aiodma_rb_set_rp()
1081 regmap_write(r, CDA2D_RDPTRLOAD, BIT(sub->swm->rb.map)); in aiodma_rb_set_rp()
1084 regmap_read(r, CDA2D_RBMXRDPTR(sub->swm->rb.map), &tmp); in aiodma_rb_set_rp()
1094 CDA2D_WRPTRLOAD_LSFLAG_STORE | BIT(sub->swm->rb.map)); in aiodma_rb_get_wp()
1097 regmap_read(r, CDA2D_RBMXWRPTR(sub->swm->rb.map), &pos_l); in aiodma_rb_get_wp()
1099 regmap_read(r, CDA2D_RBMXWRPTR(sub->swm->rb.map), &pos_l); in aiodma_rb_get_wp()
1100 regmap_read(r, CDA2D_RBMXWRPTRU(sub->swm->rb.map), &pos_u); in aiodma_rb_get_wp()
1112 regmap_write(r, CDA2D_RBMXWRPTR(sub->swm->rb.map), in aiodma_rb_set_wp()
1114 regmap_write(r, CDA2D_RBMXWRPTRU(sub->swm->rb.map), in aiodma_rb_set_wp()
1116 regmap_write(r, CDA2D_WRPTRLOAD, BIT(sub->swm->rb.map)); in aiodma_rb_set_wp()
1119 regmap_read(r, CDA2D_RBMXWRPTR(sub->swm->rb.map), &tmp); in aiodma_rb_set_wp()
1129 regmap_write(r, CDA2D_RBMXBTH(sub->swm->rb.map), th); in aiodma_rb_set_threshold()
1130 regmap_write(r, CDA2D_RBMXRTH(sub->swm->rb.map), th); in aiodma_rb_set_threshold()
1145 regmap_write(r, CDA2D_RBMXCNFG(sub->swm->rb.map), 0); in aiodma_rb_set_buffer()
1146 regmap_write(r, CDA2D_RBMXBGNADRS(sub->swm->rb.map), in aiodma_rb_set_buffer()
1148 regmap_write(r, CDA2D_RBMXBGNADRSU(sub->swm->rb.map), in aiodma_rb_set_buffer()
1150 regmap_write(r, CDA2D_RBMXENDADRS(sub->swm->rb.map), in aiodma_rb_set_buffer()
1152 regmap_write(r, CDA2D_RBMXENDADRSU(sub->swm->rb.map), in aiodma_rb_set_buffer()
1155 regmap_write(r, CDA2D_RBADRSLOAD, BIT(sub->swm->rb.map)); in aiodma_rb_set_buffer()
1161 if (sub->swm->dir == PORT_DIR_OUTPUT) { in aiodma_rb_set_buffer()
1165 regmap_update_bits(r, CDA2D_RBMXIE(sub->swm->rb.map), in aiodma_rb_set_buffer()
1172 regmap_update_bits(r, CDA2D_RBMXIE(sub->swm->rb.map), in aiodma_rb_set_buffer()
1191 if (sub->swm->dir == PORT_DIR_OUTPUT) { in aiodma_rb_sync()
1233 regmap_read(r, CDA2D_RBMXIR(sub->swm->rb.map), &ir); in aiodma_rb_is_irq()
1235 if (sub->swm->dir == PORT_DIR_OUTPUT) in aiodma_rb_is_irq()
1245 if (sub->swm->dir == PORT_DIR_OUTPUT) in aiodma_rb_clear_irq()
1246 regmap_write(r, CDA2D_RBMXIR(sub->swm->rb.map), in aiodma_rb_clear_irq()
1249 regmap_write(r, CDA2D_RBMXIR(sub->swm->rb.map), in aiodma_rb_clear_irq()