3 // tegra210_i2s.c - Tegra210 I2S driver
31 	 * is required to select i2s4b for it to be functional for I2S
50 	struct tegra210_i2s *i2s = dev_get_drvdata(dev);  in tegra210_i2s_set_clock_rate()  local
54 	regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &val);  in tegra210_i2s_set_clock_rate()
56 	/* No need to set rates if I2S is being operated in slave */  in tegra210_i2s_set_clock_rate()
60 	err = clk_set_rate(i2s->clk_i2s, clock_rate);  in tegra210_i2s_set_clock_rate()
62 		dev_err(dev, "can't set I2S bit clock rate %u, err: %d\n",  in tegra210_i2s_set_clock_rate()
67 	if (!IS_ERR(i2s->clk_sync_input)) {  in tegra210_i2s_set_clock_rate()
69 		 * Other I/O modules in AHUB can use i2s bclk as reference  in tegra210_i2s_set_clock_rate()
73 		err = clk_set_rate(i2s->clk_sync_input, clock_rate);  in tegra210_i2s_set_clock_rate()
76 				"can't set I2S sync input rate %u, err = %d\n",  in tegra210_i2s_set_clock_rate()
89 	struct tegra210_i2s *i2s = dev_get_drvdata(dev);  in tegra210_i2s_sw_reset()  local
106 	/* Store CIF and I2S control values */  in tegra210_i2s_sw_reset()
107 	regmap_read(i2s->regmap, cif_reg, &cif_ctrl);  in tegra210_i2s_sw_reset()
108 	regmap_read(i2s->regmap, stream_reg, &stream_ctrl);  in tegra210_i2s_sw_reset()
109 	regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &i2s_ctrl);  in tegra210_i2s_sw_reset()
112 	regmap_update_bits(i2s->regmap, reset_reg, reset_mask, reset_en);  in tegra210_i2s_sw_reset()
114 	err = regmap_read_poll_timeout(i2s->regmap, reset_reg, val,  in tegra210_i2s_sw_reset()
118 		dev_err(dev, "timeout: failed to reset I2S for %s\n",  in tegra210_i2s_sw_reset()
123 	/* Restore CIF and I2S control values */  in tegra210_i2s_sw_reset()
124 	regmap_write(i2s->regmap, cif_reg, cif_ctrl);  in tegra210_i2s_sw_reset()
125 	regmap_write(i2s->regmap, stream_reg, stream_ctrl);  in tegra210_i2s_sw_reset()
126 	regmap_write(i2s->regmap, TEGRA210_I2S_CTRL, i2s_ctrl);  in tegra210_i2s_sw_reset()
136 	struct tegra210_i2s *i2s = dev_get_drvdata(dev);  in tegra210_i2s_init()  local
154 	/* Ensure I2S is in disabled state before new session */  in tegra210_i2s_init()
155 	err = regmap_read_poll_timeout(i2s->regmap, status_reg, val,  in tegra210_i2s_init()
159 		dev_err(dev, "timeout: previous I2S %s is still active\n",  in tegra210_i2s_init()
169 	struct tegra210_i2s *i2s = dev_get_drvdata(dev);  in tegra210_i2s_runtime_suspend()  local
171 	regcache_cache_only(i2s->regmap, true);  in tegra210_i2s_runtime_suspend()
172 	regcache_mark_dirty(i2s->regmap);  in tegra210_i2s_runtime_suspend()
174 	clk_disable_unprepare(i2s->clk_i2s);  in tegra210_i2s_runtime_suspend()
181 	struct tegra210_i2s *i2s = dev_get_drvdata(dev);  in tegra210_i2s_runtime_resume()  local
184 	err = clk_prepare_enable(i2s->clk_i2s);  in tegra210_i2s_runtime_resume()
186 		dev_err(dev, "failed to enable I2S bit clock, err: %d\n", err);  in tegra210_i2s_runtime_resume()
190 	regcache_cache_only(i2s->regmap, false);  in tegra210_i2s_runtime_resume()
191 	regcache_sync(i2s->regmap);  in tegra210_i2s_runtime_resume()
196 static void tegra210_i2s_set_data_offset(struct tegra210_i2s *i2s,  in tegra210_i2s_set_data_offset()  argument
200 	regmap_update_bits(i2s->regmap, TEGRA210_I2S_TX_CTRL,  in tegra210_i2s_set_data_offset()
205 	regmap_update_bits(i2s->regmap, TEGRA210_I2S_RX_CTRL,  in tegra210_i2s_set_data_offset()
213 	struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);  in tegra210_i2s_set_fmt()  local
233 		tegra210_i2s_set_data_offset(i2s, 1);  in tegra210_i2s_set_fmt()
238 		tegra210_i2s_set_data_offset(i2s, 0);  in tegra210_i2s_set_fmt()
240 	/* I2S mode has data offset of 1 */  in tegra210_i2s_set_fmt()
244 		tegra210_i2s_set_data_offset(i2s, 1);  in tegra210_i2s_set_fmt()
257 		tegra210_i2s_set_data_offset(i2s, 0);  in tegra210_i2s_set_fmt()
283 	regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL, mask, val);  in tegra210_i2s_set_fmt()
285 	i2s->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;  in tegra210_i2s_set_fmt()
294 	struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);  in tegra210_i2s_set_tdm_slot()  local
297 	i2s->tx_mask = (tx_mask > DEFAULT_I2S_SLOT_MASK) ?  in tegra210_i2s_set_tdm_slot()
299 	i2s->rx_mask = (rx_mask > DEFAULT_I2S_SLOT_MASK) ?  in tegra210_i2s_set_tdm_slot()
309 	struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);  in tegra210_i2s_get_loopback()  local
311 	ucontrol->value.integer.value[0] = i2s->loopback;  in tegra210_i2s_get_loopback()
320 	struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);  in tegra210_i2s_put_loopback()  local
323 	if (value == i2s->loopback)  in tegra210_i2s_put_loopback()
326 	i2s->loopback = value;  in tegra210_i2s_put_loopback()
328 	regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL, I2S_CTRL_LPBK_MASK,  in tegra210_i2s_put_loopback()
329 			   i2s->loopback << I2S_CTRL_LPBK_SHIFT);  in tegra210_i2s_put_loopback()
338 	struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);  in tegra210_i2s_get_fsync_width()  local
340 	ucontrol->value.integer.value[0] = i2s->fsync_width;  in tegra210_i2s_get_fsync_width()
349 	struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);  in tegra210_i2s_put_fsync_width()  local
352 	if (value == i2s->fsync_width)  in tegra210_i2s_put_fsync_width()
355 	i2s->fsync_width = value;  in tegra210_i2s_put_fsync_width()
365 	regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL,  in tegra210_i2s_put_fsync_width()
367 			   i2s->fsync_width << I2S_FSYNC_WIDTH_SHIFT);  in tegra210_i2s_put_fsync_width()
376 	struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);  in tegra210_i2s_cget_stereo_to_mono()  local
378 	ucontrol->value.enumerated.item[0] = i2s->stereo_to_mono[I2S_TX_PATH];  in tegra210_i2s_cget_stereo_to_mono()
387 	struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);  in tegra210_i2s_cput_stereo_to_mono()  local
390 	if (value == i2s->stereo_to_mono[I2S_TX_PATH])  in tegra210_i2s_cput_stereo_to_mono()
393 	i2s->stereo_to_mono[I2S_TX_PATH] = value;  in tegra210_i2s_cput_stereo_to_mono()
402 	struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);  in tegra210_i2s_cget_mono_to_stereo()  local
404 	ucontrol->value.enumerated.item[0] = i2s->mono_to_stereo[I2S_TX_PATH];  in tegra210_i2s_cget_mono_to_stereo()
413 	struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);  in tegra210_i2s_cput_mono_to_stereo()  local
416 	if (value == i2s->mono_to_stereo[I2S_TX_PATH])  in tegra210_i2s_cput_mono_to_stereo()
419 	i2s->mono_to_stereo[I2S_TX_PATH] = value;  in tegra210_i2s_cput_mono_to_stereo()
428 	struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);  in tegra210_i2s_pget_stereo_to_mono()  local
430 	ucontrol->value.enumerated.item[0] = i2s->stereo_to_mono[I2S_RX_PATH];  in tegra210_i2s_pget_stereo_to_mono()
439 	struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);  in tegra210_i2s_pput_stereo_to_mono()  local
442 	if (value == i2s->stereo_to_mono[I2S_RX_PATH])  in tegra210_i2s_pput_stereo_to_mono()
445 	i2s->stereo_to_mono[I2S_RX_PATH] = value;  in tegra210_i2s_pput_stereo_to_mono()
454 	struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);  in tegra210_i2s_pget_mono_to_stereo()  local
456 	ucontrol->value.enumerated.item[0] = i2s->mono_to_stereo[I2S_RX_PATH];  in tegra210_i2s_pget_mono_to_stereo()
465 	struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);  in tegra210_i2s_pput_mono_to_stereo()  local
468 	if (value == i2s->mono_to_stereo[I2S_RX_PATH])  in tegra210_i2s_pput_mono_to_stereo()
471 	i2s->mono_to_stereo[I2S_RX_PATH] = value;  in tegra210_i2s_pput_mono_to_stereo()
480 	struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);  in tegra210_i2s_pget_fifo_th()  local
482 	ucontrol->value.integer.value[0] = i2s->rx_fifo_th;  in tegra210_i2s_pget_fifo_th()
491 	struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);  in tegra210_i2s_pput_fifo_th()  local
494 	if (value == i2s->rx_fifo_th)  in tegra210_i2s_pput_fifo_th()
497 	i2s->rx_fifo_th = value;  in tegra210_i2s_pput_fifo_th()
506 	struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);  in tegra210_i2s_get_bclk_ratio()  local
508 	ucontrol->value.integer.value[0] = i2s->bclk_ratio;  in tegra210_i2s_get_bclk_ratio()
517 	struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);  in tegra210_i2s_put_bclk_ratio()  local
520 	if (value == i2s->bclk_ratio)  in tegra210_i2s_put_bclk_ratio()
523 	i2s->bclk_ratio = value;  in tegra210_i2s_put_bclk_ratio()
531 	struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);  in tegra210_i2s_set_dai_bclk_ratio()  local
533 	i2s->bclk_ratio = ratio;  in tegra210_i2s_set_dai_bclk_ratio()
543 	struct tegra210_i2s *i2s = dev_get_drvdata(dev);  in tegra210_i2s_set_timing_params()  local
547 	if (i2s->bclk_ratio)  in tegra210_i2s_set_timing_params()
548 		num_bclk *= i2s->bclk_ratio;  in tegra210_i2s_set_timing_params()
550 	if (i2s->dai_fmt == SND_SOC_DAIFMT_RIGHT_J)  in tegra210_i2s_set_timing_params()
551 		tegra210_i2s_set_data_offset(i2s, num_bclk - sample_size);  in tegra210_i2s_set_timing_params()
553 	/* I2S bit clock rate */  in tegra210_i2s_set_timing_params()
558 		dev_err(dev, "can't set I2S bit clock rate %u, err: %d\n",  in tegra210_i2s_set_timing_params()
563 	regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &val);  in tegra210_i2s_set_timing_params()
579 		tegra210_i2s_set_slot_ctrl(i2s->regmap, channels,  in tegra210_i2s_set_timing_params()
580 					   i2s->tx_mask, i2s->rx_mask);  in tegra210_i2s_set_timing_params()
583 		dev_err(dev, "invalid I2S frame format\n");  in tegra210_i2s_set_timing_params()
588 		dev_err(dev, "invalid I2S channel bit count %u\n", bit_count);  in tegra210_i2s_set_timing_params()
592 	regmap_write(i2s->regmap, TEGRA210_I2S_TIMING,  in tegra210_i2s_set_timing_params()
603 	struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);  in tegra210_i2s_hw_params()  local
611 		dev_err(dev, "invalid I2S %d channel configuration\n",  in tegra210_i2s_hw_params()
644 	regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL,  in tegra210_i2s_hw_params()
649 	/* For playback I2S RX-CIF and for capture TX-CIF is used */  in tegra210_i2s_hw_params()
661 		if (i2s->rx_fifo_th > max_th)  in tegra210_i2s_hw_params()
662 			i2s->rx_fifo_th = max_th;  in tegra210_i2s_hw_params()
664 		cif_conf.threshold = i2s->rx_fifo_th;  in tegra210_i2s_hw_params()
671 	cif_conf.mono_conv = i2s->mono_to_stereo[path];  in tegra210_i2s_hw_params()
672 	cif_conf.stereo_conv = i2s->stereo_to_mono[path];  in tegra210_i2s_hw_params()
674 	tegra_set_cif(i2s->regmap, reg, &cif_conf);  in tegra210_i2s_hw_params()
689 		.name = "I2S-CIF",
710 		.name = "I2S-DAP",
878 	struct tegra210_i2s *i2s;  in tegra210_i2s_probe()  local
882 	i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);  in tegra210_i2s_probe()
883 	if (!i2s)  in tegra210_i2s_probe()
886 	i2s->rx_fifo_th = DEFAULT_I2S_RX_FIFO_THRESHOLD;  in tegra210_i2s_probe()
887 	i2s->tx_mask = DEFAULT_I2S_SLOT_MASK;  in tegra210_i2s_probe()
888 	i2s->rx_mask = DEFAULT_I2S_SLOT_MASK;  in tegra210_i2s_probe()
889 	i2s->loopback = false;  in tegra210_i2s_probe()
891 	dev_set_drvdata(dev, i2s);  in tegra210_i2s_probe()
893 	i2s->clk_i2s = devm_clk_get(dev, "i2s");  in tegra210_i2s_probe()
894 	if (IS_ERR(i2s->clk_i2s)) {  in tegra210_i2s_probe()
895 		dev_err(dev, "can't retrieve I2S bit clock\n");  in tegra210_i2s_probe()
896 		return PTR_ERR(i2s->clk_i2s);  in tegra210_i2s_probe()
901 	 * requires input clock from current I2S instance, which is  in tegra210_i2s_probe()
904 	i2s->clk_sync_input = devm_clk_get(dev, "sync_input");  in tegra210_i2s_probe()
905 	if (IS_ERR(i2s->clk_sync_input))  in tegra210_i2s_probe()
906 		dev_dbg(dev, "can't retrieve I2S sync input clock\n");  in tegra210_i2s_probe()
912 	i2s->regmap = devm_regmap_init_mmio(dev, regs,  in tegra210_i2s_probe()
914 	if (IS_ERR(i2s->regmap)) {  in tegra210_i2s_probe()
916 		return PTR_ERR(i2s->regmap);  in tegra210_i2s_probe()
919 	regcache_cache_only(i2s->regmap, true);  in tegra210_i2s_probe()
925 		dev_err(dev, "can't register I2S component, err: %d\n", err);  in tegra210_i2s_probe()
947 	{ .compatible = "nvidia,tegra210-i2s" },
954 		.name = "tegra210-i2s",
964 MODULE_DESCRIPTION("Tegra210 ASoC I2S driver");