63 	struct snd_sof_dev *sdev = adata->dev;  in init_dma_descriptor()  local
64 	const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);  in init_dma_descriptor()
67 	addr = desc->sram_pte_offset + sdev->debug_box.offset +  in init_dma_descriptor()
70 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DESC_BASE_ADDR, addr);  in init_dma_descriptor()
71 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DESC_MAX_NUM_DSCR, ACP_MAX_DESC_CNT);  in init_dma_descriptor()
77 	struct snd_sof_dev *sdev = adata->dev;  in configure_dma_descriptor()  local
80 	offset = ACP_SCRATCH_REG_0 + sdev->debug_box.offset +  in configure_dma_descriptor()
84 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset, dscr_info->src_addr);  in configure_dma_descriptor()
85 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x4, dscr_info->dest_addr);  in configure_dma_descriptor()
86 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x8, dscr_info->tx_cnt.u32_all);  in configure_dma_descriptor()
92 	struct snd_sof_dev *sdev = adata->dev;  in config_dma_channel()  local
96 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32),  in config_dma_channel()
99 	ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_DMA_CH_RST_STS, val,  in config_dma_channel()
103 		status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_ERROR_STATUS);  in config_dma_channel()
104 		val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_ERR_STS_0 + ch * sizeof(u32));  in config_dma_channel()
106 		dev_err(sdev->dev, "ACP_DMA_ERR_STS :0x%x ACP_ERROR_STATUS :0x%x\n", val, status);  in config_dma_channel()
110 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, (ACP_DMA_CNTL_0 + ch * sizeof(u32)), 0);  in config_dma_channel()
111 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DSCR_CNT_0 + ch * sizeof(u32), dscr_count);  in config_dma_channel()
112 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DSCR_STRT_IDX_0 + ch * sizeof(u32), idx);  in config_dma_channel()
113 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_PRIO_0 + ch * sizeof(u32), 0);  in config_dma_channel()
114 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32), ACP_DMA_CH_RUN);  in config_dma_channel()
122 	struct snd_sof_dev *sdev = adata->dev;  in acpbus_dma_start()  local
134 		dev_err(sdev->dev, "config dma ch failed:%d\n", ret);  in acpbus_dma_start()
142 	struct snd_sof_dev *sdev = adata->dev;  in configure_and_run_dma()  local
157 		dev_err(sdev->dev, "acpbus_dma_start failed\n");  in configure_and_run_dma()
174 	struct snd_sof_dev *sdev = adata->dev;  in psp_mbox_ready()  local
183 	dev_err(sdev->dev, "PSP error status %x\n", data & MBOX_STATUS_MASK);  in psp_mbox_ready()
199 	struct snd_sof_dev *sdev = adata->dev;  in psp_send_cmd()  local
211 		dev_err(sdev->dev, "Failed to get Doorbell from MBOX %x\n", MP0_C2PMSG_73_REG);  in psp_send_cmd()
235 	struct snd_sof_dev *sdev = adata->dev;  in configure_and_run_sha_dma()  local
236 	const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);  in configure_and_run_sha_dma()
241 		dev_err(sdev->dev, "SHA DMA image address is NULL\n");  in configure_and_run_sha_dma()
245 	val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD);  in configure_and_run_sha_dma()
247 		snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RESET);  in configure_and_run_sha_dma()
248 		ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD_STS,  in configure_and_run_sha_dma()
253 			dev_err(sdev->dev, "SHA DMA Failed to Reset\n");  in configure_and_run_sha_dma()
259 		snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_INCLUDE_HDR, ACP_SHA_HEADER);  in configure_and_run_sha_dma()
261 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_STRT_ADDR, start_addr);  in configure_and_run_sha_dma()
262 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_DESTINATION_ADDR, dest_addr);  in configure_and_run_sha_dma()
263 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_MSG_LENGTH, image_length);  in configure_and_run_sha_dma()
264 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RUN);  in configure_and_run_sha_dma()
266 	ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_TRANSFER_BYTE_CNT,  in configure_and_run_sha_dma()
270 		dev_err(sdev->dev, "SHA DMA Failed to Transfer Length %x\n", tx_count);  in configure_and_run_sha_dma()
281 	ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DSP_FW_QUALIFIER,  in configure_and_run_sha_dma()
285 		dev_err(sdev->dev, "PSP validation failed\n");  in configure_and_run_sha_dma()
294 	struct snd_sof_dev *sdev = adata->dev;  in acp_dma_status()  local
298 	val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32));  in acp_dma_status()
300 		ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_DMA_CH_STS, val, !val,  in acp_dma_status()
304 			dev_err(sdev->dev, "DMA_CHANNEL %d status timeout\n", ch);  in acp_dma_status()
310 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes)  in memcpy_from_scratch()  argument
316 		dst[j] = snd_sof_dsp_read(sdev, ACP_DSP_BAR, reg_offset + i);  in memcpy_from_scratch()
319 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes)  in memcpy_to_scratch()  argument
325 		snd_sof_dsp_write(sdev, ACP_DSP_BAR, reg_offset + i, src[j]);  in memcpy_to_scratch()
328 static int acp_memory_init(struct snd_sof_dev *sdev)  in acp_memory_init()  argument
330 	struct acp_dev_data *adata = sdev->pdata->hw_pdata;  in acp_memory_init()
331 	const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);  in acp_memory_init()
333 	snd_sof_dsp_update_bits(sdev, ACP_DSP_BAR, desc->dsp_intr_base + DSP_SW_INTR_CNTL_OFFSET,  in acp_memory_init()
342 	struct snd_sof_dev *sdev = context;  in acp_irq_thread()  local
343 	const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);  in acp_irq_thread()
346 	while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset)) {  in acp_irq_thread()
350 			dev_err(sdev->dev, "%s: Failed to acquire HW lock\n", __func__);  in acp_irq_thread()
355 	sof_ops(sdev)->irq_thread(irq, sdev);  in acp_irq_thread()
357 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset, 0x0);  in acp_irq_thread()
364 	struct snd_sof_dev *sdev = dev_id;  in acp_irq_handler()  local
365 	const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);  in acp_irq_handler()
369 	val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET);  in acp_irq_handler()
371 		snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET,  in acp_irq_handler()
379 static int acp_power_on(struct snd_sof_dev *sdev)  in acp_power_on()  argument
381 	const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);  in acp_power_on()
386 	val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET);  in acp_power_on()
392 		snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + PGFSM_CONTROL_OFFSET,  in acp_power_on()
395 	ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET, val,  in acp_power_on()
398 		dev_err(sdev->dev, "timeout in ACP_PGFSM_STATUS read\n");  in acp_power_on()
403 static int acp_reset(struct snd_sof_dev *sdev)  in acp_reset()  argument
405 	const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);  in acp_reset()
409 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_ASSERT_RESET);  in acp_reset()
411 	ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val,  in acp_reset()
415 		dev_err(sdev->dev, "timeout asserting reset\n");  in acp_reset()
419 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_RELEASE_RESET);  in acp_reset()
421 	ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val,  in acp_reset()
424 		dev_err(sdev->dev, "timeout in releasing reset\n");  in acp_reset()
427 		snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACLK);  in acp_reset()
430 		snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_enb, 0x01);  in acp_reset()
435 static int acp_init(struct snd_sof_dev *sdev)  in acp_init()  argument
440 	ret = acp_power_on(sdev);  in acp_init()
442 		dev_err(sdev->dev, "ACP power on failed\n");  in acp_init()
446 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x01);  in acp_init()
448 	return acp_reset(sdev);  in acp_init()
451 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state)  in amd_sof_acp_suspend()  argument
455 	ret = acp_reset(sdev);  in amd_sof_acp_suspend()
457 		dev_err(sdev->dev, "ACP Reset failed\n");  in amd_sof_acp_suspend()
461 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x00);  in amd_sof_acp_suspend()
467 int amd_sof_acp_resume(struct snd_sof_dev *sdev)  in amd_sof_acp_resume()  argument
471 	ret = acp_init(sdev);  in amd_sof_acp_resume()
473 		dev_err(sdev->dev, "ACP Init failed\n");  in amd_sof_acp_resume()
476 	return acp_memory_init(sdev);  in amd_sof_acp_resume()
480 int amd_sof_acp_probe(struct snd_sof_dev *sdev)  in amd_sof_acp_probe()  argument
482 	struct pci_dev *pci = to_pci_dev(sdev->dev);  in amd_sof_acp_probe()
483 	struct snd_sof_pdata *plat_data = sdev->pdata;  in amd_sof_acp_probe()
490 	chip = get_chip_info(sdev->pdata);  in amd_sof_acp_probe()
492 		dev_err(sdev->dev, "no such device supported, chip id:%x\n", pci->device);  in amd_sof_acp_probe()
495 	adata = devm_kzalloc(sdev->dev, sizeof(struct acp_dev_data),  in amd_sof_acp_probe()
500 	adata->dev = sdev;  in amd_sof_acp_probe()
501 	adata->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec",  in amd_sof_acp_probe()
504 		dev_err(sdev->dev, "failed to register platform for dmic codec\n");  in amd_sof_acp_probe()
508 	sdev->bar[ACP_DSP_BAR] = devm_ioremap(sdev->dev, addr, pci_resource_len(pci, ACP_DSP_BAR));  in amd_sof_acp_probe()
509 	if (!sdev->bar[ACP_DSP_BAR]) {  in amd_sof_acp_probe()
510 		dev_err(sdev->dev, "ioremap error\n");  in amd_sof_acp_probe()
517 	sdev->pdata->hw_pdata = adata;  in amd_sof_acp_probe()
520 		dev_err(sdev->dev, "Failed to get host bridge device\n");  in amd_sof_acp_probe()
525 	sdev->ipc_irq = pci->irq;  in amd_sof_acp_probe()
526 	ret = request_threaded_irq(sdev->ipc_irq, acp_irq_handler, acp_irq_thread,  in amd_sof_acp_probe()
527 				   IRQF_SHARED, "AudioDSP", sdev);  in amd_sof_acp_probe()
529 		dev_err(sdev->dev, "failed to register IRQ %d\n",  in amd_sof_acp_probe()
530 			sdev->ipc_irq);  in amd_sof_acp_probe()
534 	ret = acp_init(sdev);  in amd_sof_acp_probe()
538 	sdev->dsp_box.offset = 0;  in amd_sof_acp_probe()
539 	sdev->dsp_box.size = BOX_SIZE_512;  in amd_sof_acp_probe()
541 	sdev->host_box.offset = sdev->dsp_box.offset + sdev->dsp_box.size;  in amd_sof_acp_probe()
542 	sdev->host_box.size = BOX_SIZE_512;  in amd_sof_acp_probe()
544 	sdev->debug_box.offset = sdev->host_box.offset + sdev->host_box.size;  in amd_sof_acp_probe()
545 	sdev->debug_box.size = BOX_SIZE_1024;  in amd_sof_acp_probe()
558 		dev_dbg(sdev->dev, "fw_code_bin:%s, fw_data_bin:%s\n", adata->fw_code_bin,  in amd_sof_acp_probe()
562 	acp_memory_init(sdev);  in amd_sof_acp_probe()
564 	acp_dsp_stream_init(sdev);  in amd_sof_acp_probe()
569 	free_irq(sdev->ipc_irq, sdev);  in amd_sof_acp_probe()
578 int amd_sof_acp_remove(struct snd_sof_dev *sdev)  in amd_sof_acp_remove()  argument
580 	struct acp_dev_data *adata = sdev->pdata->hw_pdata;  in amd_sof_acp_remove()
585 	if (sdev->ipc_irq)  in amd_sof_acp_remove()
586 		free_irq(sdev->ipc_irq, sdev);  in amd_sof_acp_remove()
591 	return acp_reset(sdev);  in amd_sof_acp_remove()