Lines Matching refs:clk_prepare_enable
86 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]); in apll1_mux_setting()
102 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]); in apll1_mux_setting()
148 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]); in apll2_mux_setting()
164 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]); in apll2_mux_setting()
209 ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUDIO]); in mt8192_afe_enable_clock()
216 ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_AUDIO_26M]); in mt8192_afe_enable_clock()
223 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIO]); in mt8192_afe_enable_clock()
238 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]); in mt8192_afe_enable_clock()
262 ret = clk_prepare_enable(afe_priv->clk[CLK_AFE]); in mt8192_afe_enable_clock()
293 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL22M]); in mt8192_apll1_enable()
300 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL1_TUNER]); in mt8192_apll1_enable()
343 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL24M]); in mt8192_apll2_enable()
350 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL2_TUNER]); in mt8192_apll2_enable()
574 ret = clk_prepare_enable(afe_priv->clk[m_sel_id]); in mt8192_mck_enable()
591 ret = clk_prepare_enable(afe_priv->clk[div_clk_id]); in mt8192_mck_enable()