Lines Matching full:x1
418 #define BCK_INVERSE_MASK 0x1
419 #define BCK_INVERSE_MASK_SFT (0x1 << 3)
423 #define AWB2_ON_MASK 0x1
424 #define AWB2_ON_MASK_SFT (0x1 << 29)
426 #define VUL2_ON_MASK 0x1
427 #define VUL2_ON_MASK_SFT (0x1 << 27)
429 #define MOD_DAI_DUP_WR_MASK 0x1
430 #define MOD_DAI_DUP_WR_MASK_SFT (0x1 << 26)
435 #define VUL12_R_MONO_MASK 0x1
436 #define VUL12_R_MONO_MASK_SFT (0x1 << 11)
438 #define VUL12_MONO_MASK 0x1
439 #define VUL12_MONO_MASK_SFT (0x1 << 10)
441 #define VUL12_ON_MASK 0x1
442 #define VUL12_ON_MASK_SFT (0x1 << 9)
444 #define MOD_DAI_ON_MASK 0x1
445 #define MOD_DAI_ON_MASK_SFT (0x1 << 7)
447 #define AWB_ON_MASK 0x1
448 #define AWB_ON_MASK_SFT (0x1 << 6)
450 #define DL3_ON_MASK 0x1
451 #define DL3_ON_MASK_SFT (0x1 << 5)
453 #define VUL_ON_MASK 0x1
454 #define VUL_ON_MASK_SFT (0x1 << 3)
456 #define DL2_ON_MASK 0x1
457 #define DL2_ON_MASK_SFT (0x1 << 2)
459 #define DL1_ON_MASK 0x1
460 #define DL1_ON_MASK_SFT (0x1 << 1)
462 #define AFE_ON_MASK 0x1
463 #define AFE_ON_MASK_SFT (0x1 << 0)
470 #define VUL_R_MONO_MASK 0x1
471 #define VUL_R_MONO_MASK_SFT (0x1 << 28)
473 #define VUL_DATA_MASK 0x1
474 #define VUL_DATA_MASK_SFT (0x1 << 27)
476 #define AWB_R_MONO_MASK 0x1
477 #define AWB_R_MONO_MASK_SFT (0x1 << 25)
479 #define AWB_DATA_MASK 0x1
480 #define AWB_DATA_MASK_SFT (0x1 << 24)
482 #define DL3_DATA_MASK 0x1
483 #define DL3_DATA_MASK_SFT (0x1 << 23)
485 #define DL2_DATA_MASK 0x1
486 #define DL2_DATA_MASK_SFT (0x1 << 22)
488 #define DL1_DATA_MASK 0x1
489 #define DL1_DATA_MASK_SFT (0x1 << 21)
508 #define AWB2_R_MONO_MASK 0x1
509 #define AWB2_R_MONO_MASK_SFT (0x1 << 21)
511 #define AWB2_DATA_MASK 0x1
512 #define AWB2_DATA_MASK_SFT (0x1 << 20)
523 #define VUL2_R_MONO_MASK 0x1
524 #define VUL2_R_MONO_MASK_SFT (0x1 << 1)
526 #define VUL2_DATA_MASK 0x1
527 #define VUL2_DATA_MASK_SFT (0x1 << 0)
531 #define AFE_ON_RETM_MASK 0x1
532 #define AFE_ON_RETM_MASK_SFT (0x1 << 0)
536 #define BCK_NEG_EG_LATCH_MASK 0x1
537 #define BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 30)
539 #define BCK_INV_MASK 0x1
540 #define BCK_INV_MASK_SFT (0x1 << 29)
542 #define I2SIN_PAD_SEL_MASK 0x1
543 #define I2SIN_PAD_SEL_MASK_SFT (0x1 << 28)
545 #define I2S_LOOPBACK_MASK 0x1
546 #define I2S_LOOPBACK_MASK_SFT (0x1 << 20)
548 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
549 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
551 #define I2S1_HD_EN_MASK 0x1
552 #define I2S1_HD_EN_MASK_SFT (0x1 << 12)
554 #define INV_PAD_CTRL_MASK 0x1
555 #define INV_PAD_CTRL_MASK_SFT (0x1 << 7)
557 #define I2S_BYPSRC_MASK 0x1
558 #define I2S_BYPSRC_MASK_SFT (0x1 << 6)
560 #define INV_LRCK_MASK 0x1
561 #define INV_LRCK_MASK_SFT (0x1 << 5)
563 #define I2S_FMT_MASK 0x1
564 #define I2S_FMT_MASK_SFT (0x1 << 3)
566 #define I2S_SRC_MASK 0x1
567 #define I2S_SRC_MASK_SFT (0x1 << 2)
569 #define I2S_WLEN_MASK 0x1
570 #define I2S_WLEN_MASK_SFT (0x1 << 1)
572 #define I2S_EN_MASK 0x1
573 #define I2S_EN_MASK_SFT (0x1 << 0)
577 #define I2S2_LR_SWAP_MASK 0x1
578 #define I2S2_LR_SWAP_MASK_SFT (0x1 << 31)
580 #define I2S2_SEL_O19_O20_MASK 0x1
581 #define I2S2_SEL_O19_O20_MASK_SFT (0x1 << 18)
583 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
584 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
586 #define I2S2_SEL_O03_O04_MASK 0x1
587 #define I2S2_SEL_O03_O04_MASK_SFT (0x1 << 16)
589 #define I2S2_32BIT_EN_MASK 0x1
590 #define I2S2_32BIT_EN_MASK_SFT (0x1 << 13)
592 #define I2S2_HD_EN_MASK 0x1
593 #define I2S2_HD_EN_MASK_SFT (0x1 << 12)
598 #define INV_LRCK_MASK 0x1
599 #define INV_LRCK_MASK_SFT (0x1 << 5)
601 #define I2S2_FMT_MASK 0x1
602 #define I2S2_FMT_MASK_SFT (0x1 << 3)
604 #define I2S2_WLEN_MASK 0x1
605 #define I2S2_WLEN_MASK_SFT (0x1 << 1)
607 #define I2S2_EN_MASK 0x1
608 #define I2S2_EN_MASK_SFT (0x1 << 0)
612 #define I2S3_LR_SWAP_MASK 0x1
613 #define I2S3_LR_SWAP_MASK_SFT (0x1 << 31)
618 #define I2S3_BCK_INV_MASK 0x1
619 #define I2S3_BCK_INV_MASK_SFT (0x1 << 23)
621 #define I2S3_FPGA_BIT_TEST_MASK 0x1
622 #define I2S3_FPGA_BIT_TEST_MASK_SFT (0x1 << 22)
624 #define I2S3_FPGA_BIT_MASK 0x1
625 #define I2S3_FPGA_BIT_MASK_SFT (0x1 << 21)
627 #define I2S3_LOOPBACK_MASK 0x1
628 #define I2S3_LOOPBACK_MASK_SFT (0x1 << 20)
630 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
631 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
633 #define I2S3_HD_EN_MASK 0x1
634 #define I2S3_HD_EN_MASK_SFT (0x1 << 12)
639 #define I2S3_FMT_MASK 0x1
640 #define I2S3_FMT_MASK_SFT (0x1 << 3)
642 #define I2S3_WLEN_MASK 0x1
643 #define I2S3_WLEN_MASK_SFT (0x1 << 1)
645 #define I2S3_EN_MASK 0x1
646 #define I2S3_EN_MASK_SFT (0x1 << 0)
650 #define I2S4_LR_SWAP_MASK 0x1
651 #define I2S4_LR_SWAP_MASK_SFT (0x1 << 31)
653 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
654 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
656 #define I2S4_32BIT_EN_MASK 0x1
657 #define I2S4_32BIT_EN_MASK_SFT (0x1 << 13)
659 #define I2S4_HD_EN_MASK 0x1
660 #define I2S4_HD_EN_MASK_SFT (0x1 << 12)
665 #define INV_LRCK_MASK 0x1
666 #define INV_LRCK_MASK_SFT (0x1 << 5)
668 #define I2S4_FMT_MASK 0x1
669 #define I2S4_FMT_MASK_SFT (0x1 << 3)
671 #define I2S4_WLEN_MASK 0x1
672 #define I2S4_WLEN_MASK_SFT (0x1 << 1)
674 #define I2S4_EN_MASK 0x1
675 #define I2S4_EN_MASK_SFT (0x1 << 0)
679 #define I2S5_LR_SWAP_MASK 0x1
680 #define I2S5_LR_SWAP_MASK_SFT (0x1 << 31)
682 #define I2S_LOOPBACK_MASK 0x1
683 #define I2S_LOOPBACK_MASK_SFT (0x1 << 20)
685 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
686 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
688 #define I2S5_32BIT_EN_MASK 0x1
689 #define I2S5_32BIT_EN_MASK_SFT (0x1 << 13)
691 #define I2S5_HD_EN_MASK 0x1
692 #define I2S5_HD_EN_MASK_SFT (0x1 << 12)
697 #define INV_LRCK_MASK 0x1
698 #define INV_LRCK_MASK_SFT (0x1 << 5)
700 #define I2S5_FMT_MASK 0x1
701 #define I2S5_FMT_MASK_SFT (0x1 << 3)
703 #define I2S5_WLEN_MASK 0x1
704 #define I2S5_WLEN_MASK_SFT (0x1 << 1)
706 #define I2S5_EN_MASK 0x1
707 #define I2S5_EN_MASK_SFT (0x1 << 0)
717 #define GAIN1_ON_MASK 0x1
718 #define GAIN1_ON_MASK_SFT (0x1 << 0)
733 #define GAIN2_ON_MASK 0x1
734 #define GAIN2_ON_MASK_SFT (0x1 << 0)
788 #define AWB2_NORMAL_MODE_MASK 0x1
789 #define AWB2_NORMAL_MODE_MASK_SFT (0x1 << 30)
791 #define HDMI_NORMAL_MODE_MASK 0x1
792 #define HDMI_NORMAL_MODE_MASK_SFT (0x1 << 26)
794 #define MOD_DAI_NORMAL_MODE_MASK 0x1
795 #define MOD_DAI_NORMAL_MODE_MASK_SFT (0x1 << 25)
797 #define DAI_NORMAL_MODE_MASK 0x1
798 #define DAI_NORMAL_MODE_MASK_SFT (0x1 << 24)
800 #define VUL2_NORMAL_MODE_MASK 0x1
801 #define VUL2_NORMAL_MODE_MASK_SFT (0x1 << 23)
803 #define VUL12_NORMAL_MODE_MASK 0x1
804 #define VUL12_NORMAL_MODE_MASK_SFT (0x1 << 22)
806 #define VUL_NORMAL_MODE_MASK 0x1
807 #define VUL_NORMAL_MODE_MASK_SFT (0x1 << 21)
809 #define AWB_NORMAL_MODE_MASK 0x1
810 #define AWB_NORMAL_MODE_MASK_SFT (0x1 << 20)
812 #define DL3_NORMAL_MODE_MASK 0x1
813 #define DL3_NORMAL_MODE_MASK_SFT (0x1 << 19)
815 #define DL2_NORMAL_MODE_MASK 0x1
816 #define DL2_NORMAL_MODE_MASK_SFT (0x1 << 18)
818 #define DL1_NORMAL_MODE_MASK 0x1
819 #define DL1_NORMAL_MODE_MASK_SFT (0x1 << 16)
821 #define RESERVED1_MASK 0x1
822 #define RESERVED1_MASK_SFT (0x1 << 15)
824 #define AWB2_ALIGN_MASK 0x1
825 #define AWB2_ALIGN_MASK_SFT (0x1 << 14)
827 #define HDMI_HD_ALIGN_MASK 0x1
828 #define HDMI_HD_ALIGN_MASK_SFT (0x1 << 10)
830 #define MOD_DAI_HD_ALIGN_MASK 0x1
831 #define MOD_DAI_HD_ALIGN_MASK_SFT (0x1 << 9)
833 #define VUL2_HD_ALIGN_MASK 0x1
834 #define VUL2_HD_ALIGN_MASK_SFT (0x1 << 7)
836 #define VUL12_HD_ALIGN_MASK 0x1
837 #define VUL12_HD_ALIGN_MASK_SFT (0x1 << 6)
839 #define VUL_HD_ALIGN_MASK 0x1
840 #define VUL_HD_ALIGN_MASK_SFT (0x1 << 5)
842 #define AWB_HD_ALIGN_MASK 0x1
843 #define AWB_HD_ALIGN_MASK_SFT (0x1 << 4)
845 #define DL3_HD_ALIGN_MASK 0x1
846 #define DL3_HD_ALIGN_MASK_SFT (0x1 << 3)
848 #define DL2_HD_ALIGN_MASK 0x1
849 #define DL2_HD_ALIGN_MASK_SFT (0x1 << 2)
851 #define DL1_HD_ALIGN_MASK 0x1
852 #define DL1_HD_ALIGN_MASK_SFT (0x1 << 0)
856 #define PCM_FIX_VALUE_SEL_MASK 0x1
857 #define PCM_FIX_VALUE_SEL_MASK_SFT (0x1 << 31)
859 #define PCM_BUFFER_LOOPBACK_MASK 0x1
860 #define PCM_BUFFER_LOOPBACK_MASK_SFT (0x1 << 30)
862 #define PCM_PARALLEL_LOOPBACK_MASK 0x1
863 #define PCM_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 29)
865 #define PCM_SERIAL_LOOPBACK_MASK 0x1
866 #define PCM_SERIAL_LOOPBACK_MASK_SFT (0x1 << 28)
868 #define PCM_DAI_PCM_LOOPBACK_MASK 0x1
869 #define PCM_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 27)
871 #define PCM_I2S_PCM_LOOPBACK_MASK 0x1
872 #define PCM_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 26)
874 #define PCM_SYNC_DELSEL_MASK 0x1
875 #define PCM_SYNC_DELSEL_MASK_SFT (0x1 << 25)
877 #define PCM_TX_LR_SWAP_MASK 0x1
878 #define PCM_TX_LR_SWAP_MASK_SFT (0x1 << 24)
880 #define PCM_SYNC_OUT_INV_MASK 0x1
881 #define PCM_SYNC_OUT_INV_MASK_SFT (0x1 << 23)
883 #define PCM_BCLK_OUT_INV_MASK 0x1
884 #define PCM_BCLK_OUT_INV_MASK_SFT (0x1 << 22)
886 #define PCM_SYNC_IN_INV_MASK 0x1
887 #define PCM_SYNC_IN_INV_MASK_SFT (0x1 << 21)
889 #define PCM_BCLK_IN_INV_MASK 0x1
890 #define PCM_BCLK_IN_INV_MASK_SFT (0x1 << 20)
892 #define PCM_TX_LCH_RPT_MASK 0x1
893 #define PCM_TX_LCH_RPT_MASK_SFT (0x1 << 19)
895 #define PCM_VBT_16K_MODE_MASK 0x1
896 #define PCM_VBT_16K_MODE_MASK_SFT (0x1 << 18)
898 #define PCM_EXT_MODEM_MASK 0x1
899 #define PCM_EXT_MODEM_MASK_SFT (0x1 << 17)
901 #define PCM_24BIT_MASK 0x1
902 #define PCM_24BIT_MASK_SFT (0x1 << 16)
910 #define PCM_SYNC_TYPE_MASK 0x1
911 #define PCM_SYNC_TYPE_MASK_SFT (0x1 << 8)
913 #define PCM_BT_MODE_MASK 0x1
914 #define PCM_BT_MODE_MASK_SFT (0x1 << 7)
916 #define PCM_BYP_ASRC_MASK 0x1
917 #define PCM_BYP_ASRC_MASK_SFT (0x1 << 6)
919 #define PCM_SLAVE_MASK 0x1
920 #define PCM_SLAVE_MASK_SFT (0x1 << 5)
928 #define PCM_EN_MASK 0x1
929 #define PCM_EN_MASK_SFT (0x1 << 0)
933 #define PCM1_TX_FIFO_OV_MASK 0x1
934 #define PCM1_TX_FIFO_OV_MASK_SFT (0x1 << 31)
936 #define PCM1_RX_FIFO_OV_MASK 0x1
937 #define PCM1_RX_FIFO_OV_MASK_SFT (0x1 << 30)
939 #define PCM2_TX_FIFO_OV_MASK 0x1
940 #define PCM2_TX_FIFO_OV_MASK_SFT (0x1 << 29)
942 #define PCM2_RX_FIFO_OV_MASK 0x1
943 #define PCM2_RX_FIFO_OV_MASK_SFT (0x1 << 28)
945 #define PCM1_SYNC_GLITCH_MASK 0x1
946 #define PCM1_SYNC_GLITCH_MASK_SFT (0x1 << 27)
948 #define PCM2_SYNC_GLITCH_MASK 0x1
949 #define PCM2_SYNC_GLITCH_MASK_SFT (0x1 << 26)
951 #define TX3_RCH_DBG_MODE_MASK 0x1
952 #define TX3_RCH_DBG_MODE_MASK_SFT (0x1 << 17)
954 #define PCM1_PCM2_LOOPBACK_MASK 0x1
955 #define PCM1_PCM2_LOOPBACK_MASK_SFT (0x1 << 16)
971 #define PCM2_FIX_VALUE_SEL_MASK 0x1
972 #define PCM2_FIX_VALUE_SEL_MASK_SFT (0x1 << 23)
974 #define PCM2_BUFFER_LOOPBACK_MASK 0x1
975 #define PCM2_BUFFER_LOOPBACK_MASK_SFT (0x1 << 22)
977 #define PCM2_PARALLEL_LOOPBACK_MASK 0x1
978 #define PCM2_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 21)
980 #define PCM2_SERIAL_LOOPBACK_MASK 0x1
981 #define PCM2_SERIAL_LOOPBACK_MASK_SFT (0x1 << 20)
983 #define PCM2_DAI_PCM_LOOPBACK_MASK 0x1
984 #define PCM2_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 19)
986 #define PCM2_I2S_PCM_LOOPBACK_MASK 0x1
987 #define PCM2_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 18)
989 #define PCM2_SYNC_DELSEL_MASK 0x1
990 #define PCM2_SYNC_DELSEL_MASK_SFT (0x1 << 17)
992 #define PCM2_TX_LR_SWAP_MASK 0x1
993 #define PCM2_TX_LR_SWAP_MASK_SFT (0x1 << 16)
995 #define PCM2_SYNC_IN_INV_MASK 0x1
996 #define PCM2_SYNC_IN_INV_MASK_SFT (0x1 << 15)
998 #define PCM2_BCLK_IN_INV_MASK 0x1
999 #define PCM2_BCLK_IN_INV_MASK_SFT (0x1 << 14)
1001 #define PCM2_TX_LCH_RPT_MASK 0x1
1002 #define PCM2_TX_LCH_RPT_MASK_SFT (0x1 << 13)
1004 #define PCM2_VBT_16K_MODE_MASK 0x1
1005 #define PCM2_VBT_16K_MODE_MASK_SFT (0x1 << 12)
1010 #define PCM2_TX2_BT_MODE_MASK 0x1
1011 #define PCM2_TX2_BT_MODE_MASK_SFT (0x1 << 8)
1013 #define PCM2_BT_MODE_MASK 0x1
1014 #define PCM2_BT_MODE_MASK_SFT (0x1 << 7)
1016 #define PCM2_AFIFO_MASK 0x1
1017 #define PCM2_AFIFO_MASK_SFT (0x1 << 6)
1019 #define PCM2_WLEN_MASK 0x1
1020 #define PCM2_WLEN_MASK_SFT (0x1 << 5)
1028 #define PCM2_EN_MASK 0x1
1029 #define PCM2_EN_MASK_SFT (0x1 << 0)
1033 #define MTKAIF_RXIF_CLKINV_ADC_MASK 0x1
1034 #define MTKAIF_RXIF_CLKINV_ADC_MASK_SFT (0x1 << 31)
1036 #define MTKAIF_RXIF_BYPASS_SRC_MASK 0x1
1037 #define MTKAIF_RXIF_BYPASS_SRC_MASK_SFT (0x1 << 17)
1039 #define MTKAIF_RXIF_PROTOCOL2_MASK 0x1
1040 #define MTKAIF_RXIF_PROTOCOL2_MASK_SFT (0x1 << 16)
1042 #define MTKAIF_TXIF_BYPASS_SRC_MASK 0x1
1043 #define MTKAIF_TXIF_BYPASS_SRC_MASK_SFT (0x1 << 5)
1045 #define MTKAIF_TXIF_PROTOCOL2_MASK 0x1
1046 #define MTKAIF_TXIF_PROTOCOL2_MASK_SFT (0x1 << 4)
1048 #define MTKAIF_TXIF_8TO5_MASK 0x1
1049 #define MTKAIF_TXIF_8TO5_MASK_SFT (0x1 << 2)
1051 #define MTKAIF_RXIF_8TO5_MASK 0x1
1052 #define MTKAIF_RXIF_8TO5_MASK_SFT (0x1 << 1)
1054 #define MTKAIF_IF_LOOPBACK1_MASK 0x1
1055 #define MTKAIF_IF_LOOPBACK1_MASK_SFT (0x1 << 0)
1059 #define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK 0x1
1060 #define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT (0x1 << 16)
1065 #define MTKAIF_RXIF_DELAY_DATA_MASK 0x1
1066 #define MTKAIF_RXIF_DELAY_DATA_MASK_SFT (0x1 << 8)
1076 #define DL_2_CH1_SATURATION_EN_CTL_MASK 0x1
1077 #define DL_2_CH1_SATURATION_EN_CTL_MASK_SFT (0x1 << 27)
1079 #define DL_2_CH2_SATURATION_EN_CTL_MASK 0x1
1080 #define DL_2_CH2_SATURATION_EN_CTL_MASK_SFT (0x1 << 26)
1088 #define DL_DISABLE_HW_CG_CTL_MASK 0x1
1089 #define DL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 15)
1091 #define C_DATA_EN_SEL_CTL_PRE_MASK 0x1
1092 #define C_DATA_EN_SEL_CTL_PRE_MASK_SFT (0x1 << 14)
1094 #define DL_2_SIDE_TONE_ON_CTL_PRE_MASK 0x1
1095 #define DL_2_SIDE_TONE_ON_CTL_PRE_MASK_SFT (0x1 << 13)
1097 #define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK 0x1
1098 #define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK_SFT (0x1 << 12)
1100 #define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK 0x1
1101 #define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK_SFT (0x1 << 11)
1109 #define DL_2_VOICE_MODE_CTL_PRE_MASK 0x1
1110 #define DL_2_VOICE_MODE_CTL_PRE_MASK_SFT (0x1 << 5)
1112 #define D2_2_MUTE_CH1_ON_CTL_PRE_MASK 0x1
1113 #define D2_2_MUTE_CH1_ON_CTL_PRE_MASK_SFT (0x1 << 4)
1115 #define D2_2_MUTE_CH2_ON_CTL_PRE_MASK 0x1
1116 #define D2_2_MUTE_CH2_ON_CTL_PRE_MASK_SFT (0x1 << 3)
1118 #define DL_2_IIR_ON_CTL_PRE_MASK 0x1
1119 #define DL_2_IIR_ON_CTL_PRE_MASK_SFT (0x1 << 2)
1121 #define DL_2_GAIN_ON_CTL_PRE_MASK 0x1
1122 #define DL_2_GAIN_ON_CTL_PRE_MASK_SFT (0x1 << 1)
1124 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK 0x1
1125 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0)
1132 #define DL_2_GAIN_MODE_CTL_MASK 0x1
1133 #define DL_2_GAIN_MODE_CTL_MASK_SFT (0x1 << 0)
1137 #define ULCF_CFG_EN_CTL_MASK 0x1
1138 #define ULCF_CFG_EN_CTL_MASK_SFT (0x1 << 31)
1140 #define UL_MODE_3P25M_CH2_CTL_MASK 0x1
1141 #define UL_MODE_3P25M_CH2_CTL_MASK_SFT (0x1 << 22)
1143 #define UL_MODE_3P25M_CH1_CTL_MASK 0x1
1144 #define UL_MODE_3P25M_CH1_CTL_MASK_SFT (0x1 << 21)
1152 #define UL_DISABLE_HW_CG_CTL_MASK 0x1
1153 #define UL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 12)
1155 #define UL_IIR_ON_TMP_CTL_MASK 0x1
1156 #define UL_IIR_ON_TMP_CTL_MASK_SFT (0x1 << 10)
1161 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1
1162 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)
1164 #define UL_LOOP_BACK_MODE_CTL_MASK 0x1
1165 #define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)
1167 #define UL_SDM_3_LEVEL_CTL_MASK 0x1
1168 #define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)
1170 #define UL_SRC_ON_TMP_CTL_MASK 0x1
1171 #define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)
1175 #define C_DAC_EN_CTL_MASK 0x1
1176 #define C_DAC_EN_CTL_MASK_SFT (0x1 << 27)
1178 #define C_MUTE_SW_CTL_MASK 0x1
1179 #define C_MUTE_SW_CTL_MASK_SFT (0x1 << 26)
1181 #define ASDM_SRC_SEL_CTL_MASK 0x1
1182 #define ASDM_SRC_SEL_CTL_MASK_SFT (0x1 << 25)
1207 #define C_EXT_ADC_CTL_MASK 0x1
1208 #define C_EXT_ADC_CTL_MASK_SFT (0x1 << 0)
1212 #define AFE_ADDA6_UL_LR_SWAP_MASK 0x1
1213 #define AFE_ADDA6_UL_LR_SWAP_MASK_SFT (0x1 << 15)
1215 #define AFE_ADDA6_CKDIV_RST_MASK 0x1
1216 #define AFE_ADDA6_CKDIV_RST_MASK_SFT (0x1 << 14)
1218 #define AFE_ADDA6_FIFO_AUTO_RST_MASK 0x1
1219 #define AFE_ADDA6_FIFO_AUTO_RST_MASK_SFT (0x1 << 13)
1224 #define UL_FIFO_DIGMIC_WDATA_TESTEN_MASK 0x1
1225 #define UL_FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT (0x1 << 4)
1227 #define ADDA_AFE_ON_MASK 0x1
1228 #define ADDA_AFE_ON_MASK_SFT (0x1 << 0)
1232 #define R_RDY_MASK 0x1
1233 #define R_RDY_MASK_SFT (0x1 << 30)
1235 #define W_RDY_MASK 0x1
1236 #define W_RDY_MASK_SFT (0x1 << 29)
1238 #define R_W_EN_MASK 0x1
1239 #define R_W_EN_MASK_SFT (0x1 << 25)
1241 #define R_W_SEL_MASK 0x1
1242 #define R_W_SEL_MASK_SFT (0x1 << 24)
1244 #define SEL_CH2_MASK 0x1
1245 #define SEL_CH2_MASK_SFT (0x1 << 23)
1260 #define STF_BYPASS_MODE_MASK 0x1
1261 #define STF_BYPASS_MODE_MASK_SFT (0x1 << 31)
1263 #define STF_BYPASS_MODE_O28_O29_MASK 0x1
1264 #define STF_BYPASS_MODE_O28_O29_MASK_SFT (0x1 << 30)
1266 #define STF_BYPASS_MODE_I2S4_MASK 0x1
1267 #define STF_BYPASS_MODE_I2S4_MASK_SFT (0x1 << 29)
1269 #define STF_BYPASS_MODE_I2S5_MASK 0x1
1270 #define STF_BYPASS_MODE_I2S5_MASK_SFT (0x1 << 28)
1272 #define STF_INPUT_EN_SEL_MASK 0x1
1273 #define STF_INPUT_EN_SEL_MASK_SFT (0x1 << 13)
1275 #define STF_SOURCE_FROM_O19O20_MASK 0x1
1276 #define STF_SOURCE_FROM_O19O20_MASK_SFT (0x1 << 12)
1278 #define SIDE_TONE_ON_MASK 0x1
1279 #define SIDE_TONE_ON_MASK_SFT (0x1 << 8)
1294 #define AUD_DC_COMP_EN_MASK 0x1
1295 #define AUD_DC_COMP_EN_MASK_SFT (0x1 << 8)
1302 #define DAC_EN_MASK 0x1
1303 #define DAC_EN_MASK_SFT (0x1 << 26)
1305 #define MUTE_SW_CH2_MASK 0x1
1306 #define MUTE_SW_CH2_MASK_SFT (0x1 << 25)
1308 #define MUTE_SW_CH1_MASK 0x1
1309 #define MUTE_SW_CH1_MASK_SFT (0x1 << 24)
1367 #define VUL12_4CH_MASK 0x1
1368 #define VUL12_4CH_MASK_SFT (0x1 << 17)
1384 #define AFE_24M_ON_MASK 0x1
1385 #define AFE_24M_ON_MASK_SFT (0x1 << 1)
1387 #define AFE_22M_ON_MASK 0x1
1388 #define AFE_22M_ON_MASK_SFT (0x1 << 0)
1392 #define IRQ12_MCU_ON_MASK 0x1
1393 #define IRQ12_MCU_ON_MASK_SFT (0x1 << 12)
1395 #define IRQ11_MCU_ON_MASK 0x1
1396 #define IRQ11_MCU_ON_MASK_SFT (0x1 << 11)
1398 #define IRQ10_MCU_ON_MASK 0x1
1399 #define IRQ10_MCU_ON_MASK_SFT (0x1 << 10)
1401 #define IRQ9_MCU_ON_MASK 0x1
1402 #define IRQ9_MCU_ON_MASK_SFT (0x1 << 9)
1404 #define IRQ8_MCU_ON_MASK 0x1
1405 #define IRQ8_MCU_ON_MASK_SFT (0x1 << 8)
1407 #define IRQ7_MCU_ON_MASK 0x1
1408 #define IRQ7_MCU_ON_MASK_SFT (0x1 << 7)
1410 #define IRQ6_MCU_ON_MASK 0x1
1411 #define IRQ6_MCU_ON_MASK_SFT (0x1 << 6)
1413 #define IRQ5_MCU_ON_MASK 0x1
1414 #define IRQ5_MCU_ON_MASK_SFT (0x1 << 5)
1416 #define IRQ4_MCU_ON_MASK 0x1
1417 #define IRQ4_MCU_ON_MASK_SFT (0x1 << 4)
1419 #define IRQ3_MCU_ON_MASK 0x1
1420 #define IRQ3_MCU_ON_MASK_SFT (0x1 << 3)
1422 #define IRQ2_MCU_ON_MASK 0x1
1423 #define IRQ2_MCU_ON_MASK_SFT (0x1 << 2)
1425 #define IRQ1_MCU_ON_MASK 0x1
1426 #define IRQ1_MCU_ON_MASK_SFT (0x1 << 1)
1428 #define IRQ0_MCU_ON_MASK 0x1
1429 #define IRQ0_MCU_ON_MASK_SFT (0x1 << 0)
1467 #define IRQ12_MCU_MISS_CNT_CLR_MASK 0x1
1468 #define IRQ12_MCU_MISS_CNT_CLR_MASK_SFT (0x1 << 28)
1470 #define IRQ11_MCU_MISS_CNT_CLR_MASK 0x1
1471 #define IRQ11_MCU_MISS_CNT_CLR_MASK_SFT (0x1 << 27)
1473 #define IRQ10_MCU_MISS_CLR_MASK 0x1
1474 #define IRQ10_MCU_MISS_CLR_MASK_SFT (0x1 << 26)
1476 #define IRQ9_MCU_MISS_CLR_MASK 0x1
1477 #define IRQ9_MCU_MISS_CLR_MASK_SFT (0x1 << 25)
1479 #define IRQ8_MCU_MISS_CLR_MASK 0x1
1480 #define IRQ8_MCU_MISS_CLR_MASK_SFT (0x1 << 24)
1482 #define IRQ7_MCU_MISS_CLR_MASK 0x1
1483 #define IRQ7_MCU_MISS_CLR_MASK_SFT (0x1 << 23)
1485 #define IRQ6_MCU_MISS_CLR_MASK 0x1
1486 #define IRQ6_MCU_MISS_CLR_MASK_SFT (0x1 << 22)
1488 #define IRQ5_MCU_MISS_CLR_MASK 0x1
1489 #define IRQ5_MCU_MISS_CLR_MASK_SFT (0x1 << 21)
1491 #define IRQ4_MCU_MISS_CLR_MASK 0x1
1492 #define IRQ4_MCU_MISS_CLR_MASK_SFT (0x1 << 20)
1494 #define IRQ3_MCU_MISS_CLR_MASK 0x1
1495 #define IRQ3_MCU_MISS_CLR_MASK_SFT (0x1 << 19)
1497 #define IRQ2_MCU_MISS_CLR_MASK 0x1
1498 #define IRQ2_MCU_MISS_CLR_MASK_SFT (0x1 << 18)
1500 #define IRQ1_MCU_MISS_CLR_MASK 0x1
1501 #define IRQ1_MCU_MISS_CLR_MASK_SFT (0x1 << 17)
1503 #define IRQ0_MCU_MISS_CLR_MASK 0x1
1504 #define IRQ0_MCU_MISS_CLR_MASK_SFT (0x1 << 16)
1506 #define IRQ12_MCU_CLR_MASK 0x1
1507 #define IRQ12_MCU_CLR_MASK_SFT (0x1 << 12)
1509 #define IRQ11_MCU_CLR_MASK 0x1
1510 #define IRQ11_MCU_CLR_MASK_SFT (0x1 << 11)
1512 #define IRQ10_MCU_CLR_MASK 0x1
1513 #define IRQ10_MCU_CLR_MASK_SFT (0x1 << 10)
1515 #define IRQ9_MCU_CLR_MASK 0x1
1516 #define IRQ9_MCU_CLR_MASK_SFT (0x1 << 9)
1518 #define IRQ8_MCU_CLR_MASK 0x1
1519 #define IRQ8_MCU_CLR_MASK_SFT (0x1 << 8)
1521 #define IRQ7_MCU_CLR_MASK 0x1
1522 #define IRQ7_MCU_CLR_MASK_SFT (0x1 << 7)
1524 #define IRQ6_MCU_CLR_MASK 0x1
1525 #define IRQ6_MCU_CLR_MASK_SFT (0x1 << 6)
1527 #define IRQ5_MCU_CLR_MASK 0x1
1528 #define IRQ5_MCU_CLR_MASK_SFT (0x1 << 5)
1530 #define IRQ4_MCU_CLR_MASK 0x1
1531 #define IRQ4_MCU_CLR_MASK_SFT (0x1 << 4)
1533 #define IRQ3_MCU_CLR_MASK 0x1
1534 #define IRQ3_MCU_CLR_MASK_SFT (0x1 << 3)
1536 #define IRQ2_MCU_CLR_MASK 0x1
1537 #define IRQ2_MCU_CLR_MASK_SFT (0x1 << 2)
1539 #define IRQ1_MCU_CLR_MASK 0x1
1540 #define IRQ1_MCU_CLR_MASK_SFT (0x1 << 1)
1542 #define IRQ0_MCU_CLR_MASK 0x1
1543 #define IRQ0_MCU_CLR_MASK_SFT (0x1 << 0)
1547 #define CPU_COMPACT_MODE_MASK 0x1
1548 #define CPU_COMPACT_MODE_MASK_SFT (0x1 << 29)
1550 #define CPU_HD_ALIGN_MASK 0x1
1551 #define CPU_HD_ALIGN_MASK_SFT (0x1 << 28)
1553 #define AWB2_AXI_WR_SIGN_MASK 0x1
1554 #define AWB2_AXI_WR_SIGN_MASK_SFT (0x1 << 24)
1556 #define VUL2_AXI_WR_SIGN_MASK 0x1
1557 #define VUL2_AXI_WR_SIGN_MASK_SFT (0x1 << 22)
1559 #define VUL12_AXI_WR_SIGN_MASK 0x1
1560 #define VUL12_AXI_WR_SIGN_MASK_SFT (0x1 << 21)
1562 #define VUL_AXI_WR_SIGN_MASK 0x1
1563 #define VUL_AXI_WR_SIGN_MASK_SFT (0x1 << 20)
1565 #define MOD_DAI_AXI_WR_SIGN_MASK 0x1
1566 #define MOD_DAI_AXI_WR_SIGN_MASK_SFT (0x1 << 18)
1568 #define AWB_MSTR_SIGN_MASK 0x1
1569 #define AWB_MSTR_SIGN_MASK_SFT (0x1 << 17)
1571 #define SYSRAM_SIGN_MASK 0x1
1572 #define SYSRAM_SIGN_MASK_SFT (0x1 << 16)
1602 #define TDM_EN_MASK 0x1
1603 #define TDM_EN_MASK_SFT (0x1 << 0)
1605 #define LRCK_INVERSE_MASK 0x1
1606 #define LRCK_INVERSE_MASK_SFT (0x1 << 2)
1608 #define DELAY_DATA_MASK 0x1
1609 #define DELAY_DATA_MASK_SFT (0x1 << 3)
1611 #define LEFT_ALIGN_MASK 0x1
1612 #define LEFT_ALIGN_MASK_SFT (0x1 << 4)
1643 #define TDM_FIX_VALUE_SEL_MASK 0x1
1644 #define TDM_FIX_VALUE_SEL_MASK_SFT (0x1 << 16)
1646 #define TDM_I2S_LOOPBACK_MASK 0x1
1647 #define TDM_I2S_LOOPBACK_MASK_SFT (0x1 << 20)
1657 #define AFE_HDMI_OUT_ON_RETM_MASK 0x1
1658 #define AFE_HDMI_OUT_ON_RETM_MASK_SFT (0x1 << 8)
1663 #define AFE_HDMI_OUT_BIT_WIDTH_MASK 0x1
1664 #define AFE_HDMI_OUT_BIT_WIDTH_MASK_SFT (0x1 << 1)
1666 #define AFE_HDMI_OUT_ON_MASK 0x1
1667 #define AFE_HDMI_OUT_ON_MASK_SFT (0x1 << 0)