Lines Matching +full:imx93 +full:- +full:iomuxc
1 // SPDX-License-Identifier: GPL-2.0+
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
23 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
27 #include "imx-pcm.h"
45 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
59 return !sai->synchronous[dir] && sai->synchronous[adir]; in fsl_sai_dir_is_synced()
66 if (sai->is_pdm_mode) { in fsl_sai_get_pins_state()
69 state = pinctrl_lookup_state(sai->pinctrl, "dsd512"); in fsl_sai_get_pins_state()
73 state = pinctrl_lookup_state(sai->pinctrl, "dsd"); in fsl_sai_get_pins_state()
77 state = pinctrl_lookup_state(sai->pinctrl, "pcm_b2m"); in fsl_sai_get_pins_state()
82 state = pinctrl_lookup_state(sai->pinctrl, "default"); in fsl_sai_get_pins_state()
90 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_isr()
91 struct device *dev = &sai->pdev->dev; in fsl_sai_isr()
103 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr); in fsl_sai_isr()
130 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr); in fsl_sai_isr()
134 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr); in fsl_sai_isr()
161 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr); in fsl_sai_isr()
172 sai->slots = slots; in fsl_sai_set_dai_tdm_slot()
173 sai->slot_width = slot_width; in fsl_sai_set_dai_tdm_slot()
183 sai->bclk_ratio = ratio; in fsl_sai_set_dai_bclk_ratio()
192 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_set_dai_sysclk_tr()
209 return -EINVAL; in fsl_sai_set_dai_sysclk_tr()
212 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), in fsl_sai_set_dai_sysclk_tr()
223 fsl_asoc_reparent_pll_clocks(dai->dev, sai->mclk_clk[clk_id], in fsl_sai_set_mclk_rate()
224 sai->pll8k_clk, sai->pll11k_clk, freq); in fsl_sai_set_mclk_rate()
226 ret = clk_set_rate(sai->mclk_clk[clk_id], freq); in fsl_sai_set_mclk_rate()
228 dev_err(dai->dev, "failed to set clock rate (%u): %d\n", freq, ret); in fsl_sai_set_mclk_rate()
244 dev_err(cpu_dai->dev, "Unknown clock id: %d\n", clk_id); in fsl_sai_set_dai_sysclk()
245 return -EINVAL; in fsl_sai_set_dai_sysclk()
248 if (IS_ERR_OR_NULL(sai->mclk_clk[clk_id])) { in fsl_sai_set_dai_sysclk()
249 dev_err(cpu_dai->dev, "Unassigned clock: %d\n", clk_id); in fsl_sai_set_dai_sysclk()
250 return -EINVAL; in fsl_sai_set_dai_sysclk()
253 if (sai->mclk_streams == 0) { in fsl_sai_set_dai_sysclk()
262 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); in fsl_sai_set_dai_sysclk()
268 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); in fsl_sai_set_dai_sysclk()
277 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_set_dai_fmt_tr()
280 if (!sai->is_lsb_first) in fsl_sai_set_dai_fmt_tr()
283 sai->is_pdm_mode = false; in fsl_sai_set_dai_fmt_tr()
284 sai->is_dsp_mode = false; in fsl_sai_set_dai_fmt_tr()
313 sai->is_dsp_mode = true; in fsl_sai_set_dai_fmt_tr()
321 sai->is_dsp_mode = true; in fsl_sai_set_dai_fmt_tr()
326 sai->is_pdm_mode = true; in fsl_sai_set_dai_fmt_tr()
331 return -EINVAL; in fsl_sai_set_dai_fmt_tr()
353 return -EINVAL; in fsl_sai_set_dai_fmt_tr()
361 sai->is_consumer_mode = false; in fsl_sai_set_dai_fmt_tr()
364 sai->is_consumer_mode = true; in fsl_sai_set_dai_fmt_tr()
368 sai->is_consumer_mode = false; in fsl_sai_set_dai_fmt_tr()
372 sai->is_consumer_mode = true; in fsl_sai_set_dai_fmt_tr()
375 return -EINVAL; in fsl_sai_set_dai_fmt_tr()
378 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), in fsl_sai_set_dai_fmt_tr()
380 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), in fsl_sai_set_dai_fmt_tr()
393 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); in fsl_sai_set_dai_fmt()
399 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); in fsl_sai_set_dai_fmt()
407 unsigned int reg, ofs = sai->soc_data->reg_offset; in fsl_sai_set_bclk()
413 bool support_1_1_ratio = sai->verid.version >= 0x0301; in fsl_sai_set_bclk()
416 if (sai->is_consumer_mode) in fsl_sai_set_bclk()
424 id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0; in fsl_sai_set_bclk()
429 clk_rate = clk_get_rate(sai->mclk_clk[id]); in fsl_sai_set_bclk()
441 diff = abs((long)clk_rate - ratio * freq); in fsl_sai_set_bclk()
450 dev_dbg(dai->dev, in fsl_sai_set_bclk()
457 sai->mclk_id[tx] = id; in fsl_sai_set_bclk()
466 dev_err(dai->dev, "failed to derive required %cx rate: %d\n", in fsl_sai_set_bclk()
468 return -EINVAL; in fsl_sai_set_bclk()
471 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", in fsl_sai_set_bclk()
472 sai->mclk_id[tx], savediv, bestdiff); in fsl_sai_set_bclk()
486 else if (!sai->synchronous[dir]) in fsl_sai_set_bclk()
491 regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK, in fsl_sai_set_bclk()
492 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); in fsl_sai_set_bclk()
495 regmap_update_bits(sai->regmap, reg, in fsl_sai_set_bclk()
499 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), in fsl_sai_set_bclk()
502 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), in fsl_sai_set_bclk()
505 regmap_update_bits(sai->regmap, reg, in fsl_sai_set_bclk()
507 savediv / 2 - 1); in fsl_sai_set_bclk()
518 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_hw_params()
519 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_sai_hw_params()
522 struct fsl_sai_dl_cfg *dl_cfg = sai->dl_cfg; in fsl_sai_hw_params()
525 int dl_cfg_cnt = sai->dl_cfg_cnt; in fsl_sai_hw_params()
535 if (sai->slot_width) in fsl_sai_hw_params()
536 slot_width = sai->slot_width; in fsl_sai_hw_params()
538 if (sai->slots) in fsl_sai_hw_params()
539 slots = sai->slots; in fsl_sai_hw_params()
540 else if (sai->bclk_ratio) in fsl_sai_hw_params()
541 slots = sai->bclk_ratio / slot_width; in fsl_sai_hw_params()
549 if (sai->is_pdm_mode) { in fsl_sai_hw_params()
562 dev_err(cpu_dai->dev, "channel not supported\n"); in fsl_sai_hw_params()
563 return -EINVAL; in fsl_sai_hw_params()
566 bclk = params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots * slot_width); in fsl_sai_hw_params()
568 if (!IS_ERR_OR_NULL(sai->pinctrl)) { in fsl_sai_hw_params()
569 sai->pins_state = fsl_sai_get_pins_state(sai, bclk); in fsl_sai_hw_params()
570 if (!IS_ERR_OR_NULL(sai->pins_state)) { in fsl_sai_hw_params()
571 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); in fsl_sai_hw_params()
573 dev_err(cpu_dai->dev, "failed to set proper pins state: %d\n", ret); in fsl_sai_hw_params()
579 if (!sai->is_consumer_mode) { in fsl_sai_hw_params()
585 if (!(sai->mclk_streams & BIT(substream->stream))) { in fsl_sai_hw_params()
586 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); in fsl_sai_hw_params()
590 sai->mclk_streams |= BIT(substream->stream); in fsl_sai_hw_params()
594 if (!sai->is_dsp_mode && !sai->is_pdm_mode) in fsl_sai_hw_params()
600 if (sai->is_lsb_first || sai->is_pdm_mode) in fsl_sai_hw_params()
603 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); in fsl_sai_hw_params()
607 /* Set to output mode to avoid tri-stated data pins */ in fsl_sai_hw_params()
617 if (!sai->is_consumer_mode && fsl_sai_dir_is_synced(sai, adir)) { in fsl_sai_hw_params()
618 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs), in fsl_sai_hw_params()
622 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs), in fsl_sai_hw_params()
629 * - Can't used for singel dataline/FIFO case except the FIFO0 in fsl_sai_hw_params()
630 * - Can't used for multi dataline/FIFO case except the enabled FIFOs in fsl_sai_hw_params()
635 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) <= 1 || sai->is_multi_fifo_dma) in fsl_sai_hw_params()
636 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), in fsl_sai_hw_params()
639 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), in fsl_sai_hw_params()
642 dma_params = tx ? &sai->dma_params_tx : &sai->dma_params_rx; in fsl_sai_hw_params()
643 dma_params->addr = sai->res->start + FSL_SAI_xDR0(tx) + in fsl_sai_hw_params()
646 if (sai->is_multi_fifo_dma) { in fsl_sai_hw_params()
647 sai->audio_config[tx].words_per_fifo = min(slots, channels); in fsl_sai_hw_params()
649 sai->audio_config[tx].n_fifos_dst = pins; in fsl_sai_hw_params()
650 sai->audio_config[tx].stride_fifos_dst = dl_cfg[dl_cfg_idx].next_off[tx]; in fsl_sai_hw_params()
652 sai->audio_config[tx].n_fifos_src = pins; in fsl_sai_hw_params()
653 sai->audio_config[tx].stride_fifos_src = dl_cfg[dl_cfg_idx].next_off[tx]; in fsl_sai_hw_params()
655 dma_params->maxburst = sai->audio_config[tx].words_per_fifo * pins; in fsl_sai_hw_params()
656 dma_params->peripheral_config = &sai->audio_config[tx]; in fsl_sai_hw_params()
657 dma_params->peripheral_size = sizeof(sai->audio_config[tx]); in fsl_sai_hw_params()
659 watermark = tx ? (sai->soc_data->fifo_depth - dma_params->maxburst) : in fsl_sai_hw_params()
660 (dma_params->maxburst - 1); in fsl_sai_hw_params()
661 regmap_update_bits(sai->regmap, FSL_SAI_xCR1(tx, ofs), in fsl_sai_hw_params()
662 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), in fsl_sai_hw_params()
667 for (i = 0; i < sai->soc_data->pins; i++) { in fsl_sai_hw_params()
668 trce_mask = (1 << (i + 1)) - 1; in fsl_sai_hw_params()
673 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), in fsl_sai_hw_params()
677 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), in fsl_sai_hw_params()
681 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs), in fsl_sai_hw_params()
684 regmap_write(sai->regmap, FSL_SAI_xMR(tx), in fsl_sai_hw_params()
685 ~0UL - ((1 << min(channels, slots)) - 1)); in fsl_sai_hw_params()
694 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_sai_hw_free()
695 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_hw_free()
697 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), in fsl_sai_hw_free()
700 if (!sai->is_consumer_mode && in fsl_sai_hw_free()
701 sai->mclk_streams & BIT(substream->stream)) { in fsl_sai_hw_free()
702 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); in fsl_sai_hw_free()
703 sai->mclk_streams &= ~BIT(substream->stream); in fsl_sai_hw_free()
711 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_config_disable()
715 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output) in fsl_sai_config_disable()
720 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_config_disable()
726 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr); in fsl_sai_config_disable()
727 } while (--count && xcsr & FSL_SAI_CSR_TERE); in fsl_sai_config_disable()
729 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_config_disable()
739 if (!sai->is_consumer_mode) { in fsl_sai_config_disable()
741 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR); in fsl_sai_config_disable()
743 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0); in fsl_sai_config_disable()
751 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_trigger()
753 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_sai_trigger()
763 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC, in fsl_sai_trigger()
764 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); in fsl_sai_trigger()
765 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC, in fsl_sai_trigger()
766 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); in fsl_sai_trigger()
776 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_trigger()
779 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_trigger()
793 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs), in fsl_sai_trigger()
796 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_trigger()
802 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_trigger()
804 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_trigger()
808 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr); in fsl_sai_trigger()
828 return -EINVAL; in fsl_sai_trigger()
838 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_sai_startup()
845 if (sai->soc_data->use_edma) in fsl_sai_startup()
846 snd_pcm_hw_constraint_step(substream->runtime, 0, in fsl_sai_startup()
848 tx ? sai->dma_params_tx.maxburst : in fsl_sai_startup()
849 sai->dma_params_rx.maxburst); in fsl_sai_startup()
851 ret = snd_pcm_hw_constraint_list(substream->runtime, 0, in fsl_sai_startup()
859 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); in fsl_sai_dai_probe()
860 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_dai_probe()
863 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); in fsl_sai_dai_probe()
864 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); in fsl_sai_dai_probe()
866 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); in fsl_sai_dai_probe()
867 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); in fsl_sai_dai_probe()
869 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs), in fsl_sai_dai_probe()
870 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), in fsl_sai_dai_probe()
871 sai->soc_data->fifo_depth - sai->dma_params_tx.maxburst); in fsl_sai_dai_probe()
872 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs), in fsl_sai_dai_probe()
873 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), in fsl_sai_dai_probe()
874 sai->dma_params_rx.maxburst - 1); in fsl_sai_dai_probe()
876 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, in fsl_sai_dai_probe()
877 &sai->dma_params_rx); in fsl_sai_dai_probe()
897 struct device *dev = &sai->pdev->dev; in fsl_sai_dai_resume()
900 if (!IS_ERR_OR_NULL(sai->pinctrl) && !IS_ERR_OR_NULL(sai->pins_state)) { in fsl_sai_dai_resume()
901 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); in fsl_sai_dai_resume()
913 .stream_name = "CPU-Playback",
922 .stream_name = "CPU-Capture",
934 .name = "fsl-sai",
990 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_readable_reg()
1046 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_volatile_reg()
1089 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_writeable_reg()
1136 unsigned char ofs = sai->soc_data->reg_offset; in fsl_sai_check_version()
1143 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val); in fsl_sai_check_version()
1149 sai->verid.version = val & in fsl_sai_check_version()
1151 sai->verid.version >>= FSL_SAI_VERID_MINOR_SHIFT; in fsl_sai_check_version()
1152 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK; in fsl_sai_check_version()
1154 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val); in fsl_sai_check_version()
1161 sai->param.slot_num = 1 << in fsl_sai_check_version()
1165 sai->param.fifo_depth = 1 << in fsl_sai_check_version()
1169 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK; in fsl_sai_check_version()
1184 offset = nbidx - fbidx - 1; in fsl_sai_calc_dl_off()
1186 return (offset < 0 || offset >= (FSL_SAI_DL_NUM - 1) ? 0 : offset); in fsl_sai_calc_dl_off()
1203 struct platform_device *pdev = sai->pdev; in fsl_sai_read_dlcfg()
1204 struct device_node *np = pdev->dev.of_node; in fsl_sai_read_dlcfg()
1205 struct device *dev = &pdev->dev; in fsl_sai_read_dlcfg()
1219 return -EINVAL; in fsl_sai_read_dlcfg()
1224 cfg = devm_kzalloc(&pdev->dev, (num_cfg + 1) * sizeof(*cfg), GFP_KERNEL); in fsl_sai_read_dlcfg()
1226 return -ENOMEM; in fsl_sai_read_dlcfg()
1229 soc_dl = BIT(sai->soc_data->pins) - 1; in fsl_sai_read_dlcfg()
1231 cfg[0].pins[0] = sai->soc_data->pins; in fsl_sai_read_dlcfg()
1236 cfg[0].pins[1] = sai->soc_data->pins; in fsl_sai_read_dlcfg()
1249 return -EINVAL; in fsl_sai_read_dlcfg()
1253 return -EINVAL; in fsl_sai_read_dlcfg()
1257 return -EINVAL; in fsl_sai_read_dlcfg()
1261 return -EINVAL; in fsl_sai_read_dlcfg()
1281 sai->dl_cfg = cfg; in fsl_sai_read_dlcfg()
1282 sai->dl_cfg_cnt = num_cfg + 1; in fsl_sai_read_dlcfg()
1291 struct device_node *np = pdev->dev.of_node; in fsl_sai_probe()
1292 struct device *dev = &pdev->dev; in fsl_sai_probe()
1303 return -ENOMEM; in fsl_sai_probe()
1305 sai->pdev = pdev; in fsl_sai_probe()
1306 sai->soc_data = of_device_get_match_data(dev); in fsl_sai_probe()
1308 sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); in fsl_sai_probe()
1310 base = devm_platform_get_and_ioremap_resource(pdev, 0, &sai->res); in fsl_sai_probe()
1314 if (sai->soc_data->reg_offset == 8) { in fsl_sai_probe()
1321 sai->regmap = devm_regmap_init_mmio(dev, base, &fsl_sai_regmap_config); in fsl_sai_probe()
1322 if (IS_ERR(sai->regmap)) { in fsl_sai_probe()
1324 return PTR_ERR(sai->regmap); in fsl_sai_probe()
1327 sai->bus_clk = devm_clk_get(dev, "bus"); in fsl_sai_probe()
1329 if (IS_ERR(sai->bus_clk) && PTR_ERR(sai->bus_clk) != -EPROBE_DEFER) in fsl_sai_probe()
1330 sai->bus_clk = devm_clk_get(dev, "sai"); in fsl_sai_probe()
1331 if (IS_ERR(sai->bus_clk)) { in fsl_sai_probe()
1333 PTR_ERR(sai->bus_clk)); in fsl_sai_probe()
1334 /* -EPROBE_DEFER */ in fsl_sai_probe()
1335 return PTR_ERR(sai->bus_clk); in fsl_sai_probe()
1340 sai->mclk_clk[i] = devm_clk_get(dev, tmp); in fsl_sai_probe()
1341 if (IS_ERR(sai->mclk_clk[i])) { in fsl_sai_probe()
1343 i, PTR_ERR(sai->mclk_clk[i])); in fsl_sai_probe()
1344 sai->mclk_clk[i] = NULL; in fsl_sai_probe()
1348 if (sai->soc_data->mclk0_is_mclk1) in fsl_sai_probe()
1349 sai->mclk_clk[0] = sai->mclk_clk[1]; in fsl_sai_probe()
1351 sai->mclk_clk[0] = sai->bus_clk; in fsl_sai_probe()
1353 fsl_asoc_get_pll_clocks(&pdev->dev, &sai->pll8k_clk, in fsl_sai_probe()
1354 &sai->pll11k_clk); in fsl_sai_probe()
1358 if (!sai->soc_data->use_edma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI) in fsl_sai_probe()
1359 sai->is_multi_fifo_dma = true; in fsl_sai_probe()
1373 np->name, sai); in fsl_sai_probe()
1379 memcpy(&sai->cpu_dai_drv, &fsl_sai_dai_template, in fsl_sai_probe()
1383 sai->synchronous[RX] = true; in fsl_sai_probe()
1384 sai->synchronous[TX] = false; in fsl_sai_probe()
1385 sai->cpu_dai_drv.symmetric_rate = 1; in fsl_sai_probe()
1386 sai->cpu_dai_drv.symmetric_channels = 1; in fsl_sai_probe()
1387 sai->cpu_dai_drv.symmetric_sample_bits = 1; in fsl_sai_probe()
1389 if (of_property_read_bool(np, "fsl,sai-synchronous-rx") && in fsl_sai_probe()
1390 of_property_read_bool(np, "fsl,sai-asynchronous")) { in fsl_sai_probe()
1393 return -EINVAL; in fsl_sai_probe()
1396 if (of_property_read_bool(np, "fsl,sai-synchronous-rx")) { in fsl_sai_probe()
1398 sai->synchronous[RX] = false; in fsl_sai_probe()
1399 sai->synchronous[TX] = true; in fsl_sai_probe()
1400 } else if (of_property_read_bool(np, "fsl,sai-asynchronous")) { in fsl_sai_probe()
1402 sai->synchronous[RX] = false; in fsl_sai_probe()
1403 sai->synchronous[TX] = false; in fsl_sai_probe()
1404 sai->cpu_dai_drv.symmetric_rate = 0; in fsl_sai_probe()
1405 sai->cpu_dai_drv.symmetric_channels = 0; in fsl_sai_probe()
1406 sai->cpu_dai_drv.symmetric_sample_bits = 0; in fsl_sai_probe()
1409 sai->mclk_direction_output = of_property_read_bool(np, "fsl,sai-mclk-direction-output"); in fsl_sai_probe()
1411 if (sai->mclk_direction_output && in fsl_sai_probe()
1412 of_device_is_compatible(np, "fsl,imx6ul-sai")) { in fsl_sai_probe()
1413 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); in fsl_sai_probe()
1415 dev_err(dev, "cannot find iomuxc registers\n"); in fsl_sai_probe()
1427 sai->dma_params_rx.addr = sai->res->start + FSL_SAI_RDR0; in fsl_sai_probe()
1428 sai->dma_params_tx.addr = sai->res->start + FSL_SAI_TDR0; in fsl_sai_probe()
1429 sai->dma_params_rx.maxburst = in fsl_sai_probe()
1430 sai->soc_data->max_burst[RX] ? sai->soc_data->max_burst[RX] : FSL_SAI_MAXBURST_RX; in fsl_sai_probe()
1431 sai->dma_params_tx.maxburst = in fsl_sai_probe()
1432 sai->soc_data->max_burst[TX] ? sai->soc_data->max_burst[TX] : FSL_SAI_MAXBURST_TX; in fsl_sai_probe()
1434 sai->pinctrl = devm_pinctrl_get(&pdev->dev); in fsl_sai_probe()
1454 if (sai->mclk_direction_output && in fsl_sai_probe()
1455 sai->soc_data->max_register >= FSL_SAI_MCTL) { in fsl_sai_probe()
1456 regmap_update_bits(sai->regmap, FSL_SAI_MCTL, in fsl_sai_probe()
1461 if (ret < 0 && ret != -ENOSYS) in fsl_sai_probe()
1468 if (sai->soc_data->use_imx_pcm) { in fsl_sai_probe()
1473 dev_err(dev, "Error: You must enable the imx-pcm-dma support!\n"); in fsl_sai_probe()
1485 &sai->cpu_dai_drv, 1); in fsl_sai_probe()
1502 pm_runtime_disable(&pdev->dev); in fsl_sai_remove()
1503 if (!pm_runtime_status_suspended(&pdev->dev)) in fsl_sai_remove()
1504 fsl_sai_runtime_suspend(&pdev->dev); in fsl_sai_remove()
1620 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data },
1621 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data },
1622 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data },
1623 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data },
1624 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data },
1625 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data },
1626 { .compatible = "fsl,imx8mm-sai", .data = &fsl_sai_imx8mm_data },
1627 { .compatible = "fsl,imx8mp-sai", .data = &fsl_sai_imx8mp_data },
1628 { .compatible = "fsl,imx8ulp-sai", .data = &fsl_sai_imx8ulp_data },
1629 { .compatible = "fsl,imx8mn-sai", .data = &fsl_sai_imx8mn_data },
1630 { .compatible = "fsl,imx93-sai", .data = &fsl_sai_imx93_data },
1639 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) in fsl_sai_runtime_suspend()
1640 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); in fsl_sai_runtime_suspend()
1642 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) in fsl_sai_runtime_suspend()
1643 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); in fsl_sai_runtime_suspend()
1645 clk_disable_unprepare(sai->bus_clk); in fsl_sai_runtime_suspend()
1647 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) in fsl_sai_runtime_suspend()
1648 cpu_latency_qos_remove_request(&sai->pm_qos_req); in fsl_sai_runtime_suspend()
1650 regcache_cache_only(sai->regmap, true); in fsl_sai_runtime_suspend()
1658 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_runtime_resume()
1661 ret = clk_prepare_enable(sai->bus_clk); in fsl_sai_runtime_resume()
1667 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) { in fsl_sai_runtime_resume()
1668 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]); in fsl_sai_runtime_resume()
1673 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) { in fsl_sai_runtime_resume()
1674 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]); in fsl_sai_runtime_resume()
1679 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) in fsl_sai_runtime_resume()
1680 cpu_latency_qos_add_request(&sai->pm_qos_req, 0); in fsl_sai_runtime_resume()
1682 regcache_cache_only(sai->regmap, false); in fsl_sai_runtime_resume()
1683 regcache_mark_dirty(sai->regmap); in fsl_sai_runtime_resume()
1684 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); in fsl_sai_runtime_resume()
1685 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); in fsl_sai_runtime_resume()
1687 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); in fsl_sai_runtime_resume()
1688 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); in fsl_sai_runtime_resume()
1690 ret = regcache_sync(sai->regmap); in fsl_sai_runtime_resume()
1694 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output) in fsl_sai_runtime_resume()
1695 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), in fsl_sai_runtime_resume()
1701 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) in fsl_sai_runtime_resume()
1702 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); in fsl_sai_runtime_resume()
1704 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) in fsl_sai_runtime_resume()
1705 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); in fsl_sai_runtime_resume()
1707 clk_disable_unprepare(sai->bus_clk); in fsl_sai_runtime_resume()
1723 .name = "fsl-sai",
1732 MODULE_ALIAS("platform:fsl-sai");