Lines Matching +full:4 +full:- +full:switch
1 // SPDX-License-Identifier: GPL-2.0-only
16 * ---------------------------------------
17 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
18 * | IN1L -> LINE1L
19 * | IN1R -> LINE1R
20 * | IN2L -> LINE2L
21 * | IN2R -> LINE2R
22 * | MIC3L/R -> N/A
25 * ---------------------------------------
51 #define AIC3X_NUM_SUPPLIES 4
89 /* Output Common-Mode Voltage */
95 { 4, 0x04 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 },
126 switch (reg) { in aic3x_volatile_reg()
159 (struct soc_mixer_control *)kcontrol->private_value; in snd_soc_dapm_put_volsw_aic3x()
160 unsigned int reg = mc->reg; in snd_soc_dapm_put_volsw_aic3x()
161 unsigned int shift = mc->shift; in snd_soc_dapm_put_volsw_aic3x()
162 int max = mc->max; in snd_soc_dapm_put_volsw_aic3x()
163 unsigned int mask = (1 << fls(max)) - 1; in snd_soc_dapm_put_volsw_aic3x()
164 unsigned int invert = mc->invert; in snd_soc_dapm_put_volsw_aic3x()
169 val = (ucontrol->value.integer.value[0] & mask); in snd_soc_dapm_put_volsw_aic3x()
178 val = mask - val; in snd_soc_dapm_put_volsw_aic3x()
209 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in mic_bias_event()
212 switch (event) { in mic_bias_event()
217 aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT); in mic_bias_event()
235 static SOC_ENUM_SINGLE_DECL(aic3x_right_dac_enum, DAC_LINE_MUX, 4,
239 "differential of HPLOUT", "constant VCM", "single-ended" };
240 static SOC_ENUM_SINGLE_DECL(aic3x_left_hpcom_enum, HPLCOM_CFG, 4,
244 "differential of HPROUT", "constant VCM", "single-ended",
250 "single-ended", "differential" };
266 static SOC_ENUM_DOUBLE_DECL(aic3x_adc_hpf_enum, AIC3X_CODEC_DFILT_CTRL, 6, 4,
270 "-5.5dB", "-8dB", "-10dB", "-12dB",
271 "-14dB", "-17dB", "-20dB", "-24dB" };
272 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_level_enum, LAGC_CTRL_A, 4,
274 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_level_enum, RAGC_CTRL_A, 4,
293 "100ms", "200ms", "400ms", "800ms", "2s", "4s" };
294 static SOC_ENUM_SINGLE_DECL(aic3x_poweron_time_enum, HPOUT_POP_REDUCTION, 4,
297 static const char * const aic3x_rampup_step[] = { "0ms", "1ms", "2ms", "4ms" };
302 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
304 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
308 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
311 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
313 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
314 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
316 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
328 * only for swapped L-to-R and R-to-L routes. See below stereo controls
329 * for direct L-to-L and R-to-R routes.
361 /* Stereo output controls for direct L-to-L and R-to-R routes */
384 SOC_DOUBLE_R_TLV("Line Playback Volume", LLOPM_CTRL, RLOPM_CTRL, 4,
386 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
388 SOC_DOUBLE_R_TLV("HP Playback Volume", HPLOUT_CTRL, HPROUT_CTRL, 4,
390 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
393 4, 9, 0, out_tlv),
394 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
401 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
409 /* De-emphasis */
410 SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0),
415 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
417 SOC_ENUM("ADC HPF Cut-off", aic3x_adc_hpf_enum),
420 SOC_ENUM("Output Driver Power-On time", aic3x_poweron_time_enum),
421 SOC_ENUM("Output Driver Ramp-up step", aic3x_rampup_step_enum),
428 * only for swapped L-to-R and R-to-L routes. See below stereo controls
429 * for direct L-to-L and R-to-R routes.
449 /* Stereo output controls for direct L-to-L and R-to-R routes */
474 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
475 SOC_SINGLE_TLV("Mono Playback Volume", MONOLOPM_CTRL, 4, 9, 0,
481 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
486 SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
506 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
507 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
508 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
509 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
511 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
512 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
517 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
518 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
519 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
520 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
522 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
523 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
528 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
529 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
530 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
531 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
532 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
533 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
538 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
539 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
540 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
541 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
543 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
544 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
549 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
550 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
551 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
552 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
554 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
555 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
560 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
561 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
562 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
563 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
565 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
566 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
571 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
572 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
573 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
574 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
576 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
577 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
582 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
583 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
584 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
585 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
586 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
591 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
592 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
593 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
594 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
595 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
600 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
601 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
602 SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
603 SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
608 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
609 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
610 SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
611 SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
716 AIC3X_GPIO1_REG, 4, 0xf,
772 ARRAY_SIZE(aic3x_left_line_mixer_controls) - 2),
775 ARRAY_SIZE(aic3x_right_line_mixer_controls) - 2),
778 ARRAY_SIZE(aic3x_left_hp_mixer_controls) - 2),
781 ARRAY_SIZE(aic3x_right_hp_mixer_controls) - 2),
784 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls) - 2),
787 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls) - 2),
805 /* Class-D outputs */
806 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
807 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
815 {"Left Line1L Mux", "single-ended", "LINE1L"},
817 {"Left Line1R Mux", "single-ended", "LINE1R"},
820 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
821 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
826 {"Right Line1R Mux", "single-ended", "LINE1R"},
828 {"Right Line1L Mux", "single-ended", "LINE1L"},
831 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
832 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
847 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
848 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
849 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
850 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
857 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
858 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
859 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
860 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
867 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
868 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
869 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
870 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
877 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
878 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
879 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
880 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
887 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
888 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
889 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
890 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
894 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
899 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
900 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
901 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
902 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
906 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
916 {"Left Line2L Mux", "single-ended", "LINE2L"},
919 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
920 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
921 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
926 {"Right Line2R Mux", "single-ended", "LINE2R"},
929 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
930 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
931 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
944 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
945 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
948 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
949 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
952 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
953 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
956 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
957 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
960 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
961 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
964 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
965 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
971 {"Left PGA Mixer", "Mic2L Switch", "MIC2L"},
972 {"Left PGA Mixer", "Mic2R Switch", "MIC2R"},
975 {"Right PGA Mixer", "Mic2L Switch", "MIC2L"},
976 {"Right PGA Mixer", "Mic2R Switch", "MIC2R"},
981 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
982 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
983 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
984 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
985 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
986 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
992 /* Class-D outputs */
993 {"Left Class-D Out", NULL, "Left Line Out"},
994 {"Right Class-D Out", NULL, "Left Line Out"},
995 {"SPOP", NULL, "Left Class-D Out"},
996 {"SPOM", NULL, "Right Class-D Out"},
1004 switch (aic3x->model) { in aic3x_add_widgets()
1042 struct snd_soc_component *component = dai->component; in aic3x_hw_params()
1048 int width = aic3x->slot_width; in aic3x_hw_params()
1054 data = snd_soc_component_read(component, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4)); in aic3x_hw_params()
1055 switch (width) { in aic3x_hw_params()
1059 data |= (0x01 << 4); in aic3x_hw_params()
1062 data |= (0x02 << 4); in aic3x_hw_params()
1065 data |= (0x03 << 4); in aic3x_hw_params()
1076 if (aic3x->sysclk / (128 * pll_q) == fsref) { in aic3x_hw_params()
1108 data -= 2; in aic3x_hw_params()
1109 data |= (data << 4); in aic3x_hw_params()
1121 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000); in aic3x_hw_params()
1125 for (j = 4; j <= 55; j++) { in aic3x_hw_params()
1135 if (abs(codec_clk - tmp_clk) < in aic3x_hw_params()
1136 abs(codec_clk - last_clk)) { in aic3x_hw_params()
1152 if (j < 4 || j > 11) in aic3x_hw_params()
1156 d = ((2048 * p * fsref) - j * aic3x->sysclk) in aic3x_hw_params()
1157 * 100 / (aic3x->sysclk/100); in aic3x_hw_params()
1163 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) { in aic3x_hw_params()
1175 return -EINVAL; in aic3x_hw_params()
1194 struct snd_soc_component *component = dai->component; in aic3x_prepare()
1197 int width = aic3x->slot_width; in aic3x_prepare()
1200 width = substream->runtime->sample_bits; in aic3x_prepare()
1203 if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_A) in aic3x_prepare()
1204 delay += (aic3x->tdm_delay*width + 1); in aic3x_prepare()
1205 else if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_B) in aic3x_prepare()
1206 delay += aic3x->tdm_delay*width; in aic3x_prepare()
1216 struct snd_soc_component *component = dai->component; in aic3x_mute()
1234 struct snd_soc_component *component = codec_dai->component; in aic3x_set_dai_sysclk()
1243 aic3x->sysclk = freq; in aic3x_set_dai_sysclk()
1250 struct snd_soc_component *component = codec_dai->component; in aic3x_set_dai_fmt()
1257 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { in aic3x_set_dai_fmt()
1259 aic3x->master = 1; in aic3x_set_dai_fmt()
1263 aic3x->master = 0; in aic3x_set_dai_fmt()
1267 aic3x->master = 1; in aic3x_set_dai_fmt()
1272 aic3x->master = 1; in aic3x_set_dai_fmt()
1277 return -EINVAL; in aic3x_set_dai_fmt()
1284 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK | in aic3x_set_dai_fmt()
1299 return -EINVAL; in aic3x_set_dai_fmt()
1302 aic3x->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; in aic3x_set_dai_fmt()
1315 struct snd_soc_component *component = codec_dai->component; in aic3x_set_dai_tdm_slot()
1320 dev_err(component->dev, "tx and rx masks must be symmetric\n"); in aic3x_set_dai_tdm_slot()
1321 return -EINVAL; in aic3x_set_dai_tdm_slot()
1325 dev_err(component->dev, "tx and rx masks need to be non 0\n"); in aic3x_set_dai_tdm_slot()
1326 return -EINVAL; in aic3x_set_dai_tdm_slot()
1332 dev_err(component->dev, "Invalid mask, slots must be adjacent\n"); in aic3x_set_dai_tdm_slot()
1333 return -EINVAL; in aic3x_set_dai_tdm_slot()
1336 switch (slot_width) { in aic3x_set_dai_tdm_slot()
1343 dev_err(component->dev, "Unsupported slot width %d\n", slot_width); in aic3x_set_dai_tdm_slot()
1344 return -EINVAL; in aic3x_set_dai_tdm_slot()
1348 aic3x->tdm_delay = lsb; in aic3x_set_dai_tdm_slot()
1349 aic3x->slot_width = slot_width; in aic3x_set_dai_tdm_slot()
1351 /* DOUT in high-impedance on inactive bit clocks */ in aic3x_set_dai_tdm_slot()
1363 struct aic3x_priv *aic3x = disable_nb->aic3x; in aic3x_regulator_event()
1370 if (aic3x->gpio_reset) in aic3x_regulator_event()
1371 gpiod_set_value(aic3x->gpio_reset, 1); in aic3x_regulator_event()
1372 regcache_mark_dirty(aic3x->regmap); in aic3x_regulator_event()
1385 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies), in aic3x_set_power()
1386 aic3x->supplies); in aic3x_set_power()
1389 aic3x->power = 1; in aic3x_set_power()
1391 if (aic3x->gpio_reset) { in aic3x_set_power()
1393 gpiod_set_value(aic3x->gpio_reset, 0); in aic3x_set_power()
1397 regcache_cache_only(aic3x->regmap, false); in aic3x_set_power()
1398 regcache_sync(aic3x->regmap); in aic3x_set_power()
1413 * Delay is needed to reduce pop-noise after syncing back the in aic3x_set_power()
1424 regcache_mark_dirty(aic3x->regmap); in aic3x_set_power()
1425 aic3x->power = 0; in aic3x_set_power()
1427 regcache_cache_only(aic3x->regmap, true); in aic3x_set_power()
1428 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies), in aic3x_set_power()
1429 aic3x->supplies); in aic3x_set_power()
1440 switch (level) { in aic3x_set_bias_level()
1445 aic3x->master) { in aic3x_set_bias_level()
1452 if (!aic3x->power) in aic3x_set_bias_level()
1455 aic3x->master) { in aic3x_set_bias_level()
1462 if (aic3x->power) in aic3x_set_bias_level()
1486 .name = "tlv320aic3x-hifi",
1570 if (aic3x->model != AIC3X_MODEL_3104) { in aic3x_init()
1581 switch (aic3x->model) { in aic3x_init()
1592 /* Output common-mode voltage = 1.5 V */ in aic3x_init()
1594 aic3x->ocmv << HPOUT_SC_OCMV_SHIFT); in aic3x_init()
1604 aic3x->component = component; in aic3x_component_probe()
1606 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) { in aic3x_component_probe()
1607 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event; in aic3x_component_probe()
1608 aic3x->disable_nb[i].aic3x = aic3x; in aic3x_component_probe()
1610 aic3x->supplies[i].consumer, in aic3x_component_probe()
1611 &aic3x->disable_nb[i].nb); in aic3x_component_probe()
1613 dev_err(component->dev, in aic3x_component_probe()
1620 regcache_mark_dirty(aic3x->regmap); in aic3x_component_probe()
1623 if (aic3x->setup) { in aic3x_component_probe()
1624 if (aic3x->model != AIC3X_MODEL_3104) { in aic3x_component_probe()
1627 (aic3x->setup->gpio_func[0] & 0xf) << 4); in aic3x_component_probe()
1629 (aic3x->setup->gpio_func[1] & 0xf) << 4); in aic3x_component_probe()
1631 dev_warn(component->dev, "GPIO functionality is not supported on tlv320aic3104\n"); in aic3x_component_probe()
1635 switch (aic3x->model) { in aic3x_component_probe()
1655 switch (aic3x->micbias_vg) { in aic3x_component_probe()
1661 (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT); in aic3x_component_probe()
1667 * 'AIC3X_MICBIAS_OFF' not handled in switch" in aic3x_component_probe()
1692 struct device_node *np = dev->of_node; in aic3x_configure_ocmv()
1696 if (np && !of_property_read_u32(np, "ai3x-ocmv", &value)) { in aic3x_configure_ocmv()
1699 aic3x->ocmv = value; in aic3x_configure_ocmv()
1704 dvdd = regulator_get_voltage(aic3x->supplies[1].consumer); in aic3x_configure_ocmv()
1705 avdd = regulator_get_voltage(aic3x->supplies[2].consumer); in aic3x_configure_ocmv()
1712 aic3x->ocmv = HPOUT_SC_OCMV_1_8V; in aic3x_configure_ocmv()
1714 aic3x->ocmv = HPOUT_SC_OCMV_1_65V; in aic3x_configure_ocmv()
1716 aic3x->ocmv = HPOUT_SC_OCMV_1_5V; in aic3x_configure_ocmv()
1718 aic3x->ocmv = HPOUT_SC_OCMV_1_35V; in aic3x_configure_ocmv()
1728 /* Class-D speaker driver init; datasheet p. 46 */
1741 struct device_node *np = dev->of_node; in aic3x_probe()
1747 return -ENOMEM; in aic3x_probe()
1749 aic3x->regmap = regmap; in aic3x_probe()
1750 if (IS_ERR(aic3x->regmap)) { in aic3x_probe()
1751 ret = PTR_ERR(aic3x->regmap); in aic3x_probe()
1755 regcache_cache_only(aic3x->regmap, true); in aic3x_probe()
1761 return -ENOMEM; in aic3x_probe()
1763 if (of_property_read_u32_array(np, "ai3x-gpio-func", in aic3x_probe()
1764 ai3x_setup->gpio_func, 2) >= 0) { in aic3x_probe()
1765 aic3x->setup = ai3x_setup; in aic3x_probe()
1768 if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) { in aic3x_probe()
1769 switch (value) { in aic3x_probe()
1771 aic3x->micbias_vg = AIC3X_MICBIAS_2_0V; in aic3x_probe()
1774 aic3x->micbias_vg = AIC3X_MICBIAS_2_5V; in aic3x_probe()
1777 aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV; in aic3x_probe()
1780 aic3x->micbias_vg = AIC3X_MICBIAS_OFF; in aic3x_probe()
1785 aic3x->micbias_vg = AIC3X_MICBIAS_OFF; in aic3x_probe()
1789 aic3x->model = driver_data; in aic3x_probe()
1791 aic3x->gpio_reset = devm_gpiod_get_optional(dev, "reset", in aic3x_probe()
1793 ret = PTR_ERR_OR_ZERO(aic3x->gpio_reset); in aic3x_probe()
1795 if (ret != -EBUSY) in aic3x_probe()
1800 * its reset line. Try to get it non-exclusively, although in aic3x_probe()
1805 aic3x->gpio_reset = devm_gpiod_get(dev, "reset", in aic3x_probe()
1807 ret = PTR_ERR_OR_ZERO(aic3x->gpio_reset); in aic3x_probe()
1811 aic3x->shared_reset = true; in aic3x_probe()
1814 gpiod_set_consumer_name(aic3x->gpio_reset, "tlv320aic3x reset"); in aic3x_probe()
1816 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) in aic3x_probe()
1817 aic3x->supplies[i].supply = aic3x_supply_names[i]; in aic3x_probe()
1819 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(aic3x->supplies), in aic3x_probe()
1820 aic3x->supplies); in aic3x_probe()
1828 if (aic3x->model == AIC3X_MODEL_3007) { in aic3x_probe()
1829 ret = regmap_register_patch(aic3x->regmap, aic3007_class_d, in aic3x_probe()
1848 if (aic3x->gpio_reset && !aic3x->shared_reset) in aic3x_remove()
1849 gpiod_set_value(aic3x->gpio_reset, 1); in aic3x_remove()