Lines Matching +full:0 +full:x0300
14 #define SGTL5000_CHIP_ID 0x0000
15 #define SGTL5000_CHIP_DIG_POWER 0x0002
16 #define SGTL5000_CHIP_CLK_CTRL 0x0004
17 #define SGTL5000_CHIP_I2S_CTRL 0x0006
18 #define SGTL5000_CHIP_SSS_CTRL 0x000a
19 #define SGTL5000_CHIP_ADCDAC_CTRL 0x000e
20 #define SGTL5000_CHIP_DAC_VOL 0x0010
21 #define SGTL5000_CHIP_PAD_STRENGTH 0x0014
22 #define SGTL5000_CHIP_ANA_ADC_CTRL 0x0020
23 #define SGTL5000_CHIP_ANA_HP_CTRL 0x0022
24 #define SGTL5000_CHIP_ANA_CTRL 0x0024
25 #define SGTL5000_CHIP_LINREG_CTRL 0x0026
26 #define SGTL5000_CHIP_REF_CTRL 0x0028
27 #define SGTL5000_CHIP_MIC_CTRL 0x002a
28 #define SGTL5000_CHIP_LINE_OUT_CTRL 0x002c
29 #define SGTL5000_CHIP_LINE_OUT_VOL 0x002e
30 #define SGTL5000_CHIP_ANA_POWER 0x0030
31 #define SGTL5000_CHIP_PLL_CTRL 0x0032
32 #define SGTL5000_CHIP_CLK_TOP_CTRL 0x0034
33 #define SGTL5000_CHIP_ANA_STATUS 0x0036
34 #define SGTL5000_CHIP_SHORT_CTRL 0x003c
35 #define SGTL5000_CHIP_ANA_TEST2 0x003a
36 #define SGTL5000_DAP_CTRL 0x0100
37 #define SGTL5000_DAP_PEQ 0x0102
38 #define SGTL5000_DAP_BASS_ENHANCE 0x0104
39 #define SGTL5000_DAP_BASS_ENHANCE_CTRL 0x0106
40 #define SGTL5000_DAP_AUDIO_EQ 0x0108
41 #define SGTL5000_DAP_SURROUND 0x010a
42 #define SGTL5000_DAP_FLT_COEF_ACCESS 0x010c
43 #define SGTL5000_DAP_COEF_WR_B0_MSB 0x010e
44 #define SGTL5000_DAP_COEF_WR_B0_LSB 0x0110
45 #define SGTL5000_DAP_EQ_BASS_BAND0 0x0116
46 #define SGTL5000_DAP_EQ_BASS_BAND1 0x0118
47 #define SGTL5000_DAP_EQ_BASS_BAND2 0x011a
48 #define SGTL5000_DAP_EQ_BASS_BAND3 0x011c
49 #define SGTL5000_DAP_EQ_BASS_BAND4 0x011e
50 #define SGTL5000_DAP_MAIN_CHAN 0x0120
51 #define SGTL5000_DAP_MIX_CHAN 0x0122
52 #define SGTL5000_DAP_AVC_CTRL 0x0124
53 #define SGTL5000_DAP_AVC_THRESHOLD 0x0126
54 #define SGTL5000_DAP_AVC_ATTACK 0x0128
55 #define SGTL5000_DAP_AVC_DECAY 0x012a
56 #define SGTL5000_DAP_COEF_WR_B1_MSB 0x012c
57 #define SGTL5000_DAP_COEF_WR_B1_LSB 0x012e
58 #define SGTL5000_DAP_COEF_WR_B2_MSB 0x0130
59 #define SGTL5000_DAP_COEF_WR_B2_LSB 0x0132
60 #define SGTL5000_DAP_COEF_WR_A1_MSB 0x0134
61 #define SGTL5000_DAP_COEF_WR_A1_LSB 0x0136
62 #define SGTL5000_DAP_COEF_WR_A2_MSB 0x0138
63 #define SGTL5000_DAP_COEF_WR_A2_LSB 0x013a
72 #define SGTL5000_PARTID_MASK 0xff00
75 #define SGTL5000_PARTID_PART_ID 0xa0
76 #define SGTL5000_REVID_MASK 0x00ff
77 #define SGTL5000_REVID_SHIFT 0
83 #define SGTL5000_DIG_POWER_DEFAULT 0x0000
84 #define SGTL5000_ADC_EN 0x0040
85 #define SGTL5000_DAC_EN 0x0020
86 #define SGTL5000_DAP_POWERUP 0x0010
87 #define SGTL5000_I2S_OUT_POWERUP 0x0002
88 #define SGTL5000_I2S_IN_POWERUP 0x0001
93 #define SGTL5000_CHIP_CLK_CTRL_DEFAULT 0x0008
94 #define SGTL5000_RATE_MODE_MASK 0x0030
97 #define SGTL5000_RATE_MODE_DIV_1 0
101 #define SGTL5000_SYS_FS_MASK 0x000c
104 #define SGTL5000_SYS_FS_32k 0x0
105 #define SGTL5000_SYS_FS_44_1k 0x1
106 #define SGTL5000_SYS_FS_48k 0x2
107 #define SGTL5000_SYS_FS_96k 0x3
108 #define SGTL5000_MCLK_FREQ_MASK 0x0003
109 #define SGTL5000_MCLK_FREQ_SHIFT 0
111 #define SGTL5000_MCLK_FREQ_256FS 0x0
112 #define SGTL5000_MCLK_FREQ_384FS 0x1
113 #define SGTL5000_MCLK_FREQ_512FS 0x2
114 #define SGTL5000_MCLK_FREQ_PLL 0x3
119 #define SGTL5000_I2S_SCLKFREQ_MASK 0x0100
122 #define SGTL5000_I2S_SCLKFREQ_64FS 0x0
123 #define SGTL5000_I2S_SCLKFREQ_32FS 0x1 /* Not for RJ mode */
124 #define SGTL5000_I2S_MASTER 0x0080
125 #define SGTL5000_I2S_SCLK_INV 0x0040
126 #define SGTL5000_I2S_DLEN_MASK 0x0030
129 #define SGTL5000_I2S_DLEN_32 0x0
130 #define SGTL5000_I2S_DLEN_24 0x1
131 #define SGTL5000_I2S_DLEN_20 0x2
132 #define SGTL5000_I2S_DLEN_16 0x3
133 #define SGTL5000_I2S_MODE_MASK 0x000c
136 #define SGTL5000_I2S_MODE_I2S_LJ 0x0
137 #define SGTL5000_I2S_MODE_RJ 0x1
138 #define SGTL5000_I2S_MODE_PCM 0x2
139 #define SGTL5000_I2S_LRALIGN 0x0002
140 #define SGTL5000_I2S_LRPOL 0x0001 /* set for which mode */
145 #define SGTL5000_DAP_MIX_LRSWAP 0x4000
146 #define SGTL5000_DAP_LRSWAP 0x2000
147 #define SGTL5000_DAC_LRSWAP 0x1000
148 #define SGTL5000_I2S_OUT_LRSWAP 0x0400
149 #define SGTL5000_DAP_MIX_SEL_MASK 0x0300
152 #define SGTL5000_DAP_MIX_SEL_ADC 0x0
153 #define SGTL5000_DAP_MIX_SEL_I2S_IN 0x1
154 #define SGTL5000_DAP_SEL_MASK 0x00c0
157 #define SGTL5000_DAP_SEL_ADC 0x0
158 #define SGTL5000_DAP_SEL_I2S_IN 0x1
159 #define SGTL5000_DAC_SEL_MASK 0x0030
162 #define SGTL5000_DAC_SEL_ADC 0x0
163 #define SGTL5000_DAC_SEL_I2S_IN 0x1
164 #define SGTL5000_DAC_SEL_DAP 0x3
165 #define SGTL5000_I2S_OUT_SEL_MASK 0x0003
166 #define SGTL5000_I2S_OUT_SEL_SHIFT 0
168 #define SGTL5000_I2S_OUT_SEL_ADC 0x0
169 #define SGTL5000_I2S_OUT_SEL_I2S_IN 0x1
170 #define SGTL5000_I2S_OUT_SEL_DAP 0x3
175 #define SGTL5000_VOL_BUSY_DAC_RIGHT 0x2000
176 #define SGTL5000_VOL_BUSY_DAC_LEFT 0x1000
177 #define SGTL5000_DAC_VOL_RAMP_EN 0x0200
178 #define SGTL5000_DAC_VOL_RAMP_EXPO 0x0100
179 #define SGTL5000_DAC_MUTE_RIGHT 0x0008
180 #define SGTL5000_DAC_MUTE_LEFT 0x0004
181 #define SGTL5000_ADC_HPF_FREEZE 0x0002
182 #define SGTL5000_ADC_HPF_BYPASS 0x0001
187 #define SGTL5000_DAC_VOL_RIGHT_MASK 0xff00
190 #define SGTL5000_DAC_VOL_LEFT_MASK 0x00ff
191 #define SGTL5000_DAC_VOL_LEFT_SHIFT 0
197 #define SGTL5000_PAD_I2S_LRCLK_MASK 0x0300
200 #define SGTL5000_PAD_I2S_SCLK_MASK 0x00c0
203 #define SGTL5000_PAD_I2S_DOUT_MASK 0x0030
206 #define SGTL5000_PAD_I2C_SDA_MASK 0x000c
209 #define SGTL5000_PAD_I2C_SCL_MASK 0x0003
210 #define SGTL5000_PAD_I2C_SCL_SHIFT 0
216 #define SGTL5000_ADC_VOL_M6DB 0x0100
217 #define SGTL5000_ADC_VOL_RIGHT_MASK 0x00f0
220 #define SGTL5000_ADC_VOL_LEFT_MASK 0x000f
221 #define SGTL5000_ADC_VOL_LEFT_SHIFT 0
227 #define SGTL5000_HP_VOL_RIGHT_MASK 0x7f00
230 #define SGTL5000_HP_VOL_LEFT_MASK 0x007f
231 #define SGTL5000_HP_VOL_LEFT_SHIFT 0
237 #define SGTL5000_CHIP_ANA_CTRL_DEFAULT 0x0133
238 #define SGTL5000_LINE_OUT_MUTE 0x0100
239 #define SGTL5000_HP_SEL_MASK 0x0040
242 #define SGTL5000_HP_SEL_DAC 0x0
243 #define SGTL5000_HP_SEL_LINE_IN 0x1
244 #define SGTL5000_HP_ZCD_EN 0x0020
245 #define SGTL5000_HP_MUTE 0x0010
246 #define SGTL5000_ADC_SEL_MASK 0x0004
249 #define SGTL5000_ADC_SEL_MIC 0x0
250 #define SGTL5000_ADC_SEL_LINE_IN 0x1
251 #define SGTL5000_ADC_ZCD_EN 0x0002
252 #define SGTL5000_ADC_MUTE 0x0001
257 #define SGTL5000_VDDC_MAN_ASSN_MASK 0x0040
260 #define SGTL5000_VDDC_MAN_ASSN_VDDA 0x0
261 #define SGTL5000_VDDC_MAN_ASSN_VDDIO 0x1
262 #define SGTL5000_VDDC_ASSN_OVRD 0x0020
263 #define SGTL5000_LINREG_VDDD_MASK 0x000f
264 #define SGTL5000_LINREG_VDDD_SHIFT 0
270 #define SGTL5000_ANA_GND_MASK 0x01f0
275 #define SGTL5000_BIAS_CTRL_MASK 0x000e
278 #define SGTL5000_SMALL_POP 0x0001
283 #define SGTL5000_BIAS_R_MASK 0x0300
286 #define SGTL5000_BIAS_R_off 0x0
287 #define SGTL5000_BIAS_R_2K 0x1
288 #define SGTL5000_BIAS_R_4k 0x2
289 #define SGTL5000_BIAS_R_8k 0x3
290 #define SGTL5000_BIAS_VOLT_MASK 0x0070
293 #define SGTL5000_MIC_GAIN_MASK 0x0003
294 #define SGTL5000_MIC_GAIN_SHIFT 0
300 #define SGTL5000_LINE_OUT_CURRENT_MASK 0x0f00
303 #define SGTL5000_LINE_OUT_CURRENT_180u 0x0
304 #define SGTL5000_LINE_OUT_CURRENT_270u 0x1
305 #define SGTL5000_LINE_OUT_CURRENT_360u 0x3
306 #define SGTL5000_LINE_OUT_CURRENT_450u 0x7
307 #define SGTL5000_LINE_OUT_CURRENT_540u 0xf
308 #define SGTL5000_LINE_OUT_GND_MASK 0x003f
309 #define SGTL5000_LINE_OUT_GND_SHIFT 0
313 #define SGTL5000_LINE_OUT_GND_MAX 0x23
318 #define SGTL5000_LINE_OUT_VOL_RIGHT_MASK 0x1f00
321 #define SGTL5000_LINE_OUT_VOL_LEFT_MASK 0x001f
322 #define SGTL5000_LINE_OUT_VOL_LEFT_SHIFT 0
328 #define SGTL5000_ANA_POWER_DEFAULT 0x7060
329 #define SGTL5000_DAC_STEREO 0x4000
330 #define SGTL5000_LINREG_SIMPLE_POWERUP 0x2000
331 #define SGTL5000_STARTUP_POWERUP 0x1000
332 #define SGTL5000_VDDC_CHRGPMP_POWERUP 0x0800
333 #define SGTL5000_PLL_POWERUP 0x0400
334 #define SGTL5000_LINEREG_D_POWERUP 0x0200
335 #define SGTL5000_VCOAMP_POWERUP 0x0100
336 #define SGTL5000_VAG_POWERUP 0x0080
337 #define SGTL5000_ADC_STEREO 0x0040
338 #define SGTL5000_REFTOP_POWERUP 0x0020
339 #define SGTL5000_HP_POWERUP 0x0010
340 #define SGTL5000_DAC_POWERUP 0x0008
341 #define SGTL5000_CAPLESS_HP_POWERUP 0x0004
342 #define SGTL5000_ADC_POWERUP 0x0002
343 #define SGTL5000_LINE_OUT_POWERUP 0x0001
348 #define SGTL5000_PLL_INT_DIV_MASK 0xf800
351 #define SGTL5000_PLL_FRAC_DIV_MASK 0x07ff
352 #define SGTL5000_PLL_FRAC_DIV_SHIFT 0
358 #define SGTL5000_INT_OSC_EN 0x0800
359 #define SGTL5000_INPUT_FREQ_DIV2 0x0008
364 #define SGTL5000_HP_LRSHORT 0x0200
365 #define SGTL5000_CAPLESS_SHORT 0x0100
366 #define SGTL5000_PLL_LOCKED 0x0010
371 #define SGTL5000_LVLADJR_MASK 0x7000
374 #define SGTL5000_LVLADJL_MASK 0x0700
377 #define SGTL5000_LVLADJC_MASK 0x0070
380 #define SGTL5000_LR_SHORT_MOD_MASK 0x000c
383 #define SGTL5000_CM_SHORT_MOD_MASK 0x0003
384 #define SGTL5000_CM_SHORT_MOD_SHIFT 0
390 #define SGTL5000_MONO_DAC 0x1000
395 #define SGTL5000_DAP_MIX_EN 0x0010
396 #define SGTL5000_DAP_EN 0x0001
398 #define SGTL5000_SYSCLK 0x00
399 #define SGTL5000_LRCLK 0x01