Lines Matching full:x1
213 #define RT5670_L_MUTE (0x1 << 15)
215 #define RT5670_R_MUTE (0x1 << 7)
225 #define RT5670_ID_5672 (0x1 << 1)
231 #define RT5670_CBJ_JD_HP_EN (0x1 << 9)
232 #define RT5670_CBJ_JD_MIC_EN (0x1 << 8)
233 #define RT5670_CBJ_BST1_EN (0x1 << 2)
236 #define RT5670_CBJ_MN_JD (0x1 << 12)
237 #define RT5670_CAPLESS_EN (0x1 << 11)
238 #define RT5670_CBJ_DET_MODE (0x1 << 7)
245 #define RT5670_IN_DF1 (0x1 << 7)
247 #define RT5670_IN_DF2 (0x1 << 6)
251 #define RT5670_INL_SEL_MASK (0x1 << 15)
254 #define RT5670_INL_SEL_MONOP (0x1 << 15)
257 #define RT5670_INR_SEL_MASK (0x1 << 7)
260 #define RT5670_INR_SEL_MONON (0x1 << 7)
267 #define RT5670_M_ST_DACR2 (0x1 << 8)
269 #define RT5670_M_ST_DACL2 (0x1 << 7)
271 #define RT5670_ST_EN (0x1 << 6)
287 #define RT5670_M_DAC_L2_VOL (0x1 << 13)
289 #define RT5670_M_DAC_R2_VOL (0x1 << 12)
323 #define RT5670_STO2_ADC_SRC_MASK (0x1 << 15)
327 #define RT5670_M_ADC_L1 (0x1 << 14)
329 #define RT5670_M_ADC_L2 (0x1 << 13)
331 #define RT5670_ADC_1_SRC_MASK (0x1 << 12)
333 #define RT5670_ADC_1_SRC_ADC (0x1 << 12)
335 #define RT5670_ADC_2_SRC_MASK (0x1 << 11)
337 #define RT5670_ADC_SRC_MASK (0x1 << 10)
341 #define RT5670_M_ADC_R1 (0x1 << 6)
343 #define RT5670_M_ADC_R2 (0x1 << 5)
345 #define RT5670_DMIC3_SRC_MASK (0x1 << 1)
349 #define RT5670_M_MONO_ADC_L1 (0x1 << 14)
351 #define RT5670_M_MONO_ADC_L2 (0x1 << 13)
353 #define RT5670_MONO_ADC_L1_SRC_MASK (0x1 << 12)
356 #define RT5670_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
357 #define RT5670_MONO_ADC_L2_SRC_MASK (0x1 << 11)
359 #define RT5670_MONO_ADC_L_SRC_MASK (0x1 << 10)
363 #define RT5670_M_MONO_ADC_R1 (0x1 << 6)
365 #define RT5670_M_MONO_ADC_R2 (0x1 << 5)
367 #define RT5670_MONO_ADC_R1_SRC_MASK (0x1 << 4)
369 #define RT5670_MONO_ADC_R1_SRC_ADCR (0x1 << 4)
371 #define RT5670_MONO_ADC_R2_SRC_MASK (0x1 << 3)
377 #define RT5670_M_ADCMIX_L (0x1 << 15)
379 #define RT5670_M_DAC1_L (0x1 << 14)
384 #define RT5670_DAC1_R_SEL_IF2 (0x1 << 10)
390 #define RT5670_DAC1_L_SEL_IF2 (0x1 << 8)
393 #define RT5670_M_ADCMIX_R (0x1 << 7)
395 #define RT5670_M_DAC1_R (0x1 << 6)
399 #define RT5670_M_DAC_L1 (0x1 << 14)
401 #define RT5670_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
403 #define RT5670_M_DAC_L2 (0x1 << 12)
405 #define RT5670_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
407 #define RT5670_M_DAC_R1_STO_L (0x1 << 9)
409 #define RT5670_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
411 #define RT5670_M_DAC_R1 (0x1 << 6)
413 #define RT5670_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
415 #define RT5670_M_DAC_R2 (0x1 << 4)
417 #define RT5670_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
419 #define RT5670_M_DAC_L1_STO_R (0x1 << 1)
421 #define RT5670_DAC_L1_STO_R_VOL_MASK (0x1)
425 #define RT5670_M_DAC_L1_MONO_L (0x1 << 14)
427 #define RT5670_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
429 #define RT5670_M_DAC_L2_MONO_L (0x1 << 12)
431 #define RT5670_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
433 #define RT5670_M_DAC_R2_MONO_L (0x1 << 10)
435 #define RT5670_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)
437 #define RT5670_M_DAC_R1_MONO_R (0x1 << 6)
439 #define RT5670_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)
441 #define RT5670_M_DAC_R2_MONO_R (0x1 << 4)
443 #define RT5670_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)
445 #define RT5670_M_DAC_L2_MONO_R (0x1 << 2)
447 #define RT5670_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)
451 #define RT5670_M_STO_L_DAC_L (0x1 << 15)
453 #define RT5670_STO_L_DAC_L_VOL_MASK (0x1 << 14)
455 #define RT5670_M_DAC_L2_DAC_L (0x1 << 13)
457 #define RT5670_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
459 #define RT5670_M_STO_R_DAC_R (0x1 << 11)
461 #define RT5670_STO_R_DAC_R_VOL_MASK (0x1 << 10)
463 #define RT5670_M_DAC_R2_DAC_R (0x1 << 9)
465 #define RT5670_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
467 #define RT5670_M_DAC_R2_DAC_L (0x1 << 7)
469 #define RT5670_DAC_R2_DAC_L_VOL_MASK (0x1 << 6)
471 #define RT5670_M_DAC_L2_DAC_R (0x1 << 5)
473 #define RT5670_DAC_L2_DAC_R_VOL_MASK (0x1 << 4)
482 #define RT5670_RXDP_SRC_DIV2 (0x1 << 11)
487 #define RT5670_TXDP_SRC_DIV2 (0x1 << 4)
491 #define RT5670_DSP_UL_SEL (0x1 << 1)
493 #define RT5670_DSP_DL_SEL 0x1
503 #define RT5670_IF1_ADC2_IN_SEL (0x1 << 15)
517 #define RT5670_PDM1_L_MASK (0x1 << 15)
519 #define RT5670_M_PDM1_L (0x1 << 14)
521 #define RT5670_PDM1_R_MASK (0x1 << 13)
523 #define RT5670_M_PDM1_R (0x1 << 12)
525 #define RT5670_PDM2_L_MASK (0x1 << 11)
527 #define RT5670_M_PDM2_L (0x1 << 10)
529 #define RT5670_PDM2_R_MASK (0x1 << 9)
531 #define RT5670_M_PDM2_R (0x1 << 8)
533 #define RT5670_PDM2_BUSY (0x1 << 7)
534 #define RT5670_PDM1_BUSY (0x1 << 6)
535 #define RT5670_PDM_PATTERN (0x1 << 5)
536 #define RT5670_PDM_GAIN (0x1 << 4)
554 #define RT5670_M_IN_L_RM_L (0x1 << 5)
556 #define RT5670_M_BST2_RM_L (0x1 << 3)
558 #define RT5670_M_BST1_RM_L (0x1 << 1)
576 #define RT5670_M_IN_R_RM_R (0x1 << 5)
578 #define RT5670_M_BST2_RM_R (0x1 << 3)
580 #define RT5670_M_BST1_RM_R (0x1 << 1)
584 #define RT5670_M_DAC2_HM (0x1 << 15)
586 #define RT5670_M_HPVOL_HM (0x1 << 14)
588 #define RT5670_M_DAC1_HM (0x1 << 13)
590 #define RT5670_G_HPOMIX_MASK (0x1 << 12)
592 #define RT5670_M_INR1_HMR (0x1 << 3)
594 #define RT5670_M_DACR1_HMR (0x1 << 2)
596 #define RT5670_M_INL1_HML (0x1 << 1)
598 #define RT5670_M_DACL1_HML (0x1)
602 #define RT5670_M_DAC_R2_MA (0x1 << 15)
604 #define RT5670_M_DAC_L2_MA (0x1 << 14)
606 #define RT5670_M_OV_R_MM (0x1 << 13)
608 #define RT5670_M_OV_L_MM (0x1 << 12)
610 #define RT5670_G_MONOMIX_MASK (0x1 << 10)
612 #define RT5670_M_DAC_R2_MM (0x1 << 9)
614 #define RT5670_M_DAC_L2_MM (0x1 << 8)
616 #define RT5670_M_BST4_MM (0x1 << 7)
640 #define RT5670_M_BST1_OM_L (0x1 << 5)
642 #define RT5670_M_IN_L_OM_L (0x1 << 4)
644 #define RT5670_M_DAC_L2_OM_L (0x1 << 1)
646 #define RT5670_M_DAC_L1_OM_L (0x1)
670 #define RT5670_M_BST2_OM_R (0x1 << 6)
672 #define RT5670_M_IN_R_OM_R (0x1 << 4)
674 #define RT5670_M_DAC_R2_OM_R (0x1 << 1)
676 #define RT5670_M_DAC_R1_OM_R (0x1)
680 #define RT5670_M_DAC_L1_LM (0x1 << 15)
682 #define RT5670_M_DAC_R1_LM (0x1 << 14)
684 #define RT5670_M_OV_L_LM (0x1 << 13)
686 #define RT5670_M_OV_R_LM (0x1 << 12)
688 #define RT5670_G_LOUTMIX_MASK (0x1 << 11)
692 #define RT5670_PWR_I2S1 (0x1 << 15)
694 #define RT5670_PWR_I2S2 (0x1 << 14)
696 #define RT5670_PWR_DAC_L1 (0x1 << 12)
698 #define RT5670_PWR_DAC_R1 (0x1 << 11)
700 #define RT5670_PWR_DAC_L2 (0x1 << 7)
702 #define RT5670_PWR_DAC_R2 (0x1 << 6)
704 #define RT5670_PWR_ADC_L (0x1 << 2)
706 #define RT5670_PWR_ADC_R (0x1 << 1)
708 #define RT5670_PWR_CLS_D (0x1)
712 #define RT5670_PWR_ADC_S1F (0x1 << 15)
714 #define RT5670_PWR_ADC_MF_L (0x1 << 14)
716 #define RT5670_PWR_ADC_MF_R (0x1 << 13)
718 #define RT5670_PWR_I2S_DSP (0x1 << 12)
720 #define RT5670_PWR_DAC_S1F (0x1 << 11)
722 #define RT5670_PWR_DAC_MF_L (0x1 << 10)
724 #define RT5670_PWR_DAC_MF_R (0x1 << 9)
726 #define RT5670_PWR_ADC_S2F (0x1 << 8)
728 #define RT5670_PWR_PDM1 (0x1 << 7)
730 #define RT5670_PWR_PDM2 (0x1 << 6)
734 #define RT5670_PWR_VREF1 (0x1 << 15)
736 #define RT5670_PWR_FV1 (0x1 << 14)
738 #define RT5670_PWR_MB (0x1 << 13)
740 #define RT5670_PWR_LM (0x1 << 12)
742 #define RT5670_PWR_BG (0x1 << 11)
744 #define RT5670_PWR_HP_L (0x1 << 7)
746 #define RT5670_PWR_HP_R (0x1 << 6)
748 #define RT5670_PWR_HA (0x1 << 5)
750 #define RT5670_PWR_VREF2 (0x1 << 4)
752 #define RT5670_PWR_FV2 (0x1 << 3)
758 #define RT5670_PWR_BST1 (0x1 << 15)
760 #define RT5670_PWR_BST2 (0x1 << 13)
762 #define RT5670_PWR_MB1 (0x1 << 11)
764 #define RT5670_PWR_MB2 (0x1 << 10)
766 #define RT5670_PWR_PLL (0x1 << 9)
768 #define RT5670_PWR_BST1_P (0x1 << 6)
770 #define RT5670_PWR_BST2_P (0x1 << 4)
772 #define RT5670_PWR_JD1 (0x1 << 2)
774 #define RT5670_PWR_JD (0x1 << 1)
778 #define RT5670_PWR_OM_L (0x1 << 15)
780 #define RT5670_PWR_OM_R (0x1 << 14)
782 #define RT5670_PWR_RM_L (0x1 << 11)
784 #define RT5670_PWR_RM_R (0x1 << 10)
788 #define RT5670_PWR_HV_L (0x1 << 11)
790 #define RT5670_PWR_HV_R (0x1 << 10)
792 #define RT5670_PWR_IN_L (0x1 << 9)
794 #define RT5670_PWR_IN_R (0x1 << 8)
796 #define RT5670_PWR_MIC_DET (0x1 << 5)
800 #define RT5670_I2S_MS_MASK (0x1 << 15)
803 #define RT5670_I2S_MS_S (0x1 << 15)
809 #define RT5670_I2S_O_CP_U_LAW (0x1 << 10)
814 #define RT5670_I2S_I_CP_U_LAW (0x1 << 8)
816 #define RT5670_I2S_BP_MASK (0x1 << 7)
819 #define RT5670_I2S_BP_INV (0x1 << 7)
823 #define RT5670_I2S_DL_20 (0x1 << 2)
829 #define RT5670_I2S_DF_LEFT (0x1)
834 #define RT5670_I2S2_SDI_MASK (0x1 << 6)
837 #define RT5670_I2S2_SDI_I2S2 (0x1 << 6)
840 #define RT5670_I2S_BCLK_MS1_MASK (0x1 << 15)
843 #define RT5670_I2S_BCLK_MS1_64 (0x1 << 15)
847 #define RT5670_I2S_PD1_2 (0x1 << 12)
854 #define RT5670_I2S_BCLK_MS2_MASK (0x1 << 11)
857 #define RT5670_I2S_BCLK_MS2_64 (0x1 << 11)
861 #define RT5670_I2S_PD2_2 (0x1 << 8)
868 #define RT5670_I2S_BCLK_MS3_MASK (0x1 << 7)
871 #define RT5670_I2S_BCLK_MS3_64 (0x1 << 7)
875 #define RT5670_I2S_PD3_2 (0x1 << 4)
885 #define RT5670_DAC_OSR_64 (0x1 << 2)
891 #define RT5670_ADC_OSR_64 (0x1)
899 #define RT5670_DAC_L_OSR_64 (0x1 << 14)
905 #define RT5670_ADC_R_OSR_64 (0x1 << 12)
908 #define RT5670_DAHPF_EN (0x1 << 11)
910 #define RT5670_ADHPF_EN (0x1 << 10)
914 #define RT5670_DMIC_1_EN_MASK (0x1 << 15)
917 #define RT5670_DMIC_1_EN (0x1 << 15)
918 #define RT5670_DMIC_2_EN_MASK (0x1 << 14)
921 #define RT5670_DMIC_2_EN (0x1 << 14)
922 #define RT5670_DMIC_1L_LH_MASK (0x1 << 13)
925 #define RT5670_DMIC_1L_LH_RISING (0x1 << 13)
926 #define RT5670_DMIC_1R_LH_MASK (0x1 << 12)
929 #define RT5670_DMIC_1R_LH_RISING (0x1 << 12)
930 #define RT5670_DMIC_2_DP_MASK (0x1 << 10)
933 #define RT5670_DMIC_2_DP_IN3N (0x1 << 10)
934 #define RT5670_DMIC_2L_LH_MASK (0x1 << 9)
937 #define RT5670_DMIC_2L_LH_RISING (0x1 << 9)
938 #define RT5670_DMIC_2R_LH_MASK (0x1 << 8)
941 #define RT5670_DMIC_2R_LH_RISING (0x1 << 8)
944 #define RT5670_DMIC_3_EN_MASK (0x1 << 4)
947 #define RT5670_DMIC_3_EN (0x1 << 4)
951 #define RT5670_DMIC_1_DP_IN2P (0x1 << 0)
958 #define RT5670_DMIC_3_DP_GPIO10 (0x1 << 6)
965 #define RT5670_SCLK_SRC_PLL1 (0x1 << 14)
970 #define RT5670_PLL1_SRC_BCLK1 (0x1 << 11)
973 #define RT5670_PLL1_PD_MASK (0x1 << 3)
976 #define RT5670_PLL1_PD_2 (0x1 << 3)
992 #define RT5670_PLL_M_BP (0x1 << 11)
996 #define RT5670_STO_T_MASK (0x1 << 15)
999 #define RT5670_STO_T_LRCK1 (0x1 << 15)
1000 #define RT5670_M1_T_MASK (0x1 << 14)
1003 #define RT5670_M1_T_I2S2_D3 (0x1 << 14)
1004 #define RT5670_I2S2_F_MASK (0x1 << 12)
1007 #define RT5670_I2S2_F_I2S1_TCLK (0x1 << 12)
1008 #define RT5670_DMIC_1_M_MASK (0x1 << 9)
1011 #define RT5670_DMIC_1_M_ASYN (0x1 << 9)
1012 #define RT5670_DMIC_2_M_MASK (0x1 << 8)
1015 #define RT5670_DMIC_2_M_ASYN (0x1 << 8)
1019 #define RT5670_CLK_SEL_I2S1_ASRC (0x1)
1052 #define RT5670_HP_OVCD_MASK (0x1 << 10)
1055 #define RT5670_HP_OVCD_EN (0x1 << 10)
1059 #define RT5670_HP_OC_TH_105 (0x1 << 8)
1064 #define RT5670_CLSD_OC_MASK (0x1 << 9)
1067 #define RT5670_CLSD_OC_PD (0x1 << 9)
1068 #define RT5670_AUTO_PD_MASK (0x1 << 8)
1071 #define RT5670_AUTO_PD_EN (0x1 << 8)
1078 #define RT5670_CLSD_OM_MASK (0x1 << 11)
1081 #define RT5670_CLSD_OM_STO (0x1 << 11)
1082 #define RT5670_CLSD_SCH_MASK (0x1 << 10)
1085 #define RT5670_CLSD_SCH_S (0x1 << 10)
1088 #define RT5670_SMT_TRIG_MASK (0x1 << 15)
1091 #define RT5670_SMT_TRIG_EN (0x1 << 15)
1092 #define RT5670_HP_L_SMT_MASK (0x1 << 9)
1095 #define RT5670_HP_L_SMT_EN (0x1 << 9)
1096 #define RT5670_HP_R_SMT_MASK (0x1 << 8)
1099 #define RT5670_HP_R_SMT_EN (0x1 << 8)
1100 #define RT5670_HP_CD_PD_MASK (0x1 << 7)
1103 #define RT5670_HP_CD_PD_EN (0x1 << 7)
1104 #define RT5670_RSTN_MASK (0x1 << 6)
1107 #define RT5670_RSTN_EN (0x1 << 6)
1108 #define RT5670_RSTP_MASK (0x1 << 5)
1111 #define RT5670_RSTP_EN (0x1 << 5)
1112 #define RT5670_HP_CO_MASK (0x1 << 4)
1115 #define RT5670_HP_CO_EN (0x1 << 4)
1116 #define RT5670_HP_CP_MASK (0x1 << 3)
1119 #define RT5670_HP_CP_PU (0x1 << 3)
1120 #define RT5670_HP_SG_MASK (0x1 << 2)
1123 #define RT5670_HP_SG_EN (0x1 << 2)
1124 #define RT5670_HP_DP_MASK (0x1 << 1)
1127 #define RT5670_HP_DP_PU (0x1 << 1)
1128 #define RT5670_HP_CB_MASK (0x1)
1131 #define RT5670_HP_CB_PU (0x1)
1134 #define RT5670_DEPOP_MASK (0x1 << 13)
1137 #define RT5670_DEPOP_MAN (0x1 << 13)
1138 #define RT5670_RAMP_MASK (0x1 << 12)
1141 #define RT5670_RAMP_EN (0x1 << 12)
1142 #define RT5670_BPS_MASK (0x1 << 11)
1145 #define RT5670_BPS_EN (0x1 << 11)
1146 #define RT5670_FAST_UPDN_MASK (0x1 << 10)
1149 #define RT5670_FAST_UPDN_EN (0x1 << 10)
1153 #define RT5670_MRES_25MO (0x1 << 8)
1156 #define RT5670_VLO_MASK (0x1 << 7)
1159 #define RT5670_VLO_32V (0x1 << 7)
1160 #define RT5670_DIG_DP_MASK (0x1 << 6)
1163 #define RT5670_DIG_DP_EN (0x1 << 6)
1186 #define RT5670_OSW_L_MASK (0x1 << 11)
1189 #define RT5670_OSW_L_EN (0x1 << 11)
1190 #define RT5670_OSW_R_MASK (0x1 << 10)
1193 #define RT5670_OSW_R_EN (0x1 << 10)
1197 #define RT5670_PM_HP_MV (0x1 << 8)
1202 #define RT5670_IB_HP_25IL (0x1 << 6)
1207 #define RT5670_PVDD_DET_MASK (0x1 << 15)
1210 #define RT5670_PVDD_DET_EN (0x1 << 15)
1211 #define RT5670_SPK_AG_MASK (0x1 << 14)
1214 #define RT5670_SPK_AG_EN (0x1 << 14)
1217 #define RT5670_MIC1_BS_MASK (0x1 << 15)
1220 #define RT5670_MIC1_BS_75AV (0x1 << 15)
1221 #define RT5670_MIC2_BS_MASK (0x1 << 14)
1224 #define RT5670_MIC2_BS_75AV (0x1 << 14)
1225 #define RT5670_MIC1_CLK_MASK (0x1 << 13)
1228 #define RT5670_MIC1_CLK_EN (0x1 << 13)
1229 #define RT5670_MIC2_CLK_MASK (0x1 << 12)
1232 #define RT5670_MIC2_CLK_EN (0x1 << 12)
1233 #define RT5670_MIC1_OVCD_MASK (0x1 << 11)
1236 #define RT5670_MIC1_OVCD_EN (0x1 << 11)
1240 #define RT5670_MIC1_OVTH_1500UA (0x1 << 9)
1242 #define RT5670_MIC2_OVCD_MASK (0x1 << 8)
1245 #define RT5670_MIC2_OVCD_EN (0x1 << 8)
1249 #define RT5670_MIC2_OVTH_1500UA (0x1 << 6)
1251 #define RT5670_PWR_MB_MASK (0x1 << 5)
1254 #define RT5670_PWR_MB_PU (0x1 << 5)
1255 #define RT5670_PWR_CLK25M_MASK (0x1 << 4)
1258 #define RT5670_PWR_CLK25M_PU (0x1 << 4)
1263 #define RT5670_JD1_MODE_1 (0x1 << 0)
1271 #define RT5670_EQ_SRC_MASK (0x1 << 15)
1274 #define RT5670_EQ_SRC_ADC (0x1 << 15)
1275 #define RT5670_EQ_UPD (0x1 << 14)
1277 #define RT5670_EQ_CD_MASK (0x1 << 13)
1280 #define RT5670_EQ_CD_EN (0x1 << 13)
1284 #define RT5670_EQ_DITH_LSB (0x1 << 8)
1289 #define RT5670_EQ_HPF1_M_MASK (0x1 << 8)
1292 #define RT5670_EQ_HPF1_M_1ST (0x1 << 8)
1293 #define RT5670_EQ_LPF1_M_MASK (0x1 << 7)
1296 #define RT5670_EQ_LPF1_M_1ST (0x1 << 7)
1297 #define RT5670_EQ_HPF2_MASK (0x1 << 6)
1300 #define RT5670_EQ_HPF2_EN (0x1 << 6)
1301 #define RT5670_EQ_HPF1_MASK (0x1 << 5)
1304 #define RT5670_EQ_HPF1_EN (0x1 << 5)
1305 #define RT5670_EQ_BPF4_MASK (0x1 << 4)
1308 #define RT5670_EQ_BPF4_EN (0x1 << 4)
1309 #define RT5670_EQ_BPF3_MASK (0x1 << 3)
1312 #define RT5670_EQ_BPF3_EN (0x1 << 3)
1313 #define RT5670_EQ_BPF2_MASK (0x1 << 2)
1316 #define RT5670_EQ_BPF2_EN (0x1 << 2)
1317 #define RT5670_EQ_BPF1_MASK (0x1 << 1)
1320 #define RT5670_EQ_BPF1_EN (0x1 << 1)
1321 #define RT5670_EQ_LPF_MASK (0x1)
1324 #define RT5670_EQ_LPF_EN (0x1)
1328 #define RT5670_MT_MASK (0x1 << 15)
1331 #define RT5670_MT_EN (0x1 << 15)
1334 #define RT5670_DRC_AGC_P_MASK (0x1 << 15)
1337 #define RT5670_DRC_AGC_P_ADC (0x1 << 15)
1338 #define RT5670_DRC_AGC_MASK (0x1 << 14)
1341 #define RT5670_DRC_AGC_EN (0x1 << 14)
1342 #define RT5670_DRC_AGC_UPD (0x1 << 13)
1348 #define RT5670_DRC_AGC_R_48K (0x1 << 5)
1360 #define RT5670_DRC_AGC_CP_MASK (0x1 << 7)
1363 #define RT5670_DRC_AGC_CP_EN (0x1 << 7)
1367 #define RT5670_DRC_AGC_CPR_1_2 (0x1 << 5)
1378 #define RT5670_DRC_AGC_NG_MASK (0x1 << 6)
1381 #define RT5670_DRC_AGC_NG_EN (0x1 << 6)
1382 #define RT5670_DRC_AGC_NGH_MASK (0x1 << 5)
1385 #define RT5670_DRC_AGC_NGH_EN (0x1 << 5)
1393 #define RT5670_JD_GPIO1 (0x1 << 13)
1399 #define RT5670_JD_HP_MASK (0x1 << 11)
1402 #define RT5670_JD_HP_EN (0x1 << 11)
1403 #define RT5670_JD_HP_TRG_MASK (0x1 << 10)
1406 #define RT5670_JD_HP_TRG_HI (0x1 << 10)
1407 #define RT5670_JD_SPL_MASK (0x1 << 9)
1410 #define RT5670_JD_SPL_EN (0x1 << 9)
1411 #define RT5670_JD_SPL_TRG_MASK (0x1 << 8)
1414 #define RT5670_JD_SPL_TRG_HI (0x1 << 8)
1415 #define RT5670_JD_SPR_MASK (0x1 << 7)
1418 #define RT5670_JD_SPR_EN (0x1 << 7)
1419 #define RT5670_JD_SPR_TRG_MASK (0x1 << 6)
1422 #define RT5670_JD_SPR_TRG_HI (0x1 << 6)
1423 #define RT5670_JD_MO_MASK (0x1 << 5)
1426 #define RT5670_JD_MO_EN (0x1 << 5)
1427 #define RT5670_JD_MO_TRG_MASK (0x1 << 4)
1430 #define RT5670_JD_MO_TRG_HI (0x1 << 4)
1431 #define RT5670_JD_LO_MASK (0x1 << 3)
1434 #define RT5670_JD_LO_EN (0x1 << 3)
1435 #define RT5670_JD_LO_TRG_MASK (0x1 << 2)
1438 #define RT5670_JD_LO_TRG_HI (0x1 << 2)
1439 #define RT5670_JD1_IN4P_MASK (0x1 << 1)
1442 #define RT5670_JD1_IN4P_EN (0x1 << 1)
1443 #define RT5670_JD2_IN4N_MASK (0x1)
1446 #define RT5670_JD2_IN4N_EN (0x1)
1449 #define RT5670_IRQ_JD_MASK (0x1 << 15)
1452 #define RT5670_IRQ_JD_NOR (0x1 << 15)
1453 #define RT5670_IRQ_OT_MASK (0x1 << 14)
1456 #define RT5670_IRQ_OT_NOR (0x1 << 14)
1457 #define RT5670_JD_STKY_MASK (0x1 << 13)
1460 #define RT5670_JD_STKY_EN (0x1 << 13)
1461 #define RT5670_OT_STKY_MASK (0x1 << 12)
1464 #define RT5670_OT_STKY_EN (0x1 << 12)
1465 #define RT5670_JD_P_MASK (0x1 << 11)
1468 #define RT5670_JD_P_INV (0x1 << 11)
1469 #define RT5670_OT_P_MASK (0x1 << 10)
1472 #define RT5670_OT_P_INV (0x1 << 10)
1473 #define RT5670_JD1_1_EN_MASK (0x1 << 9)
1476 #define RT5670_JD1_1_EN (0x1 << 9)
1479 #define RT5670_IRQ_MB1_OC_MASK (0x1 << 15)
1482 #define RT5670_IRQ_MB1_OC_NOR (0x1 << 15)
1483 #define RT5670_IRQ_MB2_OC_MASK (0x1 << 14)
1486 #define RT5670_IRQ_MB2_OC_NOR (0x1 << 14)
1487 #define RT5670_MB1_OC_STKY_MASK (0x1 << 11)
1490 #define RT5670_MB1_OC_STKY_EN (0x1 << 11)
1491 #define RT5670_MB2_OC_STKY_MASK (0x1 << 10)
1494 #define RT5670_MB2_OC_STKY_EN (0x1 << 10)
1495 #define RT5670_MB1_OC_P_MASK (0x1 << 7)
1498 #define RT5670_MB1_OC_P_INV (0x1 << 7)
1499 #define RT5670_MB2_OC_P_MASK (0x1 << 6)
1502 #define RT5670_MB2_OC_P_INV (0x1 << 6)
1503 #define RT5670_MB1_OC_CLR (0x1 << 3)
1505 #define RT5670_MB2_OC_CLR (0x1 << 2)
1509 #define RT5670_GP1_PIN_MASK (0x1 << 15)
1512 #define RT5670_GP1_PIN_IRQ (0x1 << 15)
1513 #define RT5670_GP2_PIN_MASK (0x1 << 14)
1516 #define RT5670_GP2_PIN_DMIC1_SCL (0x1 << 14)
1520 #define RT5670_GP3_PIN_DMIC1_SDA (0x1 << 12)
1522 #define RT5670_GP4_PIN_MASK (0x1 << 11)
1525 #define RT5670_GP4_PIN_DMIC2_SDA (0x1 << 11)
1526 #define RT5670_DP_SIG_MASK (0x1 << 10)
1529 #define RT5670_DP_SIG_AP (0x1 << 10)
1530 #define RT5670_GPIO_M_MASK (0x1 << 9)
1533 #define RT5670_GPIO_M_PH (0x1 << 9)
1534 #define RT5670_I2S2_PIN_MASK (0x1 << 8)
1537 #define RT5670_I2S2_PIN_GPIO (0x1 << 8)
1538 #define RT5670_GP5_PIN_MASK (0x1 << 7)
1541 #define RT5670_GP5_PIN_DMIC3_SDA (0x1 << 7)
1542 #define RT5670_GP6_PIN_MASK (0x1 << 6)
1545 #define RT5670_GP6_PIN_DMIC1_SDA (0x1 << 6)
1549 #define RT5670_GP7_PIN_DMIC1_SDA (0x1 << 4)
1551 #define RT5670_GP8_PIN_MASK (0x1 << 3)
1554 #define RT5670_GP8_PIN_DMIC2_SDA (0x1 << 3)
1555 #define RT5670_GP9_PIN_MASK (0x1 << 2)
1558 #define RT5670_GP9_PIN_DMIC3_SDA (0x1 << 2)
1562 #define RT5670_GP10_PIN_DMIC3_SDA (0x1)
1566 #define RT5670_GP4_PF_MASK (0x1 << 11)
1569 #define RT5670_GP4_PF_OUT (0x1 << 11)
1570 #define RT5670_GP4_OUT_MASK (0x1 << 10)
1573 #define RT5670_GP4_OUT_HI (0x1 << 10)
1574 #define RT5670_GP4_P_MASK (0x1 << 9)
1577 #define RT5670_GP4_P_INV (0x1 << 9)
1578 #define RT5670_GP3_PF_MASK (0x1 << 8)
1581 #define RT5670_GP3_PF_OUT (0x1 << 8)
1582 #define RT5670_GP3_OUT_MASK (0x1 << 7)
1585 #define RT5670_GP3_OUT_HI (0x1 << 7)
1586 #define RT5670_GP3_P_MASK (0x1 << 6)
1589 #define RT5670_GP3_P_INV (0x1 << 6)
1590 #define RT5670_GP2_PF_MASK (0x1 << 5)
1593 #define RT5670_GP2_PF_OUT (0x1 << 5)
1594 #define RT5670_GP2_OUT_MASK (0x1 << 4)
1597 #define RT5670_GP2_OUT_HI (0x1 << 4)
1598 #define RT5670_GP2_P_MASK (0x1 << 3)
1601 #define RT5670_GP2_P_INV (0x1 << 3)
1602 #define RT5670_GP1_PF_MASK (0x1 << 2)
1605 #define RT5670_GP1_PF_OUT (0x1 << 2)
1606 #define RT5670_GP1_OUT_MASK (0x1 << 1)
1609 #define RT5670_GP1_OUT_HI (0x1 << 1)
1610 #define RT5670_GP1_P_MASK (0x1)
1613 #define RT5670_GP1_P_INV (0x1)
1620 #define RT5670_SCB_SWAP_MASK (0x1 << 15)
1623 #define RT5670_SCB_SWAP_EN (0x1 << 15)
1624 #define RT5670_SCB_MASK (0x1 << 14)
1627 #define RT5670_SCB_EN (0x1 << 14)
1630 #define RT5670_BB_MASK (0x1 << 15)
1633 #define RT5670_BB_EN (0x1 << 15)
1637 #define RT5670_BB_CT_B (0x1 << 12)
1640 #define RT5670_M_BB_L_MASK (0x1 << 9)
1642 #define RT5670_M_BB_R_MASK (0x1 << 8)
1644 #define RT5670_M_BB_HPF_L_MASK (0x1 << 7)
1646 #define RT5670_M_BB_HPF_R_MASK (0x1 << 6)
1652 #define RT5670_M_MP3_L_MASK (0x1 << 15)
1654 #define RT5670_M_MP3_R_MASK (0x1 << 14)
1656 #define RT5670_M_MP3_MASK (0x1 << 13)
1659 #define RT5670_M_MP3_EN (0x1 << 13)
1662 #define RT5670_MP3_HLP_MASK (0x1 << 7)
1665 #define RT5670_MP3_HLP_EN (0x1 << 7)
1666 #define RT5670_M_MP3_ORG_L_MASK (0x1 << 6)
1668 #define RT5670_M_MP3_ORG_R_MASK (0x1 << 5)
1672 #define RT5670_MP3_WT_MASK (0x1 << 13)
1675 #define RT5670_MP3_WT_1_2 (0x1 << 13)
1682 #define RT5670_3D_CF_MASK (0x1 << 15)
1685 #define RT5670_3D_CF_EN (0x1 << 15)
1686 #define RT5670_3D_HP_MASK (0x1 << 14)
1689 #define RT5670_3D_HP_EN (0x1 << 14)
1690 #define RT5670_3D_BT_MASK (0x1 << 13)
1693 #define RT5670_3D_BT_EN (0x1 << 13)
1696 #define RT5670_3D_HP_M_MASK (0x1 << 10)
1699 #define RT5670_3D_HP_M_FRO (0x1 << 10)
1700 #define RT5670_M_3D_HRTF_MASK (0x1 << 9)
1702 #define RT5670_M_3D_D2H_MASK (0x1 << 8)
1704 #define RT5670_M_3D_D2R_MASK (0x1 << 7)
1706 #define RT5670_M_3D_REVB_MASK (0x1 << 6)
1710 #define RT5670_2ND_HPF_MASK (0x1 << 15)
1713 #define RT5670_2ND_HPF_EN (0x1 << 15)
1716 #define RT5670_1ST_HPF_MASK (0x1 << 11)
1719 #define RT5670_1ST_HPF_EN (0x1 << 11)
1727 #define RT5670_ZD_F_ZC_IM (0x1 << 4)
1732 #define RT5670_SI_DAC_MASK (0x1 << 11)
1735 #define RT5670_SI_DAC_TEST (0x1 << 11)
1736 #define RT5670_DC_CAL_M_MASK (0x1 << 10)
1739 #define RT5670_DC_CAL_M_NOR (0x1 << 10)
1740 #define RT5670_DC_CAL_MASK (0x1 << 9)
1743 #define RT5670_DC_CAL_EN (0x1 << 9)
1746 #define RT5670_HPD_PS_MASK (0x1 << 5)
1749 #define RT5670_HPD_PS_EN (0x1 << 5)
1750 #define RT5670_CAL_M_MASK (0x1 << 4)
1753 #define RT5670_CAL_M_CAL (0x1 << 4)
1754 #define RT5670_CAL_MASK (0x1 << 3)
1757 #define RT5670_CAL_EN (0x1 << 3)
1758 #define RT5670_CAL_TEST_MASK (0x1 << 2)
1761 #define RT5670_CAL_TEST_EN (0x1 << 2)
1765 #define RT5670_CAL_P_CAL (0x1)
1769 #define RT5670_SV_MASK (0x1 << 15)
1772 #define RT5670_SV_EN (0x1 << 15)
1773 #define RT5670_SPO_SV_MASK (0x1 << 14)
1776 #define RT5670_SPO_SV_EN (0x1 << 14)
1777 #define RT5670_OUT_SV_MASK (0x1 << 13)
1780 #define RT5670_OUT_SV_EN (0x1 << 13)
1781 #define RT5670_HP_SV_MASK (0x1 << 12)
1784 #define RT5670_HP_SV_EN (0x1 << 12)
1785 #define RT5670_ZCD_DIG_MASK (0x1 << 11)
1788 #define RT5670_ZCD_DIG_EN (0x1 << 11)
1789 #define RT5670_ZCD_MASK (0x1 << 10)
1792 #define RT5670_ZCD_PU (0x1 << 10)
1795 #define RT5670_M_ZCD_RM_L (0x1 << 9)
1796 #define RT5670_M_ZCD_RM_R (0x1 << 8)
1797 #define RT5670_M_ZCD_SM_L (0x1 << 7)
1798 #define RT5670_M_ZCD_SM_R (0x1 << 6)
1799 #define RT5670_M_ZCD_OM_L (0x1 << 5)
1800 #define RT5670_M_ZCD_OM_R (0x1 << 4)
1805 #define RT5670_ZCD_HP_MASK (0x1 << 15)
1808 #define RT5670_ZCD_HP_EN (0x1 << 15)
1811 #define RT5670_TDM_DATA_MODE_SEL (0x1 << 11)
1813 #define RT5670_TDM_DATA_MODE_50FS (0x1 << 11)
1817 #define RT5670_3D_SPK_MASK (0x1 << 15)
1820 #define RT5670_3D_SPK_EN (0x1 << 15)
1829 #define RT5670_WND_MASK (0x1 << 15)
1832 #define RT5670_WND_EN (0x1 << 15)
1855 #define RT5670_WND_WIND_MASK (0x1 << 13) /* Read-Only */
1857 #define RT5670_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
1868 #define RT5670_DP_SPK_MASK (0x1 << 10)
1871 #define RT5670_DP_SPK_EN (0x1 << 10)
1883 #define RT5670_JD_CBJ_EN (0x1 << 7)
1884 #define RT5670_JD_CBJ_POL (0x1 << 6)
1888 #define RT5670_JD_CBJ_JD1_1 (0x1 << 3)
1897 #define RT5670_JD_HPO_JD1_1 (0x1)
1905 #define RT5670_RST_DSP (0x1 << 13)
1906 #define RT5670_IF1_ADC1_IN1_SEL (0x1 << 12)
1908 #define RT5670_IF1_ADC1_IN2_SEL (0x1 << 11)
1910 #define RT5670_IF1_ADC2_IN1_SEL (0x1 << 10)
1912 #define RT5670_MCLK_DET (0x1 << 3)
1915 #define RT5670_RXDC_SRC_MASK (0x1 << 7)
1917 #define RT5670_RXDC_SRC_MONO (0x1 << 7)
1919 #define RT5670_RXDP2_SEL_MASK (0x1 << 3)
1921 #define RT5670_RXDP2_SEL_ADC (0x1 << 3)
1970 RT5670_DA_STEREO_FILTER = 0x1,
1971 RT5670_DA_MONO_L_FILTER = (0x1 << 1),
1972 RT5670_DA_MONO_R_FILTER = (0x1 << 2),
1973 RT5670_AD_STEREO_FILTER = (0x1 << 3),
1974 RT5670_AD_MONO_L_FILTER = (0x1 << 4),
1975 RT5670_AD_MONO_R_FILTER = (0x1 << 5),
1976 RT5670_UP_RATE_FILTER = (0x1 << 6),
1977 RT5670_DOWN_RATE_FILTER = (0x1 << 7),