Lines Matching full:x1
183 #define RT5640_L_MUTE (0x1 << 15)
185 #define RT5640_VOL_L_MUTE (0x1 << 14)
187 #define RT5640_R_MUTE (0x1 << 7)
189 #define RT5640_VOL_R_MUTE (0x1 << 6)
207 #define RT5640_IN_DF1 (0x1 << 7)
209 #define RT5640_IN_DF2 (0x1 << 6)
213 #define RT5640_INL_SEL_MASK (0x1 << 15)
216 #define RT5640_INL_SEL_MONOP (0x1 << 15)
219 #define RT5640_INR_SEL_MASK (0x1 << 7)
222 #define RT5640_INR_SEL_MONON (0x1 << 7)
239 #define RT5640_M_DAC_L2_VOL (0x1 << 13)
241 #define RT5640_M_DAC_R2_VOL (0x1 << 12)
265 #define RT5640_M_ADC_L1 (0x1 << 14)
267 #define RT5640_M_ADC_L2 (0x1 << 13)
269 #define RT5640_ADC_1_SRC_MASK (0x1 << 12)
271 #define RT5640_ADC_1_SRC_ADC (0x1 << 12)
276 #define RT5640_ADC_2_SRC_DMIC2 (0x1 << 10)
278 #define RT5640_M_ADC_R1 (0x1 << 6)
280 #define RT5640_M_ADC_R2 (0x1 << 5)
284 #define RT5640_M_MONO_ADC_L1 (0x1 << 14)
286 #define RT5640_M_MONO_ADC_L2 (0x1 << 13)
288 #define RT5640_MONO_ADC_L1_SRC_MASK (0x1 << 12)
291 #define RT5640_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
295 #define RT5640_MONO_ADC_L2_SRC_DMIC_L2 (0x1 << 10)
297 #define RT5640_M_MONO_ADC_R1 (0x1 << 6)
299 #define RT5640_M_MONO_ADC_R2 (0x1 << 5)
301 #define RT5640_MONO_ADC_R1_SRC_MASK (0x1 << 4)
303 #define RT5640_MONO_ADC_R1_SRC_ADCR (0x1 << 4)
308 #define RT5640_MONO_ADC_R2_SRC_DMIC_R2 (0x1 << 2)
312 #define RT5640_M_ADCMIX_L (0x1 << 15)
314 #define RT5640_M_IF1_DAC_L (0x1 << 14)
316 #define RT5640_M_ADCMIX_R (0x1 << 7)
318 #define RT5640_M_IF1_DAC_R (0x1 << 6)
322 #define RT5640_M_DAC_L1 (0x1 << 14)
324 #define RT5640_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
326 #define RT5640_M_DAC_L2 (0x1 << 12)
328 #define RT5640_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
330 #define RT5640_M_ANC_DAC_L (0x1 << 10)
332 #define RT5640_M_DAC_R1 (0x1 << 6)
334 #define RT5640_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
336 #define RT5640_M_DAC_R2 (0x1 << 4)
338 #define RT5640_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
340 #define RT5640_M_ANC_DAC_R (0x1 << 2)
344 #define RT5640_M_DAC_L1_MONO_L (0x1 << 14)
346 #define RT5640_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
348 #define RT5640_M_DAC_L2_MONO_L (0x1 << 12)
350 #define RT5640_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
352 #define RT5640_M_DAC_R2_MONO_L (0x1 << 10)
354 #define RT5640_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)
356 #define RT5640_M_DAC_R1_MONO_R (0x1 << 6)
358 #define RT5640_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)
360 #define RT5640_M_DAC_R2_MONO_R (0x1 << 4)
362 #define RT5640_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)
364 #define RT5640_M_DAC_L2_MONO_R (0x1 << 2)
366 #define RT5640_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)
370 #define RT5640_M_STO_L_DAC_L (0x1 << 15)
372 #define RT5640_STO_L_DAC_L_VOL_MASK (0x1 << 14)
374 #define RT5640_M_DAC_L2_DAC_L (0x1 << 13)
376 #define RT5640_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
378 #define RT5640_M_STO_R_DAC_R (0x1 << 11)
380 #define RT5640_STO_R_DAC_R_VOL_MASK (0x1 << 10)
382 #define RT5640_M_DAC_R2_DAC_R (0x1 << 9)
384 #define RT5640_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
388 #define RT5640_RXDP_SRC_MASK (0x1 << 15)
391 #define RT5640_RXDP_SRC_DIV3 (0x1 << 15)
392 #define RT5640_TXDP_SRC_MASK (0x1 << 14)
395 #define RT5640_TXDP_SRC_DIV3 (0x1 << 14)
401 #define RT5640_DAC_L2_SEL_IF3 (0x1 << 14)
407 #define RT5640_DAC_R2_SEL_IF3 (0x1 << 12)
409 #define RT5640_IF2_ADC_L_SEL_MASK (0x1 << 11)
412 #define RT5640_IF2_ADC_L_SEL_PASS (0x1 << 11)
413 #define RT5640_IF2_ADC_R_SEL_MASK (0x1 << 10)
416 #define RT5640_IF2_ADC_R_SEL_PASS (0x1 << 10)
420 #define RT5640_RXDC_SEL_L2R (0x1 << 8)
426 #define RT5640_RXDP_SEL_L2R (0x1 << 6)
432 #define RT5640_TXDC_SEL_L2R (0x1 << 4)
438 #define RT5640_TXDP_SEL_L2R (0x1 << 2)
446 #define RT5640_IF1_DAC_SEL_SWAP (0x1 << 14)
452 #define RT5640_IF1_ADC_SEL_SWAP (0x1 << 12)
458 #define RT5640_IF2_DAC_SEL_SWAP (0x1 << 10)
464 #define RT5640_IF2_ADC_SEL_SWAP (0x1 << 8)
470 #define RT5640_IF3_DAC_SEL_SWAP (0x1 << 6)
476 #define RT5640_IF3_ADC_SEL_SWAP (0x1 << 4)
497 #define RT5640_M_HP_L_RM_L (0x1 << 6)
499 #define RT5640_M_IN_L_RM_L (0x1 << 5)
501 #define RT5640_M_BST4_RM_L (0x1 << 4)
503 #define RT5640_M_BST3_RM_L (0x1 << 3)
505 #define RT5640_M_BST2_RM_L (0x1 << 2)
507 #define RT5640_M_BST1_RM_L (0x1 << 1)
509 #define RT5640_M_OM_L_RM_L (0x1)
529 #define RT5640_M_HP_R_RM_R (0x1 << 6)
531 #define RT5640_M_IN_R_RM_R (0x1 << 5)
533 #define RT5640_M_BST4_RM_R (0x1 << 4)
535 #define RT5640_M_BST3_RM_R (0x1 << 3)
537 #define RT5640_M_BST2_RM_R (0x1 << 2)
539 #define RT5640_M_BST1_RM_R (0x1 << 1)
541 #define RT5640_M_OM_R_RM_R (0x1)
545 #define RT5640_M_DAC2_HM (0x1 << 15)
547 #define RT5640_M_DAC1_HM (0x1 << 14)
549 #define RT5640_M_HPVOL_HM (0x1 << 13)
551 #define RT5640_G_HPOMIX_MASK (0x1 << 12)
565 #define RT5640_M_RM_L_SM_L (0x1 << 5)
567 #define RT5640_M_IN_L_SM_L (0x1 << 4)
569 #define RT5640_M_DAC_L1_SM_L (0x1 << 3)
571 #define RT5640_M_DAC_L2_SM_L (0x1 << 2)
573 #define RT5640_M_OM_L_SM_L (0x1 << 1)
587 #define RT5640_M_RM_R_SM_R (0x1 << 5)
589 #define RT5640_M_IN_R_SM_R (0x1 << 4)
591 #define RT5640_M_DAC_R1_SM_R (0x1 << 3)
593 #define RT5640_M_DAC_R2_SM_R (0x1 << 2)
595 #define RT5640_M_OM_R_SM_R (0x1 << 1)
599 #define RT5640_M_DAC_R1_SPM_L (0x1 << 15)
601 #define RT5640_M_DAC_L1_SPM_L (0x1 << 14)
603 #define RT5640_M_SV_R_SPM_L (0x1 << 13)
605 #define RT5640_M_SV_L_SPM_L (0x1 << 12)
607 #define RT5640_M_BST1_SPM_L (0x1 << 11)
611 #define RT5640_M_DAC_R1_SPM_R (0x1 << 13)
613 #define RT5640_M_SV_R_SPM_R (0x1 << 12)
615 #define RT5640_M_BST1_SPM_R (0x1 << 11)
623 #define RT5640_M_DAC_R2_MM (0x1 << 15)
625 #define RT5640_M_DAC_L2_MM (0x1 << 14)
627 #define RT5640_M_OV_R_MM (0x1 << 13)
629 #define RT5640_M_OV_L_MM (0x1 << 12)
631 #define RT5640_M_BST1_MM (0x1 << 11)
633 #define RT5640_G_MONOMIX_MASK (0x1 << 10)
657 #define RT5640_M_SM_L_OM_L (0x1 << 8)
659 #define RT5640_M_BST3_OM_L (0x1 << 7)
661 #define RT5640_M_BST2_OM_L (0x1 << 6)
663 #define RT5640_M_BST1_OM_L (0x1 << 5)
665 #define RT5640_M_IN_L_OM_L (0x1 << 4)
667 #define RT5640_M_RM_L_OM_L (0x1 << 3)
669 #define RT5640_M_DAC_R2_OM_L (0x1 << 2)
671 #define RT5640_M_DAC_L2_OM_L (0x1 << 1)
673 #define RT5640_M_DAC_L1_OM_L (0x1)
697 #define RT5640_M_SM_L_OM_R (0x1 << 8)
699 #define RT5640_M_BST4_OM_R (0x1 << 7)
701 #define RT5640_M_BST2_OM_R (0x1 << 6)
703 #define RT5640_M_BST1_OM_R (0x1 << 5)
705 #define RT5640_M_IN_R_OM_R (0x1 << 4)
707 #define RT5640_M_RM_R_OM_R (0x1 << 3)
709 #define RT5640_M_DAC_L2_OM_R (0x1 << 2)
711 #define RT5640_M_DAC_R2_OM_R (0x1 << 1)
713 #define RT5640_M_DAC_R1_OM_R (0x1)
717 #define RT5640_M_DAC_L1_LM (0x1 << 15)
719 #define RT5640_M_DAC_R1_LM (0x1 << 14)
721 #define RT5640_M_OV_L_LM (0x1 << 13)
723 #define RT5640_M_OV_R_LM (0x1 << 12)
725 #define RT5640_G_LOUTMIX_MASK (0x1 << 11)
729 #define RT5640_PWR_I2S1 (0x1 << 15)
731 #define RT5640_PWR_I2S2 (0x1 << 14)
733 #define RT5640_PWR_DAC_L1 (0x1 << 12)
735 #define RT5640_PWR_DAC_R1 (0x1 << 11)
737 #define RT5640_PWR_DAC_L2 (0x1 << 7)
739 #define RT5640_PWR_DAC_R2 (0x1 << 6)
741 #define RT5640_PWR_ADC_L (0x1 << 2)
743 #define RT5640_PWR_ADC_R (0x1 << 1)
745 #define RT5640_PWR_CLS_D (0x1)
749 #define RT5640_PWR_ADC_SF (0x1 << 15)
751 #define RT5640_PWR_ADC_MF_L (0x1 << 14)
753 #define RT5640_PWR_ADC_MF_R (0x1 << 13)
755 #define RT5640_PWR_I2S_DSP (0x1 << 12)
759 #define RT5640_PWR_VREF1 (0x1 << 15)
761 #define RT5640_PWR_FV1 (0x1 << 14)
763 #define RT5640_PWR_MB (0x1 << 13)
765 #define RT5640_PWR_LM (0x1 << 12)
767 #define RT5640_PWR_BG (0x1 << 11)
769 #define RT5640_PWR_MM (0x1 << 10)
771 #define RT5640_PWR_MA (0x1 << 8)
773 #define RT5640_PWR_HP_L (0x1 << 7)
775 #define RT5640_PWR_HP_R (0x1 << 6)
777 #define RT5640_PWR_HA (0x1 << 5)
779 #define RT5640_PWR_VREF2 (0x1 << 4)
781 #define RT5640_PWR_FV2 (0x1 << 3)
783 #define RT5640_PWR_LDO2 (0x1 << 2)
787 #define RT5640_PWR_BST1 (0x1 << 15)
789 #define RT5640_PWR_BST2 (0x1 << 14)
791 #define RT5640_PWR_BST3 (0x1 << 13)
793 #define RT5640_PWR_BST4 (0x1 << 12)
795 #define RT5640_PWR_MB1 (0x1 << 11)
797 #define RT5640_PWR_PLL (0x1 << 9)
801 #define RT5640_PWR_OM_L (0x1 << 15)
803 #define RT5640_PWR_OM_R (0x1 << 14)
805 #define RT5640_PWR_SM_L (0x1 << 13)
807 #define RT5640_PWR_SM_R (0x1 << 12)
809 #define RT5640_PWR_RM_L (0x1 << 11)
811 #define RT5640_PWR_RM_R (0x1 << 10)
815 #define RT5640_PWR_SV_L (0x1 << 15)
817 #define RT5640_PWR_SV_R (0x1 << 14)
819 #define RT5640_PWR_OV_L (0x1 << 13)
821 #define RT5640_PWR_OV_R (0x1 << 12)
823 #define RT5640_PWR_HV_L (0x1 << 11)
825 #define RT5640_PWR_HV_R (0x1 << 10)
827 #define RT5640_PWR_IN_L (0x1 << 9)
829 #define RT5640_PWR_IN_R (0x1 << 8)
833 #define RT5640_I2S_MS_MASK (0x1 << 15)
836 #define RT5640_I2S_MS_S (0x1 << 15)
842 #define RT5640_I2S_O_CP_U_LAW (0x1 << 10)
847 #define RT5640_I2S_I_CP_U_LAW (0x1 << 8)
849 #define RT5640_I2S_BP_MASK (0x1 << 7)
852 #define RT5640_I2S_BP_INV (0x1 << 7)
856 #define RT5640_I2S_DL_20 (0x1 << 2)
862 #define RT5640_I2S_DF_LEFT (0x1)
867 #define RT5640_I2S2_SDI_MASK (0x1 << 6)
870 #define RT5640_I2S2_SDI_I2S2 (0x1 << 6)
873 #define RT5640_I2S_BCLK_MS1_MASK (0x1 << 15)
876 #define RT5640_I2S_BCLK_MS1_64 (0x1 << 15)
880 #define RT5640_I2S_PD1_2 (0x1 << 12)
887 #define RT5640_I2S_BCLK_MS2_MASK (0x1 << 11)
890 #define RT5640_I2S_BCLK_MS2_64 (0x1 << 11)
894 #define RT5640_I2S_PD2_2 (0x1 << 8)
901 #define RT5640_I2S_BCLK_MS3_MASK (0x1 << 7)
904 #define RT5640_I2S_BCLK_MS3_64 (0x1 << 7)
908 #define RT5640_I2S_PD3_2 (0x1 << 4)
918 #define RT5640_DAC_OSR_64 (0x1 << 2)
924 #define RT5640_ADC_OSR_64 (0x1)
932 #define RT5640_DAC_L_OSR_64 (0x1 << 14)
938 #define RT5640_ADC_R_OSR_64 (0x1 << 12)
941 #define RT5640_DAHPF_EN (0x1 << 11)
943 #define RT5640_ADHPF_EN (0x1 << 10)
947 #define RT5640_DMIC_1_EN_MASK (0x1 << 15)
950 #define RT5640_DMIC_1_EN (0x1 << 15)
951 #define RT5640_DMIC_2_EN_MASK (0x1 << 14)
954 #define RT5640_DMIC_2_EN (0x1 << 14)
955 #define RT5640_DMIC_1L_LH_MASK (0x1 << 13)
958 #define RT5640_DMIC_1L_LH_RISING (0x1 << 13)
959 #define RT5640_DMIC_1R_LH_MASK (0x1 << 12)
962 #define RT5640_DMIC_1R_LH_RISING (0x1 << 12)
963 #define RT5640_DMIC_1_DP_MASK (0x1 << 11)
966 #define RT5640_DMIC_1_DP_IN1P (0x1 << 11)
967 #define RT5640_DMIC_2_DP_MASK (0x1 << 10)
970 #define RT5640_DMIC_2_DP_IN1N (0x1 << 10)
971 #define RT5640_DMIC_2L_LH_MASK (0x1 << 9)
974 #define RT5640_DMIC_2L_LH_RISING (0x1 << 9)
975 #define RT5640_DMIC_2R_LH_MASK (0x1 << 8)
978 #define RT5640_DMIC_2R_LH_RISING (0x1 << 8)
986 #define RT5640_SCLK_SRC_PLL1 (0x1 << 14)
991 #define RT5640_PLL1_SRC_BCLK1 (0x1 << 12)
994 #define RT5640_PLL1_PD_MASK (0x1 << 3)
997 #define RT5640_PLL1_PD_2 (0x1 << 3)
1013 #define RT5640_PLL_M_BP (0x1 << 11)
1017 #define RT5640_STO_T_MASK (0x1 << 15)
1020 #define RT5640_STO_T_LRCK1 (0x1 << 15)
1021 #define RT5640_M1_T_MASK (0x1 << 14)
1024 #define RT5640_M1_T_I2S2_D3 (0x1 << 14)
1025 #define RT5640_I2S2_F_MASK (0x1 << 12)
1028 #define RT5640_I2S2_F_I2S1_TCLK (0x1 << 12)
1029 #define RT5640_DMIC_1_M_MASK (0x1 << 9)
1032 #define RT5640_DMIC_1_M_ASYN (0x1 << 9)
1033 #define RT5640_DMIC_2_M_MASK (0x1 << 8)
1036 #define RT5640_DMIC_2_M_ASYN (0x1 << 8)
1040 #define RT5640_CLK_SEL_ASRC (0x1)
1043 #define RT5640_MDA_L_M_MASK (0x1 << 15)
1046 #define RT5640_MDA_L_M_ASYN (0x1 << 15)
1047 #define RT5640_MDA_R_M_MASK (0x1 << 14)
1050 #define RT5640_MDA_R_M_ASYN (0x1 << 14)
1051 #define RT5640_MAD_L_M_MASK (0x1 << 13)
1054 #define RT5640_MAD_L_M_ASYN (0x1 << 13)
1055 #define RT5640_MAD_R_M_MASK (0x1 << 12)
1058 #define RT5640_MAD_R_M_ASYN (0x1 << 12)
1059 #define RT5640_ADC_M_MASK (0x1 << 11)
1062 #define RT5640_ADC_M_ASYN (0x1 << 11)
1063 #define RT5640_STO_DAC_M_MASK (0x1 << 5)
1066 #define RT5640_STO_DAC_M_ASYN (0x1 << 5)
1067 #define RT5640_I2S1_R_D_MASK (0x1 << 4)
1070 #define RT5640_I2S1_R_D_EN (0x1 << 4)
1071 #define RT5640_I2S2_R_D_MASK (0x1 << 3)
1074 #define RT5640_I2S2_R_D_EN (0x1 << 3)
1078 #define RT5640_PRE_SCLK_1024 (0x1)
1094 #define RT5640_HP_OVCD_MASK (0x1 << 10)
1097 #define RT5640_HP_OVCD_EN (0x1 << 10)
1101 #define RT5640_HP_OC_TH_105 (0x1 << 8)
1106 #define RT5640_CLSD_OC_MASK (0x1 << 9)
1109 #define RT5640_CLSD_OC_PD (0x1 << 9)
1110 #define RT5640_AUTO_PD_MASK (0x1 << 8)
1113 #define RT5640_AUTO_PD_EN (0x1 << 8)
1120 #define RT5640_CLSD_OM_MASK (0x1 << 11)
1123 #define RT5640_CLSD_OM_STO (0x1 << 11)
1124 #define RT5640_CLSD_SCH_MASK (0x1 << 10)
1127 #define RT5640_CLSD_SCH_S (0x1 << 10)
1130 #define RT5640_SMT_TRIG_MASK (0x1 << 15)
1133 #define RT5640_SMT_TRIG_EN (0x1 << 15)
1134 #define RT5640_HP_L_SMT_MASK (0x1 << 9)
1137 #define RT5640_HP_L_SMT_EN (0x1 << 9)
1138 #define RT5640_HP_R_SMT_MASK (0x1 << 8)
1141 #define RT5640_HP_R_SMT_EN (0x1 << 8)
1142 #define RT5640_HP_CD_PD_MASK (0x1 << 7)
1145 #define RT5640_HP_CD_PD_EN (0x1 << 7)
1146 #define RT5640_RSTN_MASK (0x1 << 6)
1149 #define RT5640_RSTN_EN (0x1 << 6)
1150 #define RT5640_RSTP_MASK (0x1 << 5)
1153 #define RT5640_RSTP_EN (0x1 << 5)
1154 #define RT5640_HP_CO_MASK (0x1 << 4)
1157 #define RT5640_HP_CO_EN (0x1 << 4)
1158 #define RT5640_HP_CP_MASK (0x1 << 3)
1161 #define RT5640_HP_CP_PU (0x1 << 3)
1162 #define RT5640_HP_SG_MASK (0x1 << 2)
1165 #define RT5640_HP_SG_EN (0x1 << 2)
1166 #define RT5640_HP_DP_MASK (0x1 << 1)
1169 #define RT5640_HP_DP_PU (0x1 << 1)
1170 #define RT5640_HP_CB_MASK (0x1)
1173 #define RT5640_HP_CB_PU (0x1)
1176 #define RT5640_DEPOP_MASK (0x1 << 13)
1179 #define RT5640_DEPOP_MAN (0x1 << 13)
1180 #define RT5640_RAMP_MASK (0x1 << 12)
1183 #define RT5640_RAMP_EN (0x1 << 12)
1184 #define RT5640_BPS_MASK (0x1 << 11)
1187 #define RT5640_BPS_EN (0x1 << 11)
1188 #define RT5640_FAST_UPDN_MASK (0x1 << 10)
1191 #define RT5640_FAST_UPDN_EN (0x1 << 10)
1195 #define RT5640_MRES_25MO (0x1 << 8)
1198 #define RT5640_VLO_MASK (0x1 << 7)
1201 #define RT5640_VLO_32V (0x1 << 7)
1202 #define RT5640_DIG_DP_MASK (0x1 << 6)
1205 #define RT5640_DIG_DP_EN (0x1 << 6)
1228 #define RT5640_OSW_L_MASK (0x1 << 11)
1231 #define RT5640_OSW_L_EN (0x1 << 11)
1232 #define RT5640_OSW_R_MASK (0x1 << 10)
1235 #define RT5640_OSW_R_EN (0x1 << 10)
1239 #define RT5640_PM_HP_MV (0x1 << 8)
1244 #define RT5640_IB_HP_25IL (0x1 << 6)
1249 #define RT5640_PVDD_DET_MASK (0x1 << 15)
1252 #define RT5640_PVDD_DET_EN (0x1 << 15)
1253 #define RT5640_SPK_AG_MASK (0x1 << 14)
1256 #define RT5640_SPK_AG_EN (0x1 << 14)
1259 #define RT5640_MIC1_BS_MASK (0x1 << 15)
1262 #define RT5640_MIC1_BS_75AV (0x1 << 15)
1263 #define RT5640_MIC2_BS_MASK (0x1 << 14)
1266 #define RT5640_MIC2_BS_75AV (0x1 << 14)
1267 #define RT5640_MIC1_CLK_MASK (0x1 << 13)
1270 #define RT5640_MIC1_CLK_EN (0x1 << 13)
1271 #define RT5640_MIC2_CLK_MASK (0x1 << 12)
1274 #define RT5640_MIC2_CLK_EN (0x1 << 12)
1275 #define RT5640_MIC1_OVCD_MASK (0x1 << 11)
1278 #define RT5640_MIC1_OVCD_EN (0x1 << 11)
1282 #define RT5640_MIC1_OVTH_1500UA (0x1 << 9)
1284 #define RT5640_MIC2_OVCD_MASK (0x1 << 8)
1287 #define RT5640_MIC2_OVCD_EN (0x1 << 8)
1291 #define RT5640_MIC2_OVTH_1500UA (0x1 << 6)
1293 #define RT5640_PWR_MB_MASK (0x1 << 5)
1296 #define RT5640_PWR_MB_PU (0x1 << 5)
1297 #define RT5640_PWR_CLK25M_MASK (0x1 << 4)
1300 #define RT5640_PWR_CLK25M_PU (0x1 << 4)
1303 #define RT5640_EQ_SRC_MASK (0x1 << 15)
1306 #define RT5640_EQ_SRC_ADC (0x1 << 15)
1307 #define RT5640_EQ_UPD (0x1 << 14)
1309 #define RT5640_EQ_CD_MASK (0x1 << 13)
1312 #define RT5640_EQ_CD_EN (0x1 << 13)
1316 #define RT5640_EQ_DITH_LSB (0x1 << 8)
1321 #define RT5640_EQ_HPF1_M_MASK (0x1 << 8)
1324 #define RT5640_EQ_HPF1_M_1ST (0x1 << 8)
1325 #define RT5640_EQ_LPF1_M_MASK (0x1 << 7)
1328 #define RT5640_EQ_LPF1_M_1ST (0x1 << 7)
1329 #define RT5640_EQ_HPF2_MASK (0x1 << 6)
1332 #define RT5640_EQ_HPF2_EN (0x1 << 6)
1333 #define RT5640_EQ_HPF1_MASK (0x1 << 5)
1336 #define RT5640_EQ_HPF1_EN (0x1 << 5)
1337 #define RT5640_EQ_BPF4_MASK (0x1 << 4)
1340 #define RT5640_EQ_BPF4_EN (0x1 << 4)
1341 #define RT5640_EQ_BPF3_MASK (0x1 << 3)
1344 #define RT5640_EQ_BPF3_EN (0x1 << 3)
1345 #define RT5640_EQ_BPF2_MASK (0x1 << 2)
1348 #define RT5640_EQ_BPF2_EN (0x1 << 2)
1349 #define RT5640_EQ_BPF1_MASK (0x1 << 1)
1352 #define RT5640_EQ_BPF1_EN (0x1 << 1)
1353 #define RT5640_EQ_LPF_MASK (0x1)
1356 #define RT5640_EQ_LPF_EN (0x1)
1359 #define RT5640_MT_MASK (0x1 << 15)
1362 #define RT5640_MT_EN (0x1 << 15)
1365 #define RT5640_DRC_AGC_P_MASK (0x1 << 15)
1368 #define RT5640_DRC_AGC_P_ADC (0x1 << 15)
1369 #define RT5640_DRC_AGC_MASK (0x1 << 14)
1372 #define RT5640_DRC_AGC_EN (0x1 << 14)
1373 #define RT5640_DRC_AGC_UPD (0x1 << 13)
1379 #define RT5640_DRC_AGC_R_48K (0x1 << 5)
1391 #define RT5640_DRC_AGC_CP_MASK (0x1 << 7)
1394 #define RT5640_DRC_AGC_CP_EN (0x1 << 7)
1398 #define RT5640_DRC_AGC_CPR_1_2 (0x1 << 5)
1409 #define RT5640_DRC_AGC_NG_MASK (0x1 << 6)
1412 #define RT5640_DRC_AGC_NG_EN (0x1 << 6)
1413 #define RT5640_DRC_AGC_NGH_MASK (0x1 << 5)
1416 #define RT5640_DRC_AGC_NGH_EN (0x1 << 5)
1421 #define RT5640_ANC_M_MASK (0x1 << 15)
1424 #define RT5640_ANC_M_REV (0x1 << 15)
1425 #define RT5640_ANC_MASK (0x1 << 14)
1428 #define RT5640_ANC_EN (0x1 << 14)
1432 #define RT5640_ANC_MD_67MS (0x1 << 12)
1435 #define RT5640_ANC_SN_MASK (0x1 << 11)
1438 #define RT5640_ANC_SN_EN (0x1 << 11)
1439 #define RT5640_ANC_CLK_MASK (0x1 << 10)
1442 #define RT5640_ANC_CLK_REG (0x1 << 10)
1446 #define RT5640_ANC_ZCD_T1 (0x1 << 8)
1449 #define RT5640_ANC_CS_MASK (0x1 << 7)
1452 #define RT5640_ANC_CS_EN (0x1 << 7)
1453 #define RT5640_ANC_SW_MASK (0x1 << 6)
1456 #define RT5640_ANC_SW_AUTO (0x1 << 6)
1471 #define RT5640_ANC_CD_MASK (0x1 << 6)
1474 #define RT5640_ANC_CD_IND (0x1 << 6)
1482 #define RT5640_JD_GPIO1 (0x1 << 13)
1488 #define RT5640_JD_HP_MASK (0x1 << 11)
1491 #define RT5640_JD_HP_EN (0x1 << 11)
1492 #define RT5640_JD_HP_TRG_MASK (0x1 << 10)
1495 #define RT5640_JD_HP_TRG_HI (0x1 << 10)
1496 #define RT5640_JD_SPL_MASK (0x1 << 9)
1499 #define RT5640_JD_SPL_EN (0x1 << 9)
1500 #define RT5640_JD_SPL_TRG_MASK (0x1 << 8)
1503 #define RT5640_JD_SPL_TRG_HI (0x1 << 8)
1504 #define RT5640_JD_SPR_MASK (0x1 << 7)
1507 #define RT5640_JD_SPR_EN (0x1 << 7)
1508 #define RT5640_JD_SPR_TRG_MASK (0x1 << 6)
1511 #define RT5640_JD_SPR_TRG_HI (0x1 << 6)
1512 #define RT5640_JD_MO_MASK (0x1 << 5)
1515 #define RT5640_JD_MO_EN (0x1 << 5)
1516 #define RT5640_JD_MO_TRG_MASK (0x1 << 4)
1519 #define RT5640_JD_MO_TRG_HI (0x1 << 4)
1520 #define RT5640_JD_LO_MASK (0x1 << 3)
1523 #define RT5640_JD_LO_EN (0x1 << 3)
1524 #define RT5640_JD_LO_TRG_MASK (0x1 << 2)
1527 #define RT5640_JD_LO_TRG_HI (0x1 << 2)
1528 #define RT5640_JD1_IN4P_MASK (0x1 << 1)
1531 #define RT5640_JD1_IN4P_EN (0x1 << 1)
1532 #define RT5640_JD2_IN4N_MASK (0x1)
1535 #define RT5640_JD2_IN4N_EN (0x1)
1541 #define RT5640_ANC_DET_MB1 (0x1 << 4)
1544 #define RT5640_AD_TRG_MASK (0x1 << 3)
1547 #define RT5640_AD_TRG_HI (0x1 << 3)
1551 #define RT5640_ANCM_DET_MB1 (0x1 << 4)
1554 #define RT5640_AMD_TRG_MASK (0x1 << 3)
1557 #define RT5640_AMD_TRG_HI (0x1 << 3)
1560 #define RT5640_IRQ_JD_MASK (0x1 << 15)
1563 #define RT5640_IRQ_JD_NOR (0x1 << 15)
1564 #define RT5640_IRQ_OT_MASK (0x1 << 14)
1567 #define RT5640_IRQ_OT_NOR (0x1 << 14)
1568 #define RT5640_JD_STKY_MASK (0x1 << 13)
1571 #define RT5640_JD_STKY_EN (0x1 << 13)
1572 #define RT5640_OT_STKY_MASK (0x1 << 12)
1575 #define RT5640_OT_STKY_EN (0x1 << 12)
1576 #define RT5640_JD_P_MASK (0x1 << 11)
1579 #define RT5640_JD_P_INV (0x1 << 11)
1580 #define RT5640_OT_P_MASK (0x1 << 10)
1583 #define RT5640_OT_P_INV (0x1 << 10)
1586 #define RT5640_IRQ_MB1_OC_MASK (0x1 << 15)
1589 #define RT5640_IRQ_MB1_OC_NOR (0x1 << 15)
1590 #define RT5640_IRQ_MB2_OC_MASK (0x1 << 14)
1593 #define RT5640_IRQ_MB2_OC_NOR (0x1 << 14)
1594 #define RT5640_MB1_OC_STKY_MASK (0x1 << 11)
1597 #define RT5640_MB1_OC_STKY_EN (0x1 << 11)
1598 #define RT5640_MB2_OC_STKY_MASK (0x1 << 10)
1601 #define RT5640_MB2_OC_STKY_EN (0x1 << 10)
1602 #define RT5640_MB1_OC_P_MASK (0x1 << 7)
1605 #define RT5640_MB1_OC_P_INV (0x1 << 7)
1606 #define RT5640_MB2_OC_P_MASK (0x1 << 6)
1609 #define RT5640_MB2_OC_P_INV (0x1 << 6)
1610 #define RT5640_MB1_OC_STATUS (0x1 << 3)
1612 #define RT5640_MB2_OC_STATUS (0x1 << 2)
1616 #define RT5640_GPIO1_STATUS (0x1 << 8)
1617 #define RT5640_GPIO2_STATUS (0x1 << 7)
1618 #define RT5640_JD_STATUS (0x1 << 4)
1619 #define RT5640_OVT_STATUS (0x1 << 3)
1620 #define RT5640_CLS_D_OVCD_STATUS (0x1 << 0)
1623 #define RT5640_GP1_PIN_MASK (0x1 << 15)
1626 #define RT5640_GP1_PIN_IRQ (0x1 << 15)
1627 #define RT5640_GP2_PIN_MASK (0x1 << 14)
1630 #define RT5640_GP2_PIN_DMIC1_SCL (0x1 << 14)
1634 #define RT5640_GP3_PIN_DMIC1_SDA (0x1 << 12)
1636 #define RT5640_GP4_PIN_MASK (0x1 << 11)
1639 #define RT5640_GP4_PIN_DMIC2_SDA (0x1 << 11)
1640 #define RT5640_DP_SIG_MASK (0x1 << 10)
1643 #define RT5640_DP_SIG_AP (0x1 << 10)
1644 #define RT5640_GPIO_M_MASK (0x1 << 9)
1647 #define RT5640_GPIO_M_PH (0x1 << 9)
1650 #define RT5640_GP4_PF_MASK (0x1 << 11)
1653 #define RT5640_GP4_PF_OUT (0x1 << 11)
1654 #define RT5640_GP4_OUT_MASK (0x1 << 10)
1657 #define RT5640_GP4_OUT_HI (0x1 << 10)
1658 #define RT5640_GP4_P_MASK (0x1 << 9)
1661 #define RT5640_GP4_P_INV (0x1 << 9)
1662 #define RT5640_GP3_PF_MASK (0x1 << 8)
1665 #define RT5640_GP3_PF_OUT (0x1 << 8)
1666 #define RT5640_GP3_OUT_MASK (0x1 << 7)
1669 #define RT5640_GP3_OUT_HI (0x1 << 7)
1670 #define RT5640_GP3_P_MASK (0x1 << 6)
1673 #define RT5640_GP3_P_INV (0x1 << 6)
1674 #define RT5640_GP2_PF_MASK (0x1 << 5)
1677 #define RT5640_GP2_PF_OUT (0x1 << 5)
1678 #define RT5640_GP2_OUT_MASK (0x1 << 4)
1681 #define RT5640_GP2_OUT_HI (0x1 << 4)
1682 #define RT5640_GP2_P_MASK (0x1 << 3)
1685 #define RT5640_GP2_P_INV (0x1 << 3)
1686 #define RT5640_GP1_PF_MASK (0x1 << 2)
1689 #define RT5640_GP1_PF_OUT (0x1 << 2)
1690 #define RT5640_GP1_OUT_MASK (0x1 << 1)
1693 #define RT5640_GP1_OUT_HI (0x1 << 1)
1694 #define RT5640_GP1_P_MASK (0x1)
1697 #define RT5640_GP1_P_INV (0x1)
1706 #define RT5640_DSP_BUSY_MASK (0x1 << 15)
1708 #define RT5640_DSP_DS_MASK (0x1 << 14)
1710 #define RT5640_DSP_DS_FM3010 (0x1 << 14)
1711 #define RT5640_DSP_DS_TEMP (0x1 << 14)
1715 #define RT5640_DSP_CLK_192K (0x1 << 12)
1718 #define RT5640_DSP_PD_PIN_MASK (0x1 << 11)
1721 #define RT5640_DSP_PD_PIN_HI (0x1 << 11)
1722 #define RT5640_DSP_RST_PIN_MASK (0x1 << 10)
1725 #define RT5640_DSP_RST_PIN_HI (0x1 << 10)
1726 #define RT5640_DSP_R_EN (0x1 << 9)
1728 #define RT5640_DSP_W_EN (0x1 << 8)
1740 #define RT5640_SEQ1_ST_MASK (0x1 << 11) /*RO*/
1743 #define RT5640_SEQ1_ST_FIN (0x1 << 11)
1744 #define RT5640_SEQ2_ST_MASK (0x1 << 10) /*RO*/
1747 #define RT5640_SEQ2_ST_FIN (0x1 << 10)
1748 #define RT5640_REG_LV_MASK (0x1 << 9)
1751 #define RT5640_REG_LV_PR (0x1 << 9)
1752 #define RT5640_SEQ_2_PT_MASK (0x1 << 8)
1764 #define RT5640_PROG_MASK (0x1 << 7)
1767 #define RT5640_PROG_EN (0x1 << 7)
1768 #define RT5640_SEQ1_PT_RUN (0x1 << 6)
1770 #define RT5640_SEQ2_PT_RUN (0x1 << 5)
1790 #define RT5640_SCB_SWAP_MASK (0x1 << 15)
1793 #define RT5640_SCB_SWAP_EN (0x1 << 15)
1794 #define RT5640_SCB_MASK (0x1 << 14)
1797 #define RT5640_SCB_EN (0x1 << 14)
1800 #define RT5640_BB_MASK (0x1 << 15)
1803 #define RT5640_BB_EN (0x1 << 15)
1807 #define RT5640_BB_CT_B (0x1 << 12)
1810 #define RT5640_M_BB_L_MASK (0x1 << 9)
1812 #define RT5640_M_BB_R_MASK (0x1 << 8)
1814 #define RT5640_M_BB_HPF_L_MASK (0x1 << 7)
1816 #define RT5640_M_BB_HPF_R_MASK (0x1 << 6)
1822 #define RT5640_M_MP3_L_MASK (0x1 << 15)
1824 #define RT5640_M_MP3_R_MASK (0x1 << 14)
1826 #define RT5640_M_MP3_MASK (0x1 << 13)
1829 #define RT5640_M_MP3_EN (0x1 << 13)
1832 #define RT5640_MP3_HLP_MASK (0x1 << 7)
1835 #define RT5640_MP3_HLP_EN (0x1 << 7)
1836 #define RT5640_M_MP3_ORG_L_MASK (0x1 << 6)
1838 #define RT5640_M_MP3_ORG_R_MASK (0x1 << 5)
1842 #define RT5640_MP3_WT_MASK (0x1 << 13)
1845 #define RT5640_MP3_WT_1_2 (0x1 << 13)
1852 #define RT5640_3D_CF_MASK (0x1 << 15)
1855 #define RT5640_3D_CF_EN (0x1 << 15)
1856 #define RT5640_3D_HP_MASK (0x1 << 14)
1859 #define RT5640_3D_HP_EN (0x1 << 14)
1860 #define RT5640_3D_BT_MASK (0x1 << 13)
1863 #define RT5640_3D_BT_EN (0x1 << 13)
1866 #define RT5640_3D_HP_M_MASK (0x1 << 10)
1869 #define RT5640_3D_HP_M_FRO (0x1 << 10)
1870 #define RT5640_M_3D_HRTF_MASK (0x1 << 9)
1872 #define RT5640_M_3D_D2H_MASK (0x1 << 8)
1874 #define RT5640_M_3D_D2R_MASK (0x1 << 7)
1876 #define RT5640_M_3D_REVB_MASK (0x1 << 6)
1880 #define RT5640_2ND_HPF_MASK (0x1 << 15)
1883 #define RT5640_2ND_HPF_EN (0x1 << 15)
1886 #define RT5640_1ST_HPF_MASK (0x1 << 11)
1889 #define RT5640_1ST_HPF_EN (0x1 << 11)
1897 #define RT5640_ZD_F_ZC_IM (0x1 << 4)
1902 #define RT5640_SI_DAC_MASK (0x1 << 11)
1905 #define RT5640_SI_DAC_TEST (0x1 << 11)
1906 #define RT5640_DC_CAL_M_MASK (0x1 << 10)
1909 #define RT5640_DC_CAL_M_NOR (0x1 << 10)
1910 #define RT5640_DC_CAL_MASK (0x1 << 9)
1913 #define RT5640_DC_CAL_EN (0x1 << 9)
1916 #define RT5640_HPD_PS_MASK (0x1 << 5)
1919 #define RT5640_HPD_PS_EN (0x1 << 5)
1920 #define RT5640_CAL_M_MASK (0x1 << 4)
1923 #define RT5640_CAL_M_CAL (0x1 << 4)
1924 #define RT5640_CAL_MASK (0x1 << 3)
1927 #define RT5640_CAL_EN (0x1 << 3)
1928 #define RT5640_CAL_TEST_MASK (0x1 << 2)
1931 #define RT5640_CAL_TEST_EN (0x1 << 2)
1935 #define RT5640_CAL_P_CAL (0x1)
1939 #define RT5640_SV_MASK (0x1 << 15)
1942 #define RT5640_SV_EN (0x1 << 15)
1943 #define RT5640_SPO_SV_MASK (0x1 << 14)
1946 #define RT5640_SPO_SV_EN (0x1 << 14)
1947 #define RT5640_OUT_SV_MASK (0x1 << 13)
1950 #define RT5640_OUT_SV_EN (0x1 << 13)
1951 #define RT5640_HP_SV_MASK (0x1 << 12)
1954 #define RT5640_HP_SV_EN (0x1 << 12)
1955 #define RT5640_ZCD_DIG_MASK (0x1 << 11)
1958 #define RT5640_ZCD_DIG_EN (0x1 << 11)
1959 #define RT5640_ZCD_MASK (0x1 << 10)
1962 #define RT5640_ZCD_PU (0x1 << 10)
1965 #define RT5640_M_ZCD_RM_L (0x1 << 9)
1966 #define RT5640_M_ZCD_RM_R (0x1 << 8)
1967 #define RT5640_M_ZCD_SM_L (0x1 << 7)
1968 #define RT5640_M_ZCD_SM_R (0x1 << 6)
1969 #define RT5640_M_ZCD_OM_L (0x1 << 5)
1970 #define RT5640_M_ZCD_OM_R (0x1 << 4)
1975 #define RT5640_ZCD_HP_MASK (0x1 << 15)
1978 #define RT5640_ZCD_HP_EN (0x1 << 15)
1981 #define RT5640_EN_LOUT_DF (0x1 << 14)
1983 #define RT5640_M_MONO_ADC_L (0x1 << 13)
1985 #define RT5640_M_MONO_ADC_R (0x1 << 12)
1987 #define RT5640_MCLK_DET (0x1 << 11)
1990 #define RT5640_IRQ_JD2_MASK (0x1 << 12)
1993 #define RT5640_IRQ_JD2_NOR (0x1 << 12)
1994 #define RT5640_JD2_P_MASK (0x1 << 10)
1997 #define RT5640_JD2_P_INV (0x1 << 10)
1998 #define RT5640_JD2_MASK (0x1 << 8)
2001 #define RT5640_JD2_EN (0x1 << 8)
2009 #define RT5640_MIC_OVCD_SF_0P75 (0x1 << 8)
2014 #define RT5640_3D_SPK_MASK (0x1 << 15)
2017 #define RT5640_3D_SPK_EN (0x1 << 15)
2026 #define RT5640_WND_MASK (0x1 << 15)
2029 #define RT5640_WND_EN (0x1 << 15)
2052 #define RT5640_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2054 #define RT5640_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2065 #define RT5640_DP_SPK_MASK (0x1 << 10)
2068 #define RT5640_DP_SPK_EN (0x1 << 10)
2103 RT5640_U_IF1 = 0x1,
2128 RT5640_DA_STEREO_FILTER = 0x1,
2129 RT5640_DA_MONO_L_FILTER = (0x1 << 1),
2130 RT5640_DA_MONO_R_FILTER = (0x1 << 2),
2131 RT5640_AD_STEREO_FILTER = (0x1 << 3),
2132 RT5640_AD_MONO_L_FILTER = (0x1 << 4),
2133 RT5640_AD_MONO_R_FILTER = (0x1 << 5),