Lines Matching full:x1
152 #define RT5616_L_MUTE (0x1 << 15)
154 #define RT5616_VOL_L_MUTE (0x1 << 14)
156 #define RT5616_R_MUTE (0x1 << 7)
158 #define RT5616_VOL_R_MUTE (0x1 << 6)
166 #define RT5616_EN_DFO (0x1 << 15)
174 #define RT5616_IN_DF1 (0x1 << 7)
176 #define RT5616_IN_DF2 (0x1 << 6)
182 #define RT5616_INR_SEL_MASK (0x1 << 7)
185 #define RT5616_INR_SEL_MONON (0x1 << 7)
208 #define RT5616_M_MONO_ADC_L (0x1 << 15)
212 #define RT5616_M_MONO_ADC_R (0x1 << 7)
226 #define RT5616_M_STO1_ADC_L1 (0x1 << 14)
228 #define RT5616_M_STO1_ADC_R1 (0x1 << 6)
232 #define RT5616_M_ADCMIX_L (0x1 << 15)
234 #define RT5616_M_IF1_DAC_L (0x1 << 14)
236 #define RT5616_M_ADCMIX_R (0x1 << 7)
238 #define RT5616_M_IF1_DAC_R (0x1 << 6)
242 #define RT5616_M_DAC_L1_MIXL (0x1 << 14)
244 #define RT5616_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
246 #define RT5616_M_DAC_R1_MIXL (0x1 << 9)
248 #define RT5616_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
250 #define RT5616_M_DAC_R1_MIXR (0x1 << 6)
252 #define RT5616_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
254 #define RT5616_M_DAC_L1_MIXR (0x1 << 1)
256 #define RT5616_DAC_L1_STO_R_VOL_MASK (0x1)
260 #define RT5616_M_STO_DD_L1 (0x1 << 14)
262 #define RT5616_STO_DD_L1_VOL_MASK (0x1 << 13)
264 #define RT5616_M_STO_DD_L2 (0x1 << 12)
266 #define RT5616_STO_DD_L2_VOL_MASK (0x1 << 11)
268 #define RT5616_M_STO_DD_R2_L (0x1 << 10)
270 #define RT5616_STO_DD_R2_L_VOL_MASK (0x1 << 9)
272 #define RT5616_M_STO_DD_R1 (0x1 << 6)
274 #define RT5616_STO_DD_R1_VOL_MASK (0x1 << 5)
276 #define RT5616_M_STO_DD_R2 (0x1 << 4)
278 #define RT5616_STO_DD_R2_VOL_MASK (0x1 << 3)
280 #define RT5616_M_STO_DD_L2_R (0x1 << 2)
282 #define RT5616_STO_DD_L2_R_VOL_MASK (0x1 << 1)
286 #define RT5616_M_STO_L_DAC_L (0x1 << 15)
288 #define RT5616_STO_L_DAC_L_VOL_MASK (0x1 << 14)
290 #define RT5616_M_DAC_L2_DAC_L (0x1 << 13)
292 #define RT5616_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
294 #define RT5616_M_STO_R_DAC_R (0x1 << 11)
296 #define RT5616_STO_R_DAC_R_VOL_MASK (0x1 << 10)
298 #define RT5616_M_DAC_R2_DAC_R (0x1 << 9)
300 #define RT5616_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
304 #define RT5616_RXDP_SRC_MASK (0x1 << 15)
307 #define RT5616_RXDP_SRC_DIV3 (0x1 << 15)
308 #define RT5616_TXDP_SRC_MASK (0x1 << 14)
311 #define RT5616_TXDP_SRC_DIV3 (0x1 << 14)
317 #define RT5616_DAC_L2_SEL_IF3 (0x1 << 14)
323 #define RT5616_DAC_R2_SEL_IF3 (0x1 << 12)
325 #define RT5616_IF2_ADC_L_SEL_MASK (0x1 << 11)
328 #define RT5616_IF2_ADC_L_SEL_PASS (0x1 << 11)
329 #define RT5616_IF2_ADC_R_SEL_MASK (0x1 << 10)
332 #define RT5616_IF2_ADC_R_SEL_PASS (0x1 << 10)
336 #define RT5616_RXDC_SEL_L2R (0x1 << 8)
342 #define RT5616_RXDP_SEL_L2R (0x1 << 6)
348 #define RT5616_TXDC_SEL_L2R (0x1 << 4)
354 #define RT5616_TXDP_SEL_L2R (0x1 << 2)
373 #define RT5616_M_IN2_L_RM_L (0x1 << 6)
375 #define RT5616_M_IN1_L_RM_L (0x1 << 5)
377 #define RT5616_M_BST3_RM_L (0x1 << 3)
379 #define RT5616_M_BST2_RM_L (0x1 << 2)
381 #define RT5616_M_BST1_RM_L (0x1 << 1)
383 #define RT5616_M_OM_L_RM_L (0x1)
401 #define RT5616_M_IN2_R_RM_R (0x1 << 6)
403 #define RT5616_M_IN1_R_RM_R (0x1 << 5)
405 #define RT5616_M_BST3_RM_R (0x1 << 3)
407 #define RT5616_M_BST2_RM_R (0x1 << 2)
409 #define RT5616_M_BST1_RM_R (0x1 << 1)
411 #define RT5616_M_OM_R_RM_R (0x1)
415 #define RT5616_M_DAC1_HM (0x1 << 14)
417 #define RT5616_M_HPVOL_HM (0x1 << 13)
419 #define RT5616_G_HPOMIX_MASK (0x1 << 12)
433 #define RT5616_M_RM_L_SM_L (0x1 << 5)
435 #define RT5616_M_IN_L_SM_L (0x1 << 4)
437 #define RT5616_M_DAC_L1_SM_L (0x1 << 3)
439 #define RT5616_M_DAC_L2_SM_L (0x1 << 2)
441 #define RT5616_M_OM_L_SM_L (0x1 << 1)
455 #define RT5616_M_RM_R_SM_R (0x1 << 5)
457 #define RT5616_M_IN_R_SM_R (0x1 << 4)
459 #define RT5616_M_DAC_R1_SM_R (0x1 << 3)
461 #define RT5616_M_DAC_R2_SM_R (0x1 << 2)
463 #define RT5616_M_OM_R_SM_R (0x1 << 1)
467 #define RT5616_M_DAC_R1_SPM_L (0x1 << 15)
469 #define RT5616_M_DAC_L1_SPM_L (0x1 << 14)
471 #define RT5616_M_SV_R_SPM_L (0x1 << 13)
473 #define RT5616_M_SV_L_SPM_L (0x1 << 12)
475 #define RT5616_M_BST1_SPM_L (0x1 << 11)
479 #define RT5616_M_DAC_R1_SPM_R (0x1 << 13)
481 #define RT5616_M_SV_R_SPM_R (0x1 << 12)
483 #define RT5616_M_BST1_SPM_R (0x1 << 11)
491 #define RT5616_M_DAC_R2_MM (0x1 << 15)
493 #define RT5616_M_DAC_L2_MM (0x1 << 14)
495 #define RT5616_M_OV_R_MM (0x1 << 13)
497 #define RT5616_M_OV_L_MM (0x1 << 12)
499 #define RT5616_M_BST1_MM (0x1 << 11)
501 #define RT5616_G_MONOMIX_MASK (0x1 << 10)
521 #define RT5616_M_IN2_L_OM_L (0x1 << 9)
523 #define RT5616_M_BST2_OM_L (0x1 << 6)
525 #define RT5616_M_BST1_OM_L (0x1 << 5)
527 #define RT5616_M_IN1_L_OM_L (0x1 << 4)
529 #define RT5616_M_RM_L_OM_L (0x1 << 3)
531 #define RT5616_M_DAC_L1_OM_L (0x1)
551 #define RT5616_M_IN2_R_OM_R (0x1 << 9)
553 #define RT5616_M_BST2_OM_R (0x1 << 6)
555 #define RT5616_M_BST1_OM_R (0x1 << 5)
557 #define RT5616_M_IN1_R_OM_R (0x1 << 4)
559 #define RT5616_M_RM_R_OM_R (0x1 << 3)
561 #define RT5616_M_DAC_R1_OM_R (0x1)
565 #define RT5616_M_DAC_L1_LM (0x1 << 15)
567 #define RT5616_M_DAC_R1_LM (0x1 << 14)
569 #define RT5616_M_OV_L_LM (0x1 << 13)
571 #define RT5616_M_OV_R_LM (0x1 << 12)
573 #define RT5616_G_LOUTMIX_MASK (0x1 << 11)
577 #define RT5616_PWR_I2S1 (0x1 << 15)
579 #define RT5616_PWR_I2S2 (0x1 << 14)
581 #define RT5616_PWR_DAC_L1 (0x1 << 12)
583 #define RT5616_PWR_DAC_R1 (0x1 << 11)
585 #define RT5616_PWR_ADC_L (0x1 << 2)
587 #define RT5616_PWR_ADC_R (0x1 << 1)
591 #define RT5616_PWR_ADC_STO1_F (0x1 << 15)
593 #define RT5616_PWR_DAC_STO1_F (0x1 << 11)
597 #define RT5616_PWR_VREF1 (0x1 << 15)
599 #define RT5616_PWR_FV1 (0x1 << 14)
601 #define RT5616_PWR_MB (0x1 << 13)
603 #define RT5616_PWR_LM (0x1 << 12)
605 #define RT5616_PWR_BG (0x1 << 11)
607 #define RT5616_PWR_HP_L (0x1 << 7)
609 #define RT5616_PWR_HP_R (0x1 << 6)
611 #define RT5616_PWR_HA (0x1 << 5)
613 #define RT5616_PWR_VREF2 (0x1 << 4)
615 #define RT5616_PWR_FV2 (0x1 << 3)
617 #define RT5616_PWR_LDO (0x1 << 2)
626 #define RT5616_PWR_BST1 (0x1 << 15)
628 #define RT5616_PWR_BST2 (0x1 << 14)
630 #define RT5616_PWR_MB1 (0x1 << 11)
632 #define RT5616_PWR_PLL (0x1 << 9)
634 #define RT5616_PWR_BST1_OP2 (0x1 << 5)
636 #define RT5616_PWR_BST2_OP2 (0x1 << 4)
638 #define RT5616_PWR_BST3_OP2 (0x1 << 3)
640 #define RT5616_PWR_JD_M (0x1 << 2)
642 #define RT5616_PWR_JD2 (0x1 << 1)
644 #define RT5616_PWR_JD3 (0x1)
648 #define RT5616_PWR_OM_L (0x1 << 15)
650 #define RT5616_PWR_OM_R (0x1 << 14)
652 #define RT5616_PWR_RM_L (0x1 << 11)
654 #define RT5616_PWR_RM_R (0x1 << 10)
658 #define RT5616_PWR_OV_L (0x1 << 13)
660 #define RT5616_PWR_OV_R (0x1 << 12)
662 #define RT5616_PWR_HV_L (0x1 << 11)
664 #define RT5616_PWR_HV_R (0x1 << 10)
666 #define RT5616_PWR_IN1_L (0x1 << 9)
668 #define RT5616_PWR_IN1_R (0x1 << 8)
670 #define RT5616_PWR_IN2_L (0x1 << 7)
672 #define RT5616_PWR_IN2_R (0x1 << 6)
676 #define RT5616_I2S_MS_MASK (0x1 << 15)
679 #define RT5616_I2S_MS_S (0x1 << 15)
683 #define RT5616_I2S_O_CP_U_LAW (0x1 << 10)
688 #define RT5616_I2S_I_CP_U_LAW (0x1 << 8)
690 #define RT5616_I2S_BP_MASK (0x1 << 7)
693 #define RT5616_I2S_BP_INV (0x1 << 7)
697 #define RT5616_I2S_DL_20 (0x1 << 2)
703 #define RT5616_I2S_DF_LEFT (0x1)
711 #define RT5616_I2S_PD1_2 (0x1 << 12)
718 #define RT5616_I2S_BCLK_MS2_MASK (0x1 << 11)
722 #define RT5616_DAC_OSR_64 (0x1 << 2)
728 #define RT5616_ADC_OSR_64 (0x1)
733 #define RT5616_DAHPF_EN (0x1 << 11)
735 #define RT5616_ADHPF_EN (0x1 << 10)
739 #define RT5616_TDM_INTEL_SEL_MASK (0x1 << 15)
742 #define RT5616_TDM_INTEL_SEL_50 (0x1 << 15)
743 #define RT5616_TDM_MODE_SEL_MASK (0x1 << 14)
746 #define RT5616_TDM_MODE_SEL_TDM (0x1 << 14)
750 #define RT5616_TDM_CH_NUM_SEL_4 (0x1 << 12)
756 #define RT5616_TDM_CH_LEN_SEL_20 (0x1 << 10)
759 #define RT5616_TDM_ADC_SEL_MASK (0x1 << 9)
762 #define RT5616_TDM_ADC_SEL_SWAP (0x1 << 9)
763 #define RT5616_TDM_ADC_START_SEL_MASK (0x1 << 8)
766 #define RT5616_TDM_ADC_START_SEL_SL4 (0x1 << 8)
770 #define RT5616_TDM_I2S_CH2_SEL_RL (0x1 << 6)
776 #define RT5616_TDM_I2S_CH4_SEL_RL (0x1 << 4)
782 #define RT5616_TDM_I2S_CH6_SEL_RL (0x1 << 2)
788 #define RT5616_TDM_I2S_CH8_SEL_RL (0x1)
793 #define RT5616_TDM_LRCK_POL_SEL_MASK (0x1 << 15)
796 #define RT5616_TDM_LRCK_POL_SEL_INV (0x1 << 15)
797 #define RT5616_TDM_CH_VAL_SEL_MASK (0x1 << 14)
800 #define RT5616_TDM_CH_VAL_SEL_CH0123 (0x1 << 14)
801 #define RT5616_TDM_CH_VAL_EN (0x1 << 13)
803 #define RT5616_TDM_LPBK_EN (0x1 << 12)
805 #define RT5616_TDM_LRCK_PULSE_SEL_MASK (0x1 << 11)
808 #define RT5616_TDM_LRCK_PULSE_SEL_CH (0x1 << 11)
809 #define RT5616_TDM_END_EDGE_SEL_MASK (0x1 << 10)
812 #define RT5616_TDM_END_EDGE_SEL_NEG (0x1 << 10)
813 #define RT5616_TDM_END_EDGE_EN (0x1 << 9)
815 #define RT5616_TDM_TRAN_EDGE_SEL_MASK (0x1 << 8)
818 #define RT5616_TDM_TRAN_EDGE_SEL_NEG (0x1 << 8)
819 #define RT5616_M_TDM2_L (0x1 << 7)
821 #define RT5616_M_TDM2_R (0x1 << 6)
823 #define RT5616_M_TDM4_L (0x1 << 5)
825 #define RT5616_M_TDM4_R (0x1 << 4)
832 #define RT5616_SCLK_SRC_PLL1 (0x1 << 14)
836 #define RT5616_PLL1_SRC_BCLK1 (0x1 << 12)
838 #define RT5616_PLL1_PD_MASK (0x1 << 3)
841 #define RT5616_PLL1_PD_2 (0x1 << 3)
857 #define RT5616_PLL_M_BP (0x1 << 11)
861 #define RT5616_STO1_T_MASK (0x1 << 15)
864 #define RT5616_STO1_T_LRCK1 (0x1 << 15)
865 #define RT5616_STO2_T_MASK (0x1 << 12)
868 #define RT5616_STO2_T_LRCK2 (0x1 << 12)
869 #define RT5616_ASRC2_REF_MASK (0x1 << 11)
872 #define RT5616_ASRC2_REF_LRCK1 (0x1 << 11)
873 #define RT5616_DMIC_1_M_MASK (0x1 << 9)
876 #define RT5616_DMIC_1_M_ASYN (0x1 << 9)
879 #define RT5616_STO1_ASRC_EN (0x1 << 15)
881 #define RT5616_STO2_ASRC_EN (0x1 << 14)
883 #define RT5616_STO1_DAC_M_MASK (0x1 << 13)
886 #define RT5616_STO1_DAC_M_ASRC (0x1 << 13)
887 #define RT5616_STO2_DAC_M_MASK (0x1 << 12)
890 #define RT5616_STO2_DAC_M_ASRC (0x1 << 12)
891 #define RT5616_ADC_M_MASK (0x1 << 11)
894 #define RT5616_ADC_M_ASRC (0x1 << 11)
895 #define RT5616_I2S1_R_D_MASK (0x1 << 4)
898 #define RT5616_I2S1_R_D_EN (0x1 << 4)
899 #define RT5616_I2S2_R_D_MASK (0x1 << 3)
902 #define RT5616_I2S2_R_D_EN (0x1 << 3)
906 #define RT5616_PRE_SCLK_1024 (0x1)
914 #define RT5616_G_ASRC_LP_MASK (0x1 << 3)
916 #define RT5616_ASRC_LP_F_M (0x1 << 2)
919 #define RT5616_ASRC_LP_F_SB (0x1 << 2)
923 #define RT5616_FTK_PH_DET_DIV2 (0x1)
940 #define RT5616_HP_OVCD_MASK (0x1 << 10)
943 #define RT5616_HP_OVCD_EN (0x1 << 10)
947 #define RT5616_HP_OC_TH_105 (0x1 << 8)
952 #define RT5616_SMT_TRIG_MASK (0x1 << 15)
955 #define RT5616_SMT_TRIG_EN (0x1 << 15)
956 #define RT5616_HP_L_SMT_MASK (0x1 << 9)
959 #define RT5616_HP_L_SMT_EN (0x1 << 9)
960 #define RT5616_HP_R_SMT_MASK (0x1 << 8)
963 #define RT5616_HP_R_SMT_EN (0x1 << 8)
964 #define RT5616_HP_CD_PD_MASK (0x1 << 7)
967 #define RT5616_HP_CD_PD_EN (0x1 << 7)
968 #define RT5616_RSTN_MASK (0x1 << 6)
971 #define RT5616_RSTN_EN (0x1 << 6)
972 #define RT5616_RSTP_MASK (0x1 << 5)
975 #define RT5616_RSTP_EN (0x1 << 5)
976 #define RT5616_HP_CO_MASK (0x1 << 4)
979 #define RT5616_HP_CO_EN (0x1 << 4)
980 #define RT5616_HP_CP_MASK (0x1 << 3)
983 #define RT5616_HP_CP_PU (0x1 << 3)
984 #define RT5616_HP_SG_MASK (0x1 << 2)
987 #define RT5616_HP_SG_EN (0x1 << 2)
988 #define RT5616_HP_DP_MASK (0x1 << 1)
991 #define RT5616_HP_DP_PU (0x1 << 1)
992 #define RT5616_HP_CB_MASK (0x1)
995 #define RT5616_HP_CB_PU (0x1)
998 #define RT5616_DEPOP_MASK (0x1 << 13)
1001 #define RT5616_DEPOP_MAN (0x1 << 13)
1002 #define RT5616_RAMP_MASK (0x1 << 12)
1005 #define RT5616_RAMP_EN (0x1 << 12)
1006 #define RT5616_BPS_MASK (0x1 << 11)
1009 #define RT5616_BPS_EN (0x1 << 11)
1010 #define RT5616_FAST_UPDN_MASK (0x1 << 10)
1013 #define RT5616_FAST_UPDN_EN (0x1 << 10)
1017 #define RT5616_MRES_25MO (0x1 << 8)
1020 #define RT5616_VLO_MASK (0x1 << 7)
1023 #define RT5616_VLO_32V (0x1 << 7)
1024 #define RT5616_DIG_DP_MASK (0x1 << 6)
1027 #define RT5616_DIG_DP_EN (0x1 << 6)
1050 #define RT5616_OSW_L_MASK (0x1 << 11)
1053 #define RT5616_OSW_L_EN (0x1 << 11)
1054 #define RT5616_OSW_R_MASK (0x1 << 10)
1057 #define RT5616_OSW_R_EN (0x1 << 10)
1061 #define RT5616_PM_HP_MV (0x1 << 8)
1066 #define RT5616_IB_HP_25IL (0x1 << 6)
1071 #define RT5616_MIC1_BS_MASK (0x1 << 15)
1074 #define RT5616_MIC1_BS_75AV (0x1 << 15)
1075 #define RT5616_MIC1_CLK_MASK (0x1 << 13)
1078 #define RT5616_MIC1_CLK_EN (0x1 << 13)
1079 #define RT5616_MIC1_OVCD_MASK (0x1 << 11)
1082 #define RT5616_MIC1_OVCD_EN (0x1 << 11)
1086 #define RT5616_MIC1_OVTH_1500UA (0x1 << 9)
1088 #define RT5616_PWR_MB_MASK (0x1 << 5)
1091 #define RT5616_PWR_MB_PU (0x1 << 5)
1092 #define RT5616_PWR_CLK12M_MASK (0x1 << 4)
1095 #define RT5616_PWR_CLK12M_PU (0x1 << 4)
1100 #define RT5616_JD_PU (0x1 << 11)
1102 #define RT5616_JD_PD (0x1 << 10)
1107 #define RT5616_JD_MODE_SEL_M1 (0x1 << 8)
1111 #define RT5616_JD_M_PU (0x1 << 3)
1113 #define RT5616_JD_M_PD (0x1 << 2)
1118 #define RT5616_JD_M_MODE_SEL_M1 (0x1)
1126 #define RT5616_EQ_SRC_MASK (0x1 << 15)
1129 #define RT5616_EQ_SRC_ADC (0x1 << 15)
1130 #define RT5616_EQ_UPD (0x1 << 14)
1132 #define RT5616_EQ_CD_MASK (0x1 << 13)
1135 #define RT5616_EQ_CD_EN (0x1 << 13)
1139 #define RT5616_EQ_DITH_LSB (0x1 << 8)
1142 #define RT5616_EQ_CD_F (0x1 << 7)
1144 #define RT5616_EQ_STA_HP2 (0x1 << 6)
1146 #define RT5616_EQ_STA_HP1 (0x1 << 5)
1148 #define RT5616_EQ_STA_BP4 (0x1 << 4)
1150 #define RT5616_EQ_STA_BP3 (0x1 << 3)
1152 #define RT5616_EQ_STA_BP2 (0x1 << 2)
1154 #define RT5616_EQ_STA_BP1 (0x1 << 1)
1156 #define RT5616_EQ_STA_LP (0x1)
1160 #define RT5616_EQ_HPF1_M_MASK (0x1 << 8)
1163 #define RT5616_EQ_HPF1_M_1ST (0x1 << 8)
1164 #define RT5616_EQ_LPF1_M_MASK (0x1 << 7)
1167 #define RT5616_EQ_LPF1_M_1ST (0x1 << 7)
1168 #define RT5616_EQ_HPF2_MASK (0x1 << 6)
1171 #define RT5616_EQ_HPF2_EN (0x1 << 6)
1172 #define RT5616_EQ_HPF1_MASK (0x1 << 5)
1175 #define RT5616_EQ_HPF1_EN (0x1 << 5)
1176 #define RT5616_EQ_BPF4_MASK (0x1 << 4)
1179 #define RT5616_EQ_BPF4_EN (0x1 << 4)
1180 #define RT5616_EQ_BPF3_MASK (0x1 << 3)
1183 #define RT5616_EQ_BPF3_EN (0x1 << 3)
1184 #define RT5616_EQ_BPF2_MASK (0x1 << 2)
1187 #define RT5616_EQ_BPF2_EN (0x1 << 2)
1188 #define RT5616_EQ_BPF1_MASK (0x1 << 1)
1191 #define RT5616_EQ_BPF1_EN (0x1 << 1)
1192 #define RT5616_EQ_LPF_MASK (0x1)
1195 #define RT5616_EQ_LPF_EN (0x1)
1199 #define RT5616_MT_MASK (0x1 << 15)
1202 #define RT5616_MT_EN (0x1 << 15)
1205 #define RT5616_DRC_AGC_P_MASK (0x1 << 15)
1208 #define RT5616_DRC_AGC_P_ADC (0x1 << 15)
1209 #define RT5616_DRC_AGC_MASK (0x1 << 14)
1212 #define RT5616_DRC_AGC_EN (0x1 << 14)
1213 #define RT5616_DRC_AGC_UPD (0x1 << 13)
1219 #define RT5616_DRC_AGC_R_48K (0x1 << 5)
1231 #define RT5616_DRC_AGC_CP_MASK (0x1 << 7)
1234 #define RT5616_DRC_AGC_CP_EN (0x1 << 7)
1238 #define RT5616_DRC_AGC_CPR_1_2 (0x1 << 5)
1249 #define RT5616_DRC_AGC_NG_MASK (0x1 << 6)
1252 #define RT5616_DRC_AGC_NG_EN (0x1 << 6)
1253 #define RT5616_DRC_AGC_NGH_MASK (0x1 << 5)
1256 #define RT5616_DRC_AGC_NGH_EN (0x1 << 5)
1264 #define RT5616_JD_GPIO1 (0x1 << 13)
1270 #define RT5616_JD_HP_MASK (0x1 << 11)
1273 #define RT5616_JD_HP_EN (0x1 << 11)
1274 #define RT5616_JD_HP_TRG_MASK (0x1 << 10)
1277 #define RT5616_JD_HP_TRG_HI (0x1 << 10)
1278 #define RT5616_JD_SPL_MASK (0x1 << 9)
1281 #define RT5616_JD_SPL_EN (0x1 << 9)
1282 #define RT5616_JD_SPL_TRG_MASK (0x1 << 8)
1285 #define RT5616_JD_SPL_TRG_HI (0x1 << 8)
1286 #define RT5616_JD_SPR_MASK (0x1 << 7)
1289 #define RT5616_JD_SPR_EN (0x1 << 7)
1290 #define RT5616_JD_SPR_TRG_MASK (0x1 << 6)
1293 #define RT5616_JD_SPR_TRG_HI (0x1 << 6)
1294 #define RT5616_JD_LO_MASK (0x1 << 3)
1297 #define RT5616_JD_LO_EN (0x1 << 3)
1298 #define RT5616_JD_LO_TRG_MASK (0x1 << 2)
1301 #define RT5616_JD_LO_TRG_HI (0x1 << 2)
1307 #define RT5616_JD_TRG_SEL_JD1_1 (0x1 << 9)
1311 #define RT5616_JD3_IRQ_EN (0x1 << 8)
1313 #define RT5616_JD3_EN_STKY (0x1 << 7)
1315 #define RT5616_JD3_INV (0x1 << 6)
1319 #define RT5616_IRQ_JD_MASK (0x1 << 15)
1322 #define RT5616_IRQ_JD_NOR (0x1 << 15)
1323 #define RT5616_JD_STKY_MASK (0x1 << 13)
1326 #define RT5616_JD_STKY_EN (0x1 << 13)
1327 #define RT5616_JD_P_MASK (0x1 << 11)
1330 #define RT5616_JD_P_INV (0x1 << 11)
1331 #define RT5616_JD1_1_IRQ_EN (0x1 << 9)
1333 #define RT5616_JD1_1_EN_STKY (0x1 << 8)
1335 #define RT5616_JD1_1_INV (0x1 << 7)
1337 #define RT5616_JD1_2_IRQ_EN (0x1 << 6)
1339 #define RT5616_JD1_2_EN_STKY (0x1 << 5)
1341 #define RT5616_JD1_2_INV (0x1 << 4)
1343 #define RT5616_JD2_IRQ_EN (0x1 << 3)
1345 #define RT5616_JD2_EN_STKY (0x1 << 2)
1347 #define RT5616_JD2_INV (0x1 << 1)
1351 #define RT5616_IRQ_MB1_OC_MASK (0x1 << 15)
1354 #define RT5616_IRQ_MB1_OC_NOR (0x1 << 15)
1355 #define RT5616_MB1_OC_STKY_MASK (0x1 << 11)
1358 #define RT5616_MB1_OC_STKY_EN (0x1 << 11)
1359 #define RT5616_MB1_OC_P_MASK (0x1 << 7)
1362 #define RT5616_MB1_OC_P_INV (0x1 << 7)
1363 #define RT5616_MB2_OC_P_MASK (0x1 << 6)
1364 #define RT5616_MB1_OC_CLR (0x1 << 3)
1366 #define RT5616_STA_GPIO8 (0x1)
1370 #define RT5616_STA_JD3 (0x1 << 15)
1372 #define RT5616_STA_JD2 (0x1 << 14)
1374 #define RT5616_STA_JD1_2 (0x1 << 13)
1376 #define RT5616_STA_JD1_1 (0x1 << 12)
1378 #define RT5616_STA_GP7 (0x1 << 11)
1380 #define RT5616_STA_GP6 (0x1 << 10)
1382 #define RT5616_STA_GP5 (0x1 << 9)
1384 #define RT5616_STA_GP1 (0x1 << 8)
1386 #define RT5616_STA_GP2 (0x1 << 7)
1388 #define RT5616_STA_GP3 (0x1 << 6)
1390 #define RT5616_STA_GP4 (0x1 << 5)
1392 #define RT5616_STA_GP_JD (0x1 << 4)
1396 #define RT5616_GP1_PIN_MASK (0x1 << 15)
1399 #define RT5616_GP1_PIN_IRQ (0x1 << 15)
1400 #define RT5616_GP2_PIN_MASK (0x1 << 14)
1403 #define RT5616_GP2_PIN_DMIC1_SCL (0x1 << 14)
1404 #define RT5616_GPIO_M_MASK (0x1 << 9)
1407 #define RT5616_GPIO_M_PH (0x1 << 9)
1408 #define RT5616_I2S2_SEL_MASK (0x1 << 8)
1411 #define RT5616_I2S2_SEL_GPIO (0x1 << 8)
1412 #define RT5616_GP5_PIN_MASK (0x1 << 7)
1415 #define RT5616_GP5_PIN_IRQ (0x1 << 7)
1416 #define RT5616_GP6_PIN_MASK (0x1 << 6)
1419 #define RT5616_GP6_PIN_DMIC_SDA (0x1 << 6)
1420 #define RT5616_GP7_PIN_MASK (0x1 << 5)
1423 #define RT5616_GP7_PIN_IRQ (0x1 << 5)
1424 #define RT5616_GP8_PIN_MASK (0x1 << 4)
1427 #define RT5616_GP8_PIN_DMIC_SDA (0x1 << 4)
1428 #define RT5616_GPIO_PDM_SEL_MASK (0x1 << 3)
1431 #define RT5616_GPIO_PDM_SEL_PDM (0x1 << 3)
1434 #define RT5616_GP5_DR_MASK (0x1 << 14)
1437 #define RT5616_GP5_DR_OUT (0x1 << 14)
1438 #define RT5616_GP5_OUT_MASK (0x1 << 13)
1441 #define RT5616_GP5_OUT_HI (0x1 << 13)
1442 #define RT5616_GP5_P_MASK (0x1 << 12)
1445 #define RT5616_GP5_P_INV (0x1 << 12)
1446 #define RT5616_GP4_DR_MASK (0x1 << 11)
1449 #define RT5616_GP4_DR_OUT (0x1 << 11)
1450 #define RT5616_GP4_OUT_MASK (0x1 << 10)
1453 #define RT5616_GP4_OUT_HI (0x1 << 10)
1454 #define RT5616_GP4_P_MASK (0x1 << 9)
1457 #define RT5616_GP4_P_INV (0x1 << 9)
1458 #define RT5616_GP3_DR_MASK (0x1 << 8)
1461 #define RT5616_GP3_DR_OUT (0x1 << 8)
1462 #define RT5616_GP3_OUT_MASK (0x1 << 7)
1465 #define RT5616_GP3_OUT_HI (0x1 << 7)
1466 #define RT5616_GP3_P_MASK (0x1 << 6)
1469 #define RT5616_GP3_P_INV (0x1 << 6)
1470 #define RT5616_GP2_DR_MASK (0x1 << 5)
1473 #define RT5616_GP2_DR_OUT (0x1 << 5)
1474 #define RT5616_GP2_OUT_MASK (0x1 << 4)
1477 #define RT5616_GP2_OUT_HI (0x1 << 4)
1478 #define RT5616_GP2_P_MASK (0x1 << 3)
1481 #define RT5616_GP2_P_INV (0x1 << 3)
1482 #define RT5616_GP1_DR_MASK (0x1 << 2)
1485 #define RT5616_GP1_DR_OUT (0x1 << 2)
1486 #define RT5616_GP1_OUT_MASK (0x1 << 1)
1489 #define RT5616_GP1_OUT_HI (0x1 << 1)
1490 #define RT5616_GP1_P_MASK (0x1)
1493 #define RT5616_GP1_P_INV (0x1)
1496 #define RT5616_GP8_DR_MASK (0x1 << 8)
1499 #define RT5616_GP8_DR_OUT (0x1 << 8)
1500 #define RT5616_GP8_OUT_MASK (0x1 << 7)
1503 #define RT5616_GP8_OUT_HI (0x1 << 7)
1504 #define RT5616_GP8_P_MASK (0x1 << 6)
1507 #define RT5616_GP8_P_INV (0x1 << 6)
1508 #define RT5616_GP7_DR_MASK (0x1 << 5)
1511 #define RT5616_GP7_DR_OUT (0x1 << 5)
1512 #define RT5616_GP7_OUT_MASK (0x1 << 4)
1515 #define RT5616_GP7_OUT_HI (0x1 << 4)
1516 #define RT5616_GP7_P_MASK (0x1 << 3)
1519 #define RT5616_GP7_P_INV (0x1 << 3)
1520 #define RT5616_GP6_DR_MASK (0x1 << 2)
1523 #define RT5616_GP6_DR_OUT (0x1 << 2)
1524 #define RT5616_GP6_OUT_MASK (0x1 << 1)
1527 #define RT5616_GP6_OUT_HI (0x1 << 1)
1528 #define RT5616_GP6_P_MASK (0x1)
1531 #define RT5616_GP6_P_INV (0x1)
1534 #define RT5616_SCB_SWAP_MASK (0x1 << 15)
1537 #define RT5616_SCB_SWAP_EN (0x1 << 15)
1538 #define RT5616_SCB_MASK (0x1 << 14)
1541 #define RT5616_SCB_EN (0x1 << 14)
1544 #define RT5616_BB_MASK (0x1 << 15)
1547 #define RT5616_BB_EN (0x1 << 15)
1551 #define RT5616_BB_CT_B (0x1 << 12)
1554 #define RT5616_M_BB_L_MASK (0x1 << 9)
1556 #define RT5616_M_BB_R_MASK (0x1 << 8)
1558 #define RT5616_M_BB_HPF_L_MASK (0x1 << 7)
1560 #define RT5616_M_BB_HPF_R_MASK (0x1 << 6)
1566 #define RT5616_M_MP3_L_MASK (0x1 << 15)
1568 #define RT5616_M_MP3_R_MASK (0x1 << 14)
1570 #define RT5616_M_MP3_MASK (0x1 << 13)
1573 #define RT5616_M_MP3_EN (0x1 << 13)
1576 #define RT5616_MP3_HLP_MASK (0x1 << 7)
1579 #define RT5616_MP3_HLP_EN (0x1 << 7)
1580 #define RT5616_M_MP3_ORG_L_MASK (0x1 << 6)
1582 #define RT5616_M_MP3_ORG_R_MASK (0x1 << 5)
1586 #define RT5616_MP3_WT_MASK (0x1 << 13)
1589 #define RT5616_MP3_WT_1_2 (0x1 << 13)
1596 #define RT5616_3D_CF_MASK (0x1 << 15)
1599 #define RT5616_3D_CF_EN (0x1 << 15)
1600 #define RT5616_3D_HP_MASK (0x1 << 14)
1603 #define RT5616_3D_HP_EN (0x1 << 14)
1604 #define RT5616_3D_BT_MASK (0x1 << 13)
1607 #define RT5616_3D_BT_EN (0x1 << 13)
1610 #define RT5616_3D_HP_M_MASK (0x1 << 10)
1613 #define RT5616_3D_HP_M_FRO (0x1 << 10)
1614 #define RT5616_M_3D_HRTF_MASK (0x1 << 9)
1616 #define RT5616_M_3D_D2H_MASK (0x1 << 8)
1618 #define RT5616_M_3D_D2R_MASK (0x1 << 7)
1620 #define RT5616_M_3D_REVB_MASK (0x1 << 6)
1624 #define RT5616_2ND_HPF_MASK (0x1 << 15)
1627 #define RT5616_2ND_HPF_EN (0x1 << 15)
1637 #define RT5616_ZD_F_ZC_IM (0x1 << 4)
1648 #define RT5616_SI_DAC_MASK (0x1 << 11)
1651 #define RT5616_SI_DAC_TEST (0x1 << 11)
1652 #define RT5616_DC_CAL_M_MASK (0x1 << 10)
1655 #define RT5616_DC_CAL_M_CAL (0x1 << 10)
1656 #define RT5616_DC_CAL_MASK (0x1 << 9)
1659 #define RT5616_DC_CAL_EN (0x1 << 9)
1662 #define RT5616_HPD_PS_MASK (0x1 << 5)
1665 #define RT5616_HPD_PS_EN (0x1 << 5)
1666 #define RT5616_CAL_M_MASK (0x1 << 4)
1669 #define RT5616_CAL_M_CAL (0x1 << 4)
1670 #define RT5616_CAL_MASK (0x1 << 3)
1673 #define RT5616_CAL_EN (0x1 << 3)
1674 #define RT5616_CAL_TEST_MASK (0x1 << 2)
1677 #define RT5616_CAL_TEST_EN (0x1 << 2)
1681 #define RT5616_CAL_P_CAL (0x1)
1685 #define RT5616_SV_MASK (0x1 << 15)
1688 #define RT5616_SV_EN (0x1 << 15)
1689 #define RT5616_OUT_SV_MASK (0x1 << 13)
1692 #define RT5616_OUT_SV_EN (0x1 << 13)
1693 #define RT5616_HP_SV_MASK (0x1 << 12)
1696 #define RT5616_HP_SV_EN (0x1 << 12)
1697 #define RT5616_ZCD_DIG_MASK (0x1 << 11)
1700 #define RT5616_ZCD_DIG_EN (0x1 << 11)
1701 #define RT5616_ZCD_MASK (0x1 << 10)
1704 #define RT5616_ZCD_PU (0x1 << 10)
1707 #define RT5616_M_ZCD_OM_L (0x1 << 7)
1708 #define RT5616_M_ZCD_OM_R (0x1 << 6)
1709 #define RT5616_M_ZCD_RM_L (0x1 << 5)
1710 #define RT5616_M_ZCD_RM_R (0x1 << 4)
1715 #define RT5616_ZCD_HP_MASK (0x1 << 15)
1718 #define RT5616_ZCD_HP_EN (0x1 << 15)
1721 #define RT5616_I2S2_MS_SP_MASK (0x1 << 8)
1724 #define RT5616_I2S2_MS_SP_50 (0x1 << 8)
1725 #define RT5616_CLK_DET_EN (0x1 << 3)
1727 #define RT5616_AMP_DET_EN (0x1 << 1)
1729 #define RT5616_D_GATE_EN (0x1)
1734 #define RT5616_3D_SPK_MASK (0x1 << 15)
1737 #define RT5616_3D_SPK_EN (0x1 << 15)
1746 #define RT5616_WND_MASK (0x1 << 15)
1749 #define RT5616_WND_EN (0x1 << 15)
1772 #define RT5616_WND_WIND_MASK (0x1 << 13) /* Read-Only */
1774 #define RT5616_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
1785 #define RT5616_DP_SPK_MASK (0x1 << 10)
1788 #define RT5616_DP_SPK_EN (0x1 << 10)