Lines Matching full:x1
140 #define AUXADC_RQST_CH0_MASK 0x1
141 #define AUXADC_RQST_CH0_MASK_SFT (0x1 << 0)
145 #define AUXADC_ACCDET_ANASWCTRL_EN_MASK 0x1
146 #define AUXADC_ACCDET_ANASWCTRL_EN_MASK_SFT (0x1 << 6)
151 #define AUXADC_ACCDET_AUTO_SPL_MASK 0x1
152 #define AUXADC_ACCDET_AUTO_SPL_MASK_SFT (0x1 << 0)
156 #define AUXADC_ACCDET_AUTO_RQST_CLR_MASK 0x1
157 #define AUXADC_ACCDET_AUTO_RQST_CLR_MASK_SFT (0x1 << 1)
172 #define RG_ACCDET_CK_PDN_MASK 0x1
173 #define RG_ACCDET_CK_PDN_MASK_SFT (0x1 << 0)
178 #define RG_ACCDET_RST_MASK 0x1
179 #define RG_ACCDET_RST_MASK_SFT (0x1 << 1)
183 #define BANK_ACCDET_SWRST_MASK 0x1
184 #define BANK_ACCDET_SWRST_MASK_SFT (0x1 << 0)
189 #define RG_INT_EN_ACCDET_MASK 0x1
190 #define RG_INT_EN_ACCDET_MASK_SFT (0x1 << 5)
194 #define RG_INT_EN_ACCDET_EINT0_MASK 0x1
195 #define RG_INT_EN_ACCDET_EINT0_MASK_SFT (0x1 << 6)
199 #define RG_INT_EN_ACCDET_EINT1_MASK 0x1
200 #define RG_INT_EN_ACCDET_EINT1_MASK_SFT (0x1 << 7)
205 #define RG_INT_MASK_ACCDET_MASK 0x1
206 #define RG_INT_MASK_ACCDET_MASK_SFT (0x1 << 5)
210 #define RG_INT_MASK_ACCDET_EINT0_MASK 0x1
211 #define RG_INT_MASK_ACCDET_EINT0_MASK_SFT (0x1 << 6)
215 #define RG_INT_MASK_ACCDET_EINT1_MASK 0x1
216 #define RG_INT_MASK_ACCDET_EINT1_MASK_SFT (0x1 << 7)
221 #define RG_INT_STATUS_ACCDET_MASK 0x1
222 #define RG_INT_STATUS_ACCDET_MASK_SFT (0x1 << 5)
226 #define RG_INT_STATUS_ACCDET_EINT0_MASK 0x1
227 #define RG_INT_STATUS_ACCDET_EINT0_MASK_SFT (0x1 << 6)
231 #define RG_INT_STATUS_ACCDET_EINT1_MASK 0x1
232 #define RG_INT_STATUS_ACCDET_EINT1_MASK_SFT (0x1 << 7)
237 #define RG_INT_RAW_STATUS_ACCDET_MASK 0x1
238 #define RG_INT_RAW_STATUS_ACCDET_MASK_SFT (0x1 << 5)
242 #define RG_INT_RAW_STATUS_ACCDET_EINT0_MASK 0x1
243 #define RG_INT_RAW_STATUS_ACCDET_EINT0_MASK_SFT (0x1 << 6)
247 #define RG_INT_RAW_STATUS_ACCDET_EINT1_MASK 0x1
248 #define RG_INT_RAW_STATUS_ACCDET_EINT1_MASK_SFT (0x1 << 7)
253 #define RG_AUDACCDETMICBIAS0PULLLOW_MASK 0x1
254 #define RG_AUDACCDETMICBIAS0PULLLOW_MASK_SFT (0x1 << 0)
258 #define RG_AUDACCDETMICBIAS1PULLLOW_MASK 0x1
259 #define RG_AUDACCDETMICBIAS1PULLLOW_MASK_SFT (0x1 << 1)
263 #define RG_AUDACCDETMICBIAS2PULLLOW_MASK 0x1
264 #define RG_AUDACCDETMICBIAS2PULLLOW_MASK_SFT (0x1 << 2)
268 #define RG_AUDACCDETVIN1PULLLOW_MASK 0x1
269 #define RG_AUDACCDETVIN1PULLLOW_MASK_SFT (0x1 << 3)
273 #define RG_AUDACCDETVTHACAL_MASK 0x1
274 #define RG_AUDACCDETVTHACAL_MASK_SFT (0x1 << 4)
278 #define RG_AUDACCDETVTHBCAL_MASK 0x1
279 #define RG_AUDACCDETVTHBCAL_MASK_SFT (0x1 << 5)
283 #define RG_AUDACCDETTVDET_MASK 0x1
284 #define RG_AUDACCDETTVDET_MASK_SFT (0x1 << 6)
288 #define RG_ACCDETSEL_MASK 0x1
289 #define RG_ACCDETSEL_MASK_SFT (0x1 << 7)
294 #define RG_AUDPWDBMICBIAS1_MASK 0x1
295 #define RG_AUDPWDBMICBIAS1_MASK_SFT (0x1 << 0)
299 #define RG_AUDMICBIAS1BYPASSEN_MASK 0x1
300 #define RG_AUDMICBIAS1BYPASSEN_MASK_SFT (0x1 << 1)
304 #define RG_AUDMICBIAS1LOWPEN_MASK 0x1
305 #define RG_AUDMICBIAS1LOWPEN_MASK_SFT (0x1 << 2)
314 #define RG_AUDMICBIAS1DCSW1PEN_MASK 0x1
315 #define RG_AUDMICBIAS1DCSW1PEN_MASK_SFT (0x1 << 8)
319 #define RG_AUDMICBIAS1DCSW1NEN_MASK 0x1
320 #define RG_AUDMICBIAS1DCSW1NEN_MASK_SFT (0x1 << 9)
324 #define RG_BANDGAPGEN_MASK 0x1
325 #define RG_BANDGAPGEN_MASK_SFT (0x1 << 10)
329 #define RG_AUDMICBIAS1HVEN_MASK 0x1
330 #define RG_AUDMICBIAS1HVEN_MASK_SFT (0x1 << 12)
334 #define RG_AUDMICBIAS1HVVREF_MASK 0x1
335 #define RG_AUDMICBIAS1HVVREF_MASK_SFT (0x1 << 13)
340 #define RG_EINT0NOHYS_MASK 0x1
341 #define RG_EINT0NOHYS_MASK_SFT (0x1 << 10)
345 #define RG_EINT0CONFIGACCDET_MASK 0x1
346 #define RG_EINT0CONFIGACCDET_MASK_SFT (0x1 << 11)
350 #define RG_EINT0HIRENB_MASK 0x1
351 #define RG_EINT0HIRENB_MASK_SFT (0x1 << 12)
355 #define RG_ACCDET2AUXRESBYPASS_MASK 0x1
356 #define RG_ACCDET2AUXRESBYPASS_MASK_SFT (0x1 << 13)
360 #define RG_ACCDET2AUXSWEN_MASK 0x1
361 #define RG_ACCDET2AUXSWEN_MASK_SFT (0x1 << 14)
365 #define RG_AUDACCDETMICBIAS3PULLLOW_MASK 0x1
366 #define RG_AUDACCDETMICBIAS3PULLLOW_MASK_SFT (0x1 << 15)
370 #define RG_EINT1CONFIGACCDET_MASK 0x1
371 #define RG_EINT1CONFIGACCDET_MASK_SFT (0x1 << 0)
375 #define RG_EINT1HIRENB_MASK 0x1
376 #define RG_EINT1HIRENB_MASK_SFT (0x1 << 1)
380 #define RG_EINT1NOHYS_MASK 0x1
381 #define RG_EINT1NOHYS_MASK_SFT (0x1 << 2)
387 #define RG_MTEST_EN_MASK 0x1
388 #define RG_MTEST_EN_MASK_SFT (0x1 << 8)
392 #define RG_MTEST_SEL_MASK 0x1
393 #define RG_MTEST_SEL_MASK_SFT (0x1 << 9)
397 #define RG_MTEST_CURRENT_MASK 0x1
398 #define RG_MTEST_CURRENT_MASK_SFT (0x1 << 10)
402 #define RG_ANALOGFDEN_MASK 0x1
403 #define RG_ANALOGFDEN_MASK_SFT (0x1 << 12)
407 #define RG_FDVIN1PPULLLOW_MASK 0x1
408 #define RG_FDVIN1PPULLLOW_MASK_SFT (0x1 << 13)
412 #define RG_FDEINT0TYPE_MASK 0x1
413 #define RG_FDEINT0TYPE_MASK_SFT (0x1 << 14)
417 #define RG_FDEINT1TYPE_MASK 0x1
418 #define RG_FDEINT1TYPE_MASK_SFT (0x1 << 15)
422 #define RG_EINT0CMPEN_MASK 0x1
423 #define RG_EINT0CMPEN_MASK_SFT (0x1 << 0)
427 #define RG_EINT0CMPMEN_MASK 0x1
428 #define RG_EINT0CMPMEN_MASK_SFT (0x1 << 1)
432 #define RG_EINT0EN_MASK 0x1
433 #define RG_EINT0EN_MASK_SFT (0x1 << 2)
437 #define RG_EINT0CEN_MASK 0x1
438 #define RG_EINT0CEN_MASK_SFT (0x1 << 3)
442 #define RG_EINT0INVEN_MASK 0x1
443 #define RG_EINT0INVEN_MASK_SFT (0x1 << 4)
452 #define RG_EINT1CMPEN_MASK 0x1
453 #define RG_EINT1CMPEN_MASK_SFT (0x1 << 8)
457 #define RG_EINT1CMPMEN_MASK 0x1
458 #define RG_EINT1CMPMEN_MASK_SFT (0x1 << 9)
462 #define RG_EINT1EN_MASK 0x1
463 #define RG_EINT1EN_MASK_SFT (0x1 << 10)
467 #define RG_EINT1CEN_MASK 0x1
468 #define RG_EINT1CEN_MASK_SFT (0x1 << 11)
472 #define RG_EINT1INVEN_MASK 0x1
473 #define RG_EINT1INVEN_MASK_SFT (0x1 << 12)
535 #define ACCDET_AUXADC_SEL_MASK 0x1
536 #define ACCDET_AUXADC_SEL_MASK_SFT (0x1 << 0)
540 #define ACCDET_AUXADC_SW_MASK 0x1
541 #define ACCDET_AUXADC_SW_MASK_SFT (0x1 << 1)
545 #define ACCDET_TEST_AUXADC_MASK 0x1
546 #define ACCDET_TEST_AUXADC_MASK_SFT (0x1 << 2)
550 #define ACCDET_AUXADC_ANASWCTRL_SEL_MASK 0x1
551 #define ACCDET_AUXADC_ANASWCTRL_SEL_MASK_SFT (0x1 << 8)
555 #define AUDACCDETAUXADCSWCTRL_SEL_MASK 0x1
556 #define AUDACCDETAUXADCSWCTRL_SEL_MASK_SFT (0x1 << 9)
560 #define AUDACCDETAUXADCSWCTRL_SW_MASK 0x1
561 #define AUDACCDETAUXADCSWCTRL_SW_MASK_SFT (0x1 << 10)
565 #define ACCDET_TEST_ANA_MASK 0x1
566 #define ACCDET_TEST_ANA_MASK_SFT (0x1 << 11)
575 #define ACCDET_SW_EN_MASK 0x1
576 #define ACCDET_SW_EN_MASK_SFT (0x1 << 0)
580 #define ACCDET_SEQ_INIT_MASK 0x1
581 #define ACCDET_SEQ_INIT_MASK_SFT (0x1 << 1)
585 #define ACCDET_EINT0_SW_EN_MASK 0x1
586 #define ACCDET_EINT0_SW_EN_MASK_SFT (0x1 << 2)
590 #define ACCDET_EINT0_SEQ_INIT_MASK 0x1
591 #define ACCDET_EINT0_SEQ_INIT_MASK_SFT (0x1 << 3)
595 #define ACCDET_EINT1_SW_EN_MASK 0x1
596 #define ACCDET_EINT1_SW_EN_MASK_SFT (0x1 << 4)
600 #define ACCDET_EINT1_SEQ_INIT_MASK 0x1
601 #define ACCDET_EINT1_SEQ_INIT_MASK_SFT (0x1 << 5)
605 #define ACCDET_EINT0_INVERTER_SW_EN_MASK 0x1
606 #define ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT (0x1 << 6)
610 #define ACCDET_EINT0_INVERTER_SEQ_INIT_MASK 0x1
611 #define ACCDET_EINT0_INVERTER_SEQ_INIT_MASK_SFT (0x1 << 7)
615 #define ACCDET_EINT1_INVERTER_SW_EN_MASK 0x1
616 #define ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT (0x1 << 8)
620 #define ACCDET_EINT1_INVERTER_SEQ_INIT_MASK 0x1
621 #define ACCDET_EINT1_INVERTER_SEQ_INIT_MASK_SFT (0x1 << 9)
625 #define ACCDET_EINT0_M_SW_EN_MASK 0x1
626 #define ACCDET_EINT0_M_SW_EN_MASK_SFT (0x1 << 10)
630 #define ACCDET_EINT1_M_SW_EN_MASK 0x1
631 #define ACCDET_EINT1_M_SW_EN_MASK_SFT (0x1 << 11)
635 #define ACCDET_EINT_M_DETECT_EN_MASK 0x1
636 #define ACCDET_EINT_M_DETECT_EN_MASK_SFT (0x1 << 12)
640 #define ACCDET_CMP_PWM_EN_MASK 0x1
641 #define ACCDET_CMP_PWM_EN_MASK_SFT (0x1 << 0)
645 #define ACCDET_VTH_PWM_EN_MASK 0x1
646 #define ACCDET_VTH_PWM_EN_MASK_SFT (0x1 << 1)
650 #define ACCDET_MBIAS_PWM_EN_MASK 0x1
651 #define ACCDET_MBIAS_PWM_EN_MASK_SFT (0x1 << 2)
655 #define ACCDET_EINT_EN_PWM_EN_MASK 0x1
656 #define ACCDET_EINT_EN_PWM_EN_MASK_SFT (0x1 << 3)
660 #define ACCDET_EINT_CMPEN_PWM_EN_MASK 0x1
661 #define ACCDET_EINT_CMPEN_PWM_EN_MASK_SFT (0x1 << 4)
665 #define ACCDET_EINT_CMPMEN_PWM_EN_MASK 0x1
666 #define ACCDET_EINT_CMPMEN_PWM_EN_MASK_SFT (0x1 << 5)
670 #define ACCDET_EINT_CTURBO_PWM_EN_MASK 0x1
671 #define ACCDET_EINT_CTURBO_PWM_EN_MASK_SFT (0x1 << 6)
675 #define ACCDET_CMP_PWM_IDLE_MASK 0x1
676 #define ACCDET_CMP_PWM_IDLE_MASK_SFT (0x1 << 8)
680 #define ACCDET_VTH_PWM_IDLE_MASK 0x1
681 #define ACCDET_VTH_PWM_IDLE_MASK_SFT (0x1 << 9)
685 #define ACCDET_MBIAS_PWM_IDLE_MASK 0x1
686 #define ACCDET_MBIAS_PWM_IDLE_MASK_SFT (0x1 << 10)
690 #define ACCDET_EINT0_CMPEN_PWM_IDLE_MASK 0x1
691 #define ACCDET_EINT0_CMPEN_PWM_IDLE_MASK_SFT (0x1 << 11)
695 #define ACCDET_EINT1_CMPEN_PWM_IDLE_MASK 0x1
696 #define ACCDET_EINT1_CMPEN_PWM_IDLE_MASK_SFT (0x1 << 12)
700 #define ACCDET_PWM_EN_SW_MASK 0x1
701 #define ACCDET_PWM_EN_SW_MASK_SFT (0x1 << 13)
725 #define ACCDET_FALL_DELAY_MASK 0x1
726 #define ACCDET_FALL_DELAY_MASK_SFT (0x1 << 15)
845 #define ACCDET_IVAL_SEL_MASK 0x1
846 #define ACCDET_IVAL_SEL_MASK_SFT (0x1 << 12)
850 #define ACCDET_EINT_IVAL_SEL_MASK 0x1
851 #define ACCDET_EINT_IVAL_SEL_MASK_SFT (0x1 << 13)
855 #define ACCDET_EINT_INVERTER_IVAL_CUR_IN_MASK 0x1
856 #define ACCDET_EINT_INVERTER_IVAL_CUR_IN_MASK_SFT (0x1 << 0)
860 #define ACCDET_EINT_INVERTER_IVAL_SAM_IN_MASK 0x1
861 #define ACCDET_EINT_INVERTER_IVAL_SAM_IN_MASK_SFT (0x1 << 1)
865 #define ACCDET_EINT_INVERTER_IVAL_MEM_IN_MASK 0x1
866 #define ACCDET_EINT_INVERTER_IVAL_MEM_IN_MASK_SFT (0x1 << 2)
870 #define ACCDET_EINT_INVERTER_IVAL_SEL_MASK 0x1
871 #define ACCDET_EINT_INVERTER_IVAL_SEL_MASK_SFT (0x1 << 3)
875 #define ACCDET_IRQ_MASK 0x1
876 #define ACCDET_IRQ_MASK_SFT (0x1 << 0)
880 #define ACCDET_EINT0_IRQ_MASK 0x1
881 #define ACCDET_EINT0_IRQ_MASK_SFT (0x1 << 2)
885 #define ACCDET_EINT1_IRQ_MASK 0x1
886 #define ACCDET_EINT1_IRQ_MASK_SFT (0x1 << 3)
890 #define ACCDET_EINT_IN_INVERSE_MASK 0x1
891 #define ACCDET_EINT_IN_INVERSE_MASK_SFT (0x1 << 4)
895 #define ACCDET_IRQ_CLR_MASK 0x1
896 #define ACCDET_IRQ_CLR_MASK_SFT (0x1 << 8)
900 #define ACCDET_EINT0_IRQ_CLR_MASK 0x1
901 #define ACCDET_EINT0_IRQ_CLR_MASK_SFT (0x1 << 10)
905 #define ACCDET_EINT1_IRQ_CLR_MASK 0x1
906 #define ACCDET_EINT1_IRQ_CLR_MASK_SFT (0x1 << 11)
915 #define ACCDET_DA_STABLE_MASK 0x1
916 #define ACCDET_DA_STABLE_MASK_SFT (0x1 << 0)
920 #define ACCDET_EINT0_EN_STABLE_MASK 0x1
921 #define ACCDET_EINT0_EN_STABLE_MASK_SFT (0x1 << 1)
925 #define ACCDET_EINT0_CMPEN_STABLE_MASK 0x1
926 #define ACCDET_EINT0_CMPEN_STABLE_MASK_SFT (0x1 << 2)
930 #define ACCDET_EINT0_CMPMEN_STABLE_MASK 0x1
931 #define ACCDET_EINT0_CMPMEN_STABLE_MASK_SFT (0x1 << 3)
935 #define ACCDET_EINT0_CTURBO_STABLE_MASK 0x1
936 #define ACCDET_EINT0_CTURBO_STABLE_MASK_SFT (0x1 << 4)
940 #define ACCDET_EINT0_CEN_STABLE_MASK 0x1
941 #define ACCDET_EINT0_CEN_STABLE_MASK_SFT (0x1 << 5)
945 #define ACCDET_EINT1_EN_STABLE_MASK 0x1
946 #define ACCDET_EINT1_EN_STABLE_MASK_SFT (0x1 << 6)
950 #define ACCDET_EINT1_CMPEN_STABLE_MASK 0x1
951 #define ACCDET_EINT1_CMPEN_STABLE_MASK_SFT (0x1 << 7)
955 #define ACCDET_EINT1_CMPMEN_STABLE_MASK 0x1
956 #define ACCDET_EINT1_CMPMEN_STABLE_MASK_SFT (0x1 << 8)
960 #define ACCDET_EINT1_CTURBO_STABLE_MASK 0x1
961 #define ACCDET_EINT1_CTURBO_STABLE_MASK_SFT (0x1 << 9)
965 #define ACCDET_EINT1_CEN_STABLE_MASK 0x1
966 #define ACCDET_EINT1_CEN_STABLE_MASK_SFT (0x1 << 10)
970 #define ACCDET_HWMODE_EN_MASK 0x1
971 #define ACCDET_HWMODE_EN_MASK_SFT (0x1 << 0)
980 #define ACCDET_PLUG_OUT_DETECT_MASK 0x1
981 #define ACCDET_PLUG_OUT_DETECT_MASK_SFT (0x1 << 3)
985 #define ACCDET_EINT0_REVERSE_MASK 0x1
986 #define ACCDET_EINT0_REVERSE_MASK_SFT (0x1 << 4)
990 #define ACCDET_EINT1_REVERSE_MASK 0x1
991 #define ACCDET_EINT1_REVERSE_MASK_SFT (0x1 << 5)
995 #define ACCDET_EINT_HWMODE_EN_MASK 0x1
996 #define ACCDET_EINT_HWMODE_EN_MASK_SFT (0x1 << 8)
1000 #define ACCDET_EINT_PLUG_OUT_BYPASS_DEB_MASK 0x1
1001 #define ACCDET_EINT_PLUG_OUT_BYPASS_DEB_MASK_SFT (0x1 << 9)
1005 #define ACCDET_EINT_M_PLUG_IN_EN_MASK 0x1
1006 #define ACCDET_EINT_M_PLUG_IN_EN_MASK_SFT (0x1 << 10)
1010 #define ACCDET_EINT_M_HWMODE_EN_MASK 0x1
1011 #define ACCDET_EINT_M_HWMODE_EN_MASK_SFT (0x1 << 11)
1015 #define ACCDET_TEST_CMPEN_MASK 0x1
1016 #define ACCDET_TEST_CMPEN_MASK_SFT (0x1 << 0)
1020 #define ACCDET_TEST_VTHEN_MASK 0x1
1021 #define ACCDET_TEST_VTHEN_MASK_SFT (0x1 << 1)
1025 #define ACCDET_TEST_MBIASEN_MASK 0x1
1026 #define ACCDET_TEST_MBIASEN_MASK_SFT (0x1 << 2)
1030 #define ACCDET_EINT_TEST_EN_MASK 0x1
1031 #define ACCDET_EINT_TEST_EN_MASK_SFT (0x1 << 3)
1035 #define ACCDET_EINT_TEST_INVEN_MASK 0x1
1036 #define ACCDET_EINT_TEST_INVEN_MASK_SFT (0x1 << 4)
1040 #define ACCDET_EINT_TEST_CMPEN_MASK 0x1
1041 #define ACCDET_EINT_TEST_CMPEN_MASK_SFT (0x1 << 5)
1045 #define ACCDET_EINT_TEST_CMPMEN_MASK 0x1
1046 #define ACCDET_EINT_TEST_CMPMEN_MASK_SFT (0x1 << 6)
1050 #define ACCDET_EINT_TEST_CTURBO_MASK 0x1
1051 #define ACCDET_EINT_TEST_CTURBO_MASK_SFT (0x1 << 7)
1055 #define ACCDET_EINT_TEST_CEN_MASK 0x1
1056 #define ACCDET_EINT_TEST_CEN_MASK_SFT (0x1 << 8)
1060 #define ACCDET_TEST_B_MASK 0x1
1061 #define ACCDET_TEST_B_MASK_SFT (0x1 << 9)
1065 #define ACCDET_TEST_A_MASK 0x1
1066 #define ACCDET_TEST_A_MASK_SFT (0x1 << 10)
1070 #define ACCDET_EINT_TEST_CMPOUT_MASK 0x1
1071 #define ACCDET_EINT_TEST_CMPOUT_MASK_SFT (0x1 << 11)
1075 #define ACCDET_EINT_TEST_CMPMOUT_MASK 0x1
1076 #define ACCDET_EINT_TEST_CMPMOUT_MASK_SFT (0x1 << 12)
1080 #define ACCDET_EINT_TEST_INVOUT_MASK 0x1
1081 #define ACCDET_EINT_TEST_INVOUT_MASK_SFT (0x1 << 13)
1085 #define ACCDET_CMPEN_SEL_MASK 0x1
1086 #define ACCDET_CMPEN_SEL_MASK_SFT (0x1 << 0)
1090 #define ACCDET_VTHEN_SEL_MASK 0x1
1091 #define ACCDET_VTHEN_SEL_MASK_SFT (0x1 << 1)
1095 #define ACCDET_MBIASEN_SEL_MASK 0x1
1096 #define ACCDET_MBIASEN_SEL_MASK_SFT (0x1 << 2)
1100 #define ACCDET_EINT_EN_SEL_MASK 0x1
1101 #define ACCDET_EINT_EN_SEL_MASK_SFT (0x1 << 3)
1105 #define ACCDET_EINT_INVEN_SEL_MASK 0x1
1106 #define ACCDET_EINT_INVEN_SEL_MASK_SFT (0x1 << 4)
1110 #define ACCDET_EINT_CMPEN_SEL_MASK 0x1
1111 #define ACCDET_EINT_CMPEN_SEL_MASK_SFT (0x1 << 5)
1115 #define ACCDET_EINT_CMPMEN_SEL_MASK 0x1
1116 #define ACCDET_EINT_CMPMEN_SEL_MASK_SFT (0x1 << 6)
1120 #define ACCDET_EINT_CTURBO_SEL_MASK 0x1
1121 #define ACCDET_EINT_CTURBO_SEL_MASK_SFT (0x1 << 7)
1125 #define ACCDET_B_SEL_MASK 0x1
1126 #define ACCDET_B_SEL_MASK_SFT (0x1 << 9)
1130 #define ACCDET_A_SEL_MASK 0x1
1131 #define ACCDET_A_SEL_MASK_SFT (0x1 << 10)
1135 #define ACCDET_EINT_CMPOUT_SEL_MASK 0x1
1136 #define ACCDET_EINT_CMPOUT_SEL_MASK_SFT (0x1 << 11)
1140 #define ACCDET_EINT_CMPMOUT_SEL_MASK 0x1
1141 #define ACCDET_EINT_CMPMOUT_SEL_MASK_SFT (0x1 << 12)
1145 #define ACCDET_EINT_INVOUT_SEL_MASK 0x1
1146 #define ACCDET_EINT_INVOUT_SEL_MASK_SFT (0x1 << 13)
1150 #define ACCDET_CMPEN_SW_MASK 0x1
1151 #define ACCDET_CMPEN_SW_MASK_SFT (0x1 << 0)
1155 #define ACCDET_VTHEN_SW_MASK 0x1
1156 #define ACCDET_VTHEN_SW_MASK_SFT (0x1 << 1)
1160 #define ACCDET_MBIASEN_SW_MASK 0x1
1161 #define ACCDET_MBIASEN_SW_MASK_SFT (0x1 << 2)
1165 #define ACCDET_EINT0_EN_SW_MASK 0x1
1166 #define ACCDET_EINT0_EN_SW_MASK_SFT (0x1 << 3)
1170 #define ACCDET_EINT0_INVEN_SW_MASK 0x1
1171 #define ACCDET_EINT0_INVEN_SW_MASK_SFT (0x1 << 4)
1175 #define ACCDET_EINT0_CMPEN_SW_MASK 0x1
1176 #define ACCDET_EINT0_CMPEN_SW_MASK_SFT (0x1 << 5)
1180 #define ACCDET_EINT0_CMPMEN_SW_MASK 0x1
1181 #define ACCDET_EINT0_CMPMEN_SW_MASK_SFT (0x1 << 6)
1185 #define ACCDET_EINT0_CTURBO_SW_MASK 0x1
1186 #define ACCDET_EINT0_CTURBO_SW_MASK_SFT (0x1 << 7)
1190 #define ACCDET_EINT1_EN_SW_MASK 0x1
1191 #define ACCDET_EINT1_EN_SW_MASK_SFT (0x1 << 8)
1195 #define ACCDET_EINT1_INVEN_SW_MASK 0x1
1196 #define ACCDET_EINT1_INVEN_SW_MASK_SFT (0x1 << 9)
1200 #define ACCDET_EINT1_CMPEN_SW_MASK 0x1
1201 #define ACCDET_EINT1_CMPEN_SW_MASK_SFT (0x1 << 10)
1205 #define ACCDET_EINT1_CMPMEN_SW_MASK 0x1
1206 #define ACCDET_EINT1_CMPMEN_SW_MASK_SFT (0x1 << 11)
1210 #define ACCDET_EINT1_CTURBO_SW_MASK 0x1
1211 #define ACCDET_EINT1_CTURBO_SW_MASK_SFT (0x1 << 12)
1215 #define ACCDET_B_SW_MASK 0x1
1216 #define ACCDET_B_SW_MASK_SFT (0x1 << 0)
1220 #define ACCDET_A_SW_MASK 0x1
1221 #define ACCDET_A_SW_MASK_SFT (0x1 << 1)
1225 #define ACCDET_EINT0_CMPOUT_SW_MASK 0x1
1226 #define ACCDET_EINT0_CMPOUT_SW_MASK_SFT (0x1 << 2)
1230 #define ACCDET_EINT0_CMPMOUT_SW_MASK 0x1
1231 #define ACCDET_EINT0_CMPMOUT_SW_MASK_SFT (0x1 << 3)
1235 #define ACCDET_EINT0_INVOUT_SW_MASK 0x1
1236 #define ACCDET_EINT0_INVOUT_SW_MASK_SFT (0x1 << 4)
1240 #define ACCDET_EINT1_CMPOUT_SW_MASK 0x1
1241 #define ACCDET_EINT1_CMPOUT_SW_MASK_SFT (0x1 << 5)
1245 #define ACCDET_EINT1_CMPMOUT_SW_MASK 0x1
1246 #define ACCDET_EINT1_CMPMOUT_SW_MASK_SFT (0x1 << 6)
1250 #define ACCDET_EINT1_INVOUT_SW_MASK 0x1
1251 #define ACCDET_EINT1_INVOUT_SW_MASK_SFT (0x1 << 7)
1255 #define AD_AUDACCDETCMPOB_MASK 0x1
1256 #define AD_AUDACCDETCMPOB_MASK_SFT (0x1 << 0)
1260 #define AD_AUDACCDETCMPOA_MASK 0x1
1261 #define AD_AUDACCDETCMPOA_MASK_SFT (0x1 << 1)
1285 #define DA_AUDACCDETMBIASCLK_MASK 0x1
1286 #define DA_AUDACCDETMBIASCLK_MASK_SFT (0x1 << 12)
1290 #define DA_AUDACCDETVTHCLK_MASK 0x1
1291 #define DA_AUDACCDETVTHCLK_MASK_SFT (0x1 << 13)
1295 #define DA_AUDACCDETCMPCLK_MASK 0x1
1296 #define DA_AUDACCDETCMPCLK_MASK_SFT (0x1 << 14)
1300 #define DA_AUDACCDETAUXADCSWCTRL_MASK 0x1
1301 #define DA_AUDACCDETAUXADCSWCTRL_MASK_SFT (0x1 << 15)
1305 #define AD_EINT0CMPMOUT_MASK 0x1
1306 #define AD_EINT0CMPMOUT_MASK_SFT (0x1 << 0)
1310 #define AD_EINT0CMPOUT_MASK 0x1
1311 #define AD_EINT0CMPOUT_MASK_SFT (0x1 << 1)
1335 #define DA_EINT0CMPEN_MASK 0x1
1336 #define DA_EINT0CMPEN_MASK_SFT (0x1 << 13)
1340 #define DA_EINT0CMPMEN_MASK 0x1
1341 #define DA_EINT0CMPMEN_MASK_SFT (0x1 << 14)
1345 #define DA_EINT0CTURBO_MASK 0x1
1346 #define DA_EINT0CTURBO_MASK_SFT (0x1 << 15)
1350 #define AD_EINT1CMPMOUT_MASK 0x1
1351 #define AD_EINT1CMPMOUT_MASK_SFT (0x1 << 0)
1355 #define AD_EINT1CMPOUT_MASK 0x1
1356 #define AD_EINT1CMPOUT_MASK_SFT (0x1 << 1)
1380 #define DA_EINT1CMPEN_MASK 0x1
1381 #define DA_EINT1CMPEN_MASK_SFT (0x1 << 13)
1385 #define DA_EINT1CMPMEN_MASK 0x1
1386 #define DA_EINT1CMPMEN_MASK_SFT (0x1 << 14)
1390 #define DA_EINT1CTURBO_MASK 0x1
1391 #define DA_EINT1CTURBO_MASK_SFT (0x1 << 15)
1395 #define AD_EINT0INVOUT_MASK 0x1
1396 #define AD_EINT0INVOUT_MASK_SFT (0x1 << 0)
1400 #define ACCDET_EINT0_INVERTER_CUR_IN_MASK 0x1
1401 #define ACCDET_EINT0_INVERTER_CUR_IN_MASK_SFT (0x1 << 1)
1405 #define ACCDET_EINT0_INVERTER_SAM_IN_MASK 0x1
1406 #define ACCDET_EINT0_INVERTER_SAM_IN_MASK_SFT (0x1 << 2)
1410 #define ACCDET_EINT0_INVERTER_MEM_IN_MASK 0x1
1411 #define ACCDET_EINT0_INVERTER_MEM_IN_MASK_SFT (0x1 << 3)
1420 #define DA_EINT0EN_MASK 0x1
1421 #define DA_EINT0EN_MASK_SFT (0x1 << 12)
1425 #define DA_EINT0INVEN_MASK 0x1
1426 #define DA_EINT0INVEN_MASK_SFT (0x1 << 13)
1430 #define DA_EINT0CEN_MASK 0x1
1431 #define DA_EINT0CEN_MASK_SFT (0x1 << 14)
1435 #define AD_EINT1INVOUT_MASK 0x1
1436 #define AD_EINT1INVOUT_MASK_SFT (0x1 << 0)
1440 #define ACCDET_EINT1_INVERTER_CUR_IN_MASK 0x1
1441 #define ACCDET_EINT1_INVERTER_CUR_IN_MASK_SFT (0x1 << 1)
1445 #define ACCDET_EINT1_INVERTER_SAM_IN_MASK 0x1
1446 #define ACCDET_EINT1_INVERTER_SAM_IN_MASK_SFT (0x1 << 2)
1450 #define ACCDET_EINT1_INVERTER_MEM_IN_MASK 0x1
1451 #define ACCDET_EINT1_INVERTER_MEM_IN_MASK_SFT (0x1 << 3)
1460 #define DA_EINT1EN_MASK 0x1
1461 #define DA_EINT1EN_MASK_SFT (0x1 << 12)
1465 #define DA_EINT1INVEN_MASK 0x1
1466 #define DA_EINT1INVEN_MASK_SFT (0x1 << 13)
1470 #define DA_EINT1CEN_MASK 0x1
1471 #define DA_EINT1CEN_MASK_SFT (0x1 << 14)
1475 #define ACCDET_EN_MASK 0x1
1476 #define ACCDET_EN_MASK_SFT (0x1 << 0)
1480 #define ACCDET_EINT0_EN_MASK 0x1
1481 #define ACCDET_EINT0_EN_MASK_SFT (0x1 << 1)
1485 #define ACCDET_EINT1_EN_MASK 0x1
1486 #define ACCDET_EINT1_EN_MASK_SFT (0x1 << 2)
1490 #define ACCDET_EINT0_M_EN_MASK 0x1
1491 #define ACCDET_EINT0_M_EN_MASK_SFT (0x1 << 3)
1495 #define ACCDET_EINT0_DETECT_MOISTURE_MASK 0x1
1496 #define ACCDET_EINT0_DETECT_MOISTURE_MASK_SFT (0x1 << 4)
1500 #define ACCDET_EINT0_PLUG_IN_MASK 0x1
1501 #define ACCDET_EINT0_PLUG_IN_MASK_SFT (0x1 << 5)
1505 #define ACCDET_EINT0_M_PLUG_IN_MASK 0x1
1506 #define ACCDET_EINT0_M_PLUG_IN_MASK_SFT (0x1 << 6)
1510 #define ACCDET_EINT1_M_EN_MASK 0x1
1511 #define ACCDET_EINT1_M_EN_MASK_SFT (0x1 << 7)
1515 #define ACCDET_EINT1_DETECT_MOISTURE_MASK 0x1
1516 #define ACCDET_EINT1_DETECT_MOISTURE_MASK_SFT (0x1 << 8)
1520 #define ACCDET_EINT1_PLUG_IN_MASK 0x1
1521 #define ACCDET_EINT1_PLUG_IN_MASK_SFT (0x1 << 9)
1525 #define ACCDET_EINT1_M_PLUG_IN_MASK 0x1
1526 #define ACCDET_EINT1_M_PLUG_IN_MASK_SFT (0x1 << 10)
1555 #define AD_AUDACCDETCMPOB_MON_MASK 0x1
1556 #define AD_AUDACCDETCMPOB_MON_MASK_SFT (0x1 << 0)
1560 #define AD_AUDACCDETCMPOA_MON_MASK 0x1
1561 #define AD_AUDACCDETCMPOA_MON_MASK_SFT (0x1 << 1)
1565 #define AD_EINT0CMPMOUT_MON_MASK 0x1
1566 #define AD_EINT0CMPMOUT_MON_MASK_SFT (0x1 << 2)
1570 #define AD_EINT0CMPOUT_MON_MASK 0x1
1571 #define AD_EINT0CMPOUT_MON_MASK_SFT (0x1 << 3)
1575 #define AD_EINT0INVOUT_MON_MASK 0x1
1576 #define AD_EINT0INVOUT_MON_MASK_SFT (0x1 << 4)
1580 #define AD_EINT1CMPMOUT_MON_MASK 0x1
1581 #define AD_EINT1CMPMOUT_MON_MASK_SFT (0x1 << 5)
1585 #define AD_EINT1CMPOUT_MON_MASK 0x1
1586 #define AD_EINT1CMPOUT_MON_MASK_SFT (0x1 << 6)
1590 #define AD_EINT1INVOUT_MON_MASK 0x1
1591 #define AD_EINT1INVOUT_MON_MASK_SFT (0x1 << 7)
1595 #define DA_AUDACCDETCMPCLK_MON_MASK 0x1
1596 #define DA_AUDACCDETCMPCLK_MON_MASK_SFT (0x1 << 0)
1600 #define DA_AUDACCDETVTHCLK_MON_MASK 0x1
1601 #define DA_AUDACCDETVTHCLK_MON_MASK_SFT (0x1 << 1)
1605 #define DA_AUDACCDETMBIASCLK_MON_MASK 0x1
1606 #define DA_AUDACCDETMBIASCLK_MON_MASK_SFT (0x1 << 2)
1610 #define DA_AUDACCDETAUXADCSWCTRL_MON_MASK 0x1
1611 #define DA_AUDACCDETAUXADCSWCTRL_MON_MASK_SFT (0x1 << 3)
1615 #define DA_EINT0CTURBO_MON_MASK 0x1
1616 #define DA_EINT0CTURBO_MON_MASK_SFT (0x1 << 0)
1620 #define DA_EINT0CMPMEN_MON_MASK 0x1
1621 #define DA_EINT0CMPMEN_MON_MASK_SFT (0x1 << 1)
1625 #define DA_EINT0CMPEN_MON_MASK 0x1
1626 #define DA_EINT0CMPEN_MON_MASK_SFT (0x1 << 2)
1630 #define DA_EINT0INVEN_MON_MASK 0x1
1631 #define DA_EINT0INVEN_MON_MASK_SFT (0x1 << 3)
1635 #define DA_EINT0CEN_MON_MASK 0x1
1636 #define DA_EINT0CEN_MON_MASK_SFT (0x1 << 4)
1640 #define DA_EINT0EN_MON_MASK 0x1
1641 #define DA_EINT0EN_MON_MASK_SFT (0x1 << 5)
1645 #define DA_EINT1CTURBO_MON_MASK 0x1
1646 #define DA_EINT1CTURBO_MON_MASK_SFT (0x1 << 8)
1650 #define DA_EINT1CMPMEN_MON_MASK 0x1
1651 #define DA_EINT1CMPMEN_MON_MASK_SFT (0x1 << 9)
1655 #define DA_EINT1CMPEN_MON_MASK 0x1
1656 #define DA_EINT1CMPEN_MON_MASK_SFT (0x1 << 10)
1660 #define DA_EINT1INVEN_MON_MASK 0x1
1661 #define DA_EINT1INVEN_MON_MASK_SFT (0x1 << 11)
1665 #define DA_EINT1CEN_MON_MASK 0x1
1666 #define DA_EINT1CEN_MON_MASK_SFT (0x1 << 12)
1670 #define DA_EINT1EN_MON_MASK 0x1
1671 #define DA_EINT1EN_MON_MASK_SFT (0x1 << 13)
1685 #define ACCDET_MON_FLAG_EN_MASK 0x1
1686 #define ACCDET_MON_FLAG_EN_MASK_SFT (0x1 << 0)
1696 #define RG_AUDPWDBMICBIAS0_MASK 0x1
1697 #define RG_AUDPWDBMICBIAS0_MASK_SFT (0x1 << 0)
1701 #define RG_AUDPREAMPLON_MASK 0x1
1702 #define RG_AUDPREAMPLON_MASK_SFT (0x1 << 0)
1706 #define RG_CLKSQ_EN_MASK 0x1
1707 #define RG_CLKSQ_EN_MASK_SFT (0x1 << 0)
1711 #define RG_RTC32K_CK_PDN_MASK 0x1
1712 #define RG_RTC32K_CK_PDN_MASK_SFT (0x1 << 15)
1721 #define AUXADC_RQST_CH5_MASK 0x1
1722 #define AUXADC_RQST_CH5_MASK_SFT (0x1 << 5)
1726 #define RG_LDO_VUSB_HW0_OP_EN_MASK 0x1
1727 #define RG_LDO_VUSB_HW0_OP_EN_MASK_SFT (0x1 << 0)
1736 #define RG_NCP_PDDIS_EN_MASK 0x1
1737 #define RG_NCP_PDDIS_EN_MASK_SFT (0x1 << 0)
1741 #define RG_SCK32K_CK_PDN_MASK 0x1
1742 #define RG_SCK32K_CK_PDN_MASK_SFT (0x1 << 0)
1790 #define RG_VOW13M_CK_PDN_MASK 0x1
1791 #define RG_VOW13M_CK_PDN_MASK_SFT (0x1 << 13)
1793 #define RG_VOW32K_CK_PDN_MASK 0x1
1794 #define RG_VOW32K_CK_PDN_MASK_SFT (0x1 << 12)
1796 #define RG_AUD_INTRP_CK_PDN_MASK 0x1
1797 #define RG_AUD_INTRP_CK_PDN_MASK_SFT (0x1 << 8)
1799 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK 0x1
1800 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK_SFT (0x1 << 7)
1802 #define RG_AUDNCP_CK_PDN_MASK 0x1
1803 #define RG_AUDNCP_CK_PDN_MASK_SFT (0x1 << 6)
1805 #define RG_ZCD13M_CK_PDN_MASK 0x1
1806 #define RG_ZCD13M_CK_PDN_MASK_SFT (0x1 << 5)
1808 #define RG_AUDIF_CK_PDN_MASK 0x1
1809 #define RG_AUDIF_CK_PDN_MASK_SFT (0x1 << 2)
1811 #define RG_AUD_CK_PDN_MASK 0x1
1812 #define RG_AUD_CK_PDN_MASK_SFT (0x1 << 1)
1814 #define RG_ACCDET_CK_PDN_MASK 0x1
1815 #define RG_ACCDET_CK_PDN_MASK_SFT (0x1 << 0)
1829 #define RG_AUDIF_CK_CKSEL_MASK 0x1
1830 #define RG_AUDIF_CK_CKSEL_MASK_SFT (0x1 << 3)
1832 #define RG_AUD_CK_CKSEL_MASK 0x1
1833 #define RG_AUD_CK_CKSEL_MASK_SFT (0x1 << 2)
1847 #define RG_VOW13M_CK_TSTSEL_MASK 0x1
1848 #define RG_VOW13M_CK_TSTSEL_MASK_SFT (0x1 << 9)
1850 #define RG_VOW13M_CK_TST_DIS_MASK 0x1
1851 #define RG_VOW13M_CK_TST_DIS_MASK_SFT (0x1 << 8)
1853 #define RG_AUD26M_CK_TSTSEL_MASK 0x1
1854 #define RG_AUD26M_CK_TSTSEL_MASK_SFT (0x1 << 4)
1856 #define RG_AUDIF_CK_TSTSEL_MASK 0x1
1857 #define RG_AUDIF_CK_TSTSEL_MASK_SFT (0x1 << 3)
1859 #define RG_AUD_CK_TSTSEL_MASK 0x1
1860 #define RG_AUD_CK_TSTSEL_MASK_SFT (0x1 << 2)
1862 #define RG_AUD26M_CK_TST_DIS_MASK 0x1
1863 #define RG_AUD26M_CK_TST_DIS_MASK_SFT (0x1 << 0)
1867 #define RG_AUD_INTRP_CK_PDN_HWEN_MASK 0x1
1868 #define RG_AUD_INTRP_CK_PDN_HWEN_MASK_SFT (0x1 << 0)
1882 #define RG_AUDNCP_RST_MASK 0x1
1883 #define RG_AUDNCP_RST_MASK_SFT (0x1 << 3)
1885 #define RG_ZCD_RST_MASK 0x1
1886 #define RG_ZCD_RST_MASK_SFT (0x1 << 2)
1888 #define RG_ACCDET_RST_MASK 0x1
1889 #define RG_ACCDET_RST_MASK_SFT (0x1 << 1)
1891 #define RG_AUDIO_RST_MASK 0x1
1892 #define RG_AUDIO_RST_MASK_SFT (0x1 << 0)
1906 #define BANK_AUDZCD_SWRST_MASK 0x1
1907 #define BANK_AUDZCD_SWRST_MASK_SFT (0x1 << 2)
1909 #define BANK_AUDIO_SWRST_MASK 0x1
1910 #define BANK_AUDIO_SWRST_MASK_SFT (0x1 << 1)
1912 #define BANK_ACCDET_SWRST_MASK 0x1
1913 #define BANK_ACCDET_SWRST_MASK_SFT (0x1 << 0)
1917 #define AFE_UL_LR_SWAP_MASK 0x1
1918 #define AFE_UL_LR_SWAP_MASK_SFT (0x1 << 15)
1920 #define AFE_DL_LR_SWAP_MASK 0x1
1921 #define AFE_DL_LR_SWAP_MASK_SFT (0x1 << 14)
1923 #define AFE_ON_MASK 0x1
1924 #define AFE_ON_MASK_SFT (0x1 << 0)
1928 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK 0x1
1929 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0)
1939 #define C_TWO_DIGITAL_MIC_CTL_MASK 0x1
1940 #define C_TWO_DIGITAL_MIC_CTL_MASK_SFT (0x1 << 7)
1947 #define DIGMIC_4P33M_SEL_CTL_MASK 0x1
1948 #define DIGMIC_4P33M_SEL_CTL_MASK_SFT (0x1 << 6)
1950 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1
1951 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)
1953 #define UL_LOOP_BACK_MODE_CTL_MASK 0x1
1954 #define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)
1956 #define UL_SDM_3_LEVEL_CTL_MASK 0x1
1957 #define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)
1959 #define UL_SRC_ON_TMP_CTL_MASK 0x1
1960 #define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)
1970 #define ADDA6_C_TWO_DIGITAL_MIC_CTL_MASK 0x1
1971 #define ADDA6_C_TWO_DIGITAL_MIC_CTL_MASK_SFT (0x1 << 7)
1978 #define ADDA6_DIGMIC_4P33M_SEL_CTL_MASK 0x1
1979 #define ADDA6_DIGMIC_4P33M_SEL_CTL_MASK_SFT (0x1 << 6)
1981 #define ADDA6_DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1
1982 #define ADDA6_DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)
1984 #define ADDA6_UL_LOOP_BACK_MODE_CTL_MASK 0x1
1985 #define ADDA6_UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)
1987 #define ADDA6_UL_SDM_3_LEVEL_CTL_MASK 0x1
1988 #define ADDA6_UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)
1990 #define ADDA6_UL_SRC_ON_TMP_CTL_MASK 0x1
1991 #define ADDA6_UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)
1995 #define ADDA6_MTKAIF_SINE_ON_MASK 0x1
1996 #define ADDA6_MTKAIF_SINE_ON_MASK_SFT (0x1 << 4)
1998 #define ADDA6_UL_SINE_ON_MASK 0x1
1999 #define ADDA6_UL_SINE_ON_MASK_SFT (0x1 << 3)
2001 #define MTKAIF_SINE_ON_MASK 0x1
2002 #define MTKAIF_SINE_ON_MASK_SFT (0x1 << 2)
2004 #define UL_SINE_ON_MASK 0x1
2005 #define UL_SINE_ON_MASK_SFT (0x1 << 1)
2007 #define DL_SINE_ON_MASK 0x1
2008 #define DL_SINE_ON_MASK_SFT (0x1 << 0)
2012 #define PDN_AFE_CTL_MASK 0x1
2013 #define PDN_AFE_CTL_MASK_SFT (0x1 << 7)
2015 #define PDN_DAC_CTL_MASK 0x1
2016 #define PDN_DAC_CTL_MASK_SFT (0x1 << 6)
2018 #define PDN_ADC_CTL_MASK 0x1
2019 #define PDN_ADC_CTL_MASK_SFT (0x1 << 5)
2021 #define PDN_ADDA6_ADC_CTL_MASK 0x1
2022 #define PDN_ADDA6_ADC_CTL_MASK_SFT (0x1 << 4)
2024 #define PDN_I2S_DL_CTL_MASK 0x1
2025 #define PDN_I2S_DL_CTL_MASK_SFT (0x1 << 3)
2027 #define PWR_CLK_DIS_CTL_MASK 0x1
2028 #define PWR_CLK_DIS_CTL_MASK_SFT (0x1 << 2)
2030 #define PDN_AFE_TESTMODEL_CTL_MASK 0x1
2031 #define PDN_AFE_TESTMODEL_CTL_MASK_SFT (0x1 << 1)
2033 #define PDN_RESERVED_MASK 0x1
2034 #define PDN_RESERVED_MASK_SFT (0x1 << 0)
2049 #define CCI_AUD_ANACK_SEL_MASK 0x1
2050 #define CCI_AUD_ANACK_SEL_MASK_SFT (0x1 << 15)
2055 #define CCI_SCRAMBLER_CG_EN_MASK 0x1
2056 #define CCI_SCRAMBLER_CG_EN_MASK_SFT (0x1 << 11)
2058 #define CCI_LCH_INV_MASK 0x1
2059 #define CCI_LCH_INV_MASK_SFT (0x1 << 10)
2061 #define CCI_RAND_EN_MASK 0x1
2062 #define CCI_RAND_EN_MASK_SFT (0x1 << 9)
2064 #define CCI_SPLT_SCRMB_CLK_ON_MASK 0x1
2065 #define CCI_SPLT_SCRMB_CLK_ON_MASK_SFT (0x1 << 8)
2067 #define CCI_SPLT_SCRMB_ON_MASK 0x1
2068 #define CCI_SPLT_SCRMB_ON_MASK_SFT (0x1 << 7)
2070 #define CCI_AUD_IDAC_TEST_EN_MASK 0x1
2071 #define CCI_AUD_IDAC_TEST_EN_MASK_SFT (0x1 << 6)
2073 #define CCI_ZERO_PAD_DISABLE_MASK 0x1
2074 #define CCI_ZERO_PAD_DISABLE_MASK_SFT (0x1 << 5)
2076 #define CCI_AUD_SPLIT_TEST_EN_MASK 0x1
2077 #define CCI_AUD_SPLIT_TEST_EN_MASK_SFT (0x1 << 4)
2079 #define CCI_AUD_SDM_MUTEL_MASK 0x1
2080 #define CCI_AUD_SDM_MUTEL_MASK_SFT (0x1 << 3)
2082 #define CCI_AUD_SDM_MUTER_MASK 0x1
2083 #define CCI_AUD_SDM_MUTER_MASK_SFT (0x1 << 2)
2085 #define CCI_AUD_SDM_7BIT_SEL_MASK 0x1
2086 #define CCI_AUD_SDM_7BIT_SEL_MASK_SFT (0x1 << 1)
2088 #define CCI_SCRAMBLER_EN_MASK 0x1
2089 #define CCI_SCRAMBLER_EN_MASK_SFT (0x1 << 0)
2101 #define CCI_AUD_DAC_ANA_MUTE_MASK 0x1
2102 #define CCI_AUD_DAC_ANA_MUTE_MASK_SFT (0x1 << 7)
2104 #define CCI_AUD_DAC_ANA_RSTB_SEL_MASK 0x1
2105 #define CCI_AUD_DAC_ANA_RSTB_SEL_MASK_SFT (0x1 << 6)
2107 #define CCI_AUDIO_FIFO_CLKIN_INV_MASK 0x1
2108 #define CCI_AUDIO_FIFO_CLKIN_INV_MASK_SFT (0x1 << 4)
2110 #define CCI_AUDIO_FIFO_ENABLE_MASK 0x1
2111 #define CCI_AUDIO_FIFO_ENABLE_MASK_SFT (0x1 << 3)
2113 #define CCI_ACD_MODE_MASK 0x1
2114 #define CCI_ACD_MODE_MASK_SFT (0x1 << 2)
2116 #define CCI_AFIFO_CLK_PWDB_MASK 0x1
2117 #define CCI_AFIFO_CLK_PWDB_MASK_SFT (0x1 << 1)
2119 #define CCI_ACD_FUNC_RSTB_MASK 0x1
2120 #define CCI_ACD_FUNC_RSTB_MASK_SFT (0x1 << 0)
2124 #define SDM_ANA13M_TESTCK_SEL_MASK 0x1
2125 #define SDM_ANA13M_TESTCK_SEL_MASK_SFT (0x1 << 15)
2136 #define DIGMIC_TESTCK_SEL_MASK 0x1
2137 #define DIGMIC_TESTCK_SEL_MASK_SFT (0x1 << 0)
2141 #define UL_FIFO_WCLK_INV_MASK 0x1
2142 #define UL_FIFO_WCLK_INV_MASK_SFT (0x1 << 8)
2144 #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK 0x1
2145 #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 6)
2147 #define UL_FIFO_WDATA_TESTEN_MASK 0x1
2148 #define UL_FIFO_WDATA_TESTEN_MASK_SFT (0x1 << 5)
2150 #define UL_FIFO_WDATA_TESTSRC_SEL_MASK 0x1
2151 #define UL_FIFO_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 4)
2153 #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK 0x1
2154 #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK_SFT (0x1 << 3)
2181 #define R_AUD_DAC_MONO_SEL_MASK 0x1
2182 #define R_AUD_DAC_MONO_SEL_MASK_SFT (0x1 << 3)
2184 #define R_AUD_DAC_3TH_SEL_MASK 0x1
2185 #define R_AUD_DAC_3TH_SEL_MASK_SFT (0x1 << 1)
2187 #define R_AUD_DAC_SW_RSTB_MASK 0x1
2188 #define R_AUD_DAC_SW_RSTB_MASK_SFT (0x1 << 0)
2195 #define UL2_DIGMIC_TESTCK_SEL_MASK 0x1
2196 #define UL2_DIGMIC_TESTCK_SEL_MASK_SFT (0x1 << 9)
2198 #define UL2_FIFO_WCLK_INV_MASK 0x1
2199 #define UL2_FIFO_WCLK_INV_MASK_SFT (0x1 << 8)
2201 #define UL2_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK 0x1
2202 #define UL2_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 6)
2204 #define UL2_FIFO_WDATA_TESTEN_MASK 0x1
2205 #define UL2_FIFO_WDATA_TESTEN_MASK_SFT (0x1 << 5)
2207 #define UL2_FIFO_WDATA_TESTSRC_SEL_MASK 0x1
2208 #define UL2_FIFO_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 4)
2210 #define UL2_FIFO_WCLK_6P5M_TESTCK_SEL_MASK 0x1
2211 #define UL2_FIFO_WCLK_6P5M_TESTCK_SEL_MASK_SFT (0x1 << 3)
2218 #define SPLITTER2_DITHER_EN_MASK 0x1
2219 #define SPLITTER2_DITHER_EN_MASK_SFT (0x1 << 9)
2221 #define SPLITTER1_DITHER_EN_MASK 0x1
2222 #define SPLITTER1_DITHER_EN_MASK_SFT (0x1 << 8)
2232 #define CCI_AUD_ANACK_SEL_2ND_MASK 0x1
2233 #define CCI_AUD_ANACK_SEL_2ND_MASK_SFT (0x1 << 15)
2238 #define CCI_SCRAMBLER_CG_EN_2ND_MASK 0x1
2239 #define CCI_SCRAMBLER_CG_EN_2ND_MASK_SFT (0x1 << 11)
2241 #define CCI_LCH_INV_2ND_MASK 0x1
2242 #define CCI_LCH_INV_2ND_MASK_SFT (0x1 << 10)
2244 #define CCI_RAND_EN_2ND_MASK 0x1
2245 #define CCI_RAND_EN_2ND_MASK_SFT (0x1 << 9)
2247 #define CCI_SPLT_SCRMB_CLK_ON_2ND_MASK 0x1
2248 #define CCI_SPLT_SCRMB_CLK_ON_2ND_MASK_SFT (0x1 << 8)
2250 #define CCI_SPLT_SCRMB_ON_2ND_MASK 0x1
2251 #define CCI_SPLT_SCRMB_ON_2ND_MASK_SFT (0x1 << 7)
2253 #define CCI_AUD_IDAC_TEST_EN_2ND_MASK 0x1
2254 #define CCI_AUD_IDAC_TEST_EN_2ND_MASK_SFT (0x1 << 6)
2256 #define CCI_ZERO_PAD_DISABLE_2ND_MASK 0x1
2257 #define CCI_ZERO_PAD_DISABLE_2ND_MASK_SFT (0x1 << 5)
2259 #define CCI_AUD_SPLIT_TEST_EN_2ND_MASK 0x1
2260 #define CCI_AUD_SPLIT_TEST_EN_2ND_MASK_SFT (0x1 << 4)
2262 #define CCI_AUD_SDM_MUTEL_2ND_MASK 0x1
2263 #define CCI_AUD_SDM_MUTEL_2ND_MASK_SFT (0x1 << 3)
2265 #define CCI_AUD_SDM_MUTER_2ND_MASK 0x1
2266 #define CCI_AUD_SDM_MUTER_2ND_MASK_SFT (0x1 << 2)
2268 #define CCI_AUD_SDM_7BIT_SEL_2ND_MASK 0x1
2269 #define CCI_AUD_SDM_7BIT_SEL_2ND_MASK_SFT (0x1 << 1)
2271 #define CCI_SCRAMBLER_EN_2ND_MASK 0x1
2272 #define CCI_SCRAMBLER_EN_2ND_MASK_SFT (0x1 << 0)
2284 #define CCI_AUD_DAC_ANA_MUTE_2ND_MASK 0x1
2285 #define CCI_AUD_DAC_ANA_MUTE_2ND_MASK_SFT (0x1 << 7)
2287 #define CCI_AUD_DAC_ANA_RSTB_SEL_2ND_MASK 0x1
2288 #define CCI_AUD_DAC_ANA_RSTB_SEL_2ND_MASK_SFT (0x1 << 6)
2290 #define CCI_AUDIO_FIFO_CLKIN_INV_2ND_MASK 0x1
2291 #define CCI_AUDIO_FIFO_CLKIN_INV_2ND_MASK_SFT (0x1 << 4)
2293 #define CCI_AUDIO_FIFO_ENABLE_2ND_MASK 0x1
2294 #define CCI_AUDIO_FIFO_ENABLE_2ND_MASK_SFT (0x1 << 3)
2296 #define CCI_ACD_MODE_2ND_MASK 0x1
2297 #define CCI_ACD_MODE_2ND_MASK_SFT (0x1 << 2)
2299 #define CCI_AFIFO_CLK_PWDB_2ND_MASK 0x1
2300 #define CCI_AFIFO_CLK_PWDB_2ND_MASK_SFT (0x1 << 1)
2302 #define CCI_ACD_FUNC_RSTB_2ND_MASK 0x1
2303 #define CCI_ACD_FUNC_RSTB_2ND_MASK_SFT (0x1 << 0)
2307 #define SPLITTER2_DITHER_EN_2ND_MASK 0x1
2308 #define SPLITTER2_DITHER_EN_2ND_MASK_SFT (0x1 << 9)
2310 #define SPLITTER1_DITHER_EN_2ND_MASK 0x1
2311 #define SPLITTER1_DITHER_EN_2ND_MASK_SFT (0x1 << 8)
2337 #define ASYNC_TEST_OUT_BCK_MASK 0x1
2338 #define ASYNC_TEST_OUT_BCK_MASK_SFT (0x1 << 15)
2351 #define RG_MTKAIF_RXIF_FIFO_INTEN_MASK 0x1
2352 #define RG_MTKAIF_RXIF_FIFO_INTEN_MASK_SFT (0x1 << 0)
2356 #define MTKAIF_RXIF_WR_FULL_STATUS_MASK 0x1
2357 #define MTKAIF_RXIF_WR_FULL_STATUS_MASK_SFT (0x1 << 1)
2359 #define MTKAIF_RXIF_RD_EMPTY_STATUS_MASK 0x1
2360 #define MTKAIF_RXIF_RD_EMPTY_STATUS_MASK_SFT (0x1 << 0)
2364 #define MTKAIFTX_V3_SYNC_OUT_MASK 0x1
2365 #define MTKAIFTX_V3_SYNC_OUT_MASK_SFT (0x1 << 15)
2367 #define MTKAIFTX_V3_SDATA_OUT3_MASK 0x1
2368 #define MTKAIFTX_V3_SDATA_OUT3_MASK_SFT (0x1 << 14)
2370 #define MTKAIFTX_V3_SDATA_OUT2_MASK 0x1
2371 #define MTKAIFTX_V3_SDATA_OUT2_MASK_SFT (0x1 << 13)
2373 #define MTKAIFTX_V3_SDATA_OUT1_MASK 0x1
2374 #define MTKAIFTX_V3_SDATA_OUT1_MASK_SFT (0x1 << 12)
2381 #define MTKAIFRX_V3_SYNC_IN_MASK 0x1
2382 #define MTKAIFRX_V3_SYNC_IN_MASK_SFT (0x1 << 15)
2384 #define MTKAIFRX_V3_SDATA_IN3_MASK 0x1
2385 #define MTKAIFRX_V3_SDATA_IN3_MASK_SFT (0x1 << 14)
2387 #define MTKAIFRX_V3_SDATA_IN2_MASK 0x1
2388 #define MTKAIFRX_V3_SDATA_IN2_MASK_SFT (0x1 << 13)
2390 #define MTKAIFRX_V3_SDATA_IN1_MASK 0x1
2391 #define MTKAIFRX_V3_SDATA_IN1_MASK_SFT (0x1 << 12)
2393 #define MTKAIF_RXIF_SEARCH_FAIL_FLAG_MASK 0x1
2394 #define MTKAIF_RXIF_SEARCH_FAIL_FLAG_MASK_SFT (0x1 << 11)
2396 #define MTKAIF_RXIF_INVALID_FLAG_MASK 0x1
2397 #define MTKAIF_RXIF_INVALID_FLAG_MASK_SFT (0x1 << 8)
2433 #define RG_MTKAIF_RXIF_CLKINV_MASK 0x1
2434 #define RG_MTKAIF_RXIF_CLKINV_MASK_SFT (0x1 << 15)
2436 #define RG_ADDA6_MTKAIF_TXIF_PROTOCOL2_MASK 0x1
2437 #define RG_ADDA6_MTKAIF_TXIF_PROTOCOL2_MASK_SFT (0x1 << 9)
2439 #define RG_MTKAIF_RXIF_PROTOCOL2_MASK 0x1
2440 #define RG_MTKAIF_RXIF_PROTOCOL2_MASK_SFT (0x1 << 8)
2445 #define RG_MTKAIF_BYPASS_SRC_TEST_MASK 0x1
2446 #define RG_MTKAIF_BYPASS_SRC_TEST_MASK_SFT (0x1 << 5)
2448 #define RG_MTKAIF_TXIF_PROTOCOL2_MASK 0x1
2449 #define RG_MTKAIF_TXIF_PROTOCOL2_MASK_SFT (0x1 << 4)
2451 #define RG_ADDA6_MTKAIF_PMIC_TXIF_8TO5_MASK 0x1
2452 #define RG_ADDA6_MTKAIF_PMIC_TXIF_8TO5_MASK_SFT (0x1 << 3)
2454 #define RG_MTKAIF_PMIC_TXIF_8TO5_MASK 0x1
2455 #define RG_MTKAIF_PMIC_TXIF_8TO5_MASK_SFT (0x1 << 2)
2457 #define RG_MTKAIF_LOOPBACK_TEST2_MASK 0x1
2458 #define RG_MTKAIF_LOOPBACK_TEST2_MASK_SFT (0x1 << 1)
2460 #define RG_MTKAIF_LOOPBACK_TEST1_MASK 0x1
2461 #define RG_MTKAIF_LOOPBACK_TEST1_MASK_SFT (0x1 << 0)
2474 #define RG_MTKAIF_RXIF_DETECT_ON_MASK 0x1
2475 #define RG_MTKAIF_RXIF_DETECT_ON_MASK_SFT (0x1 << 3)
2477 #define RG_MTKAIF_RXIF_DATA_MODE_MASK 0x1
2478 #define RG_MTKAIF_RXIF_DATA_MODE_MASK_SFT (0x1 << 0)
2496 #define RG_MTKAIF_RXIF_P2_INPUT_SEL_MASK 0x1
2497 #define RG_MTKAIF_RXIF_P2_INPUT_SEL_MASK_SFT (0x1 << 15)
2499 #define RG_MTKAIF_RXIF_SYNC_WORD2_DISABLE_MASK 0x1
2500 #define RG_MTKAIF_RXIF_SYNC_WORD2_DISABLE_MASK_SFT (0x1 << 14)
2502 #define RG_MTKAIF_RXIF_SYNC_WORD1_DISABLE_MASK 0x1
2503 #define RG_MTKAIF_RXIF_SYNC_WORD1_DISABLE_MASK_SFT (0x1 << 13)
2505 #define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK 0x1
2506 #define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK_SFT (0x1 << 12)
2513 #define RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_MASK 0x1
2514 #define RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_MASK_SFT (0x1 << 7)
2519 #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK 0x1
2520 #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT (0x1 << 3)
2549 #define SGEN_DAC_EN_CTL_MASK 0x1
2550 #define SGEN_DAC_EN_CTL_MASK_SFT (0x1 << 7)
2552 #define SGEN_MUTE_SW_CTL_MASK 0x1
2553 #define SGEN_MUTE_SW_CTL_MASK_SFT (0x1 << 6)
2555 #define R_AUD_SDM_MUTE_L_MASK 0x1
2556 #define R_AUD_SDM_MUTE_L_MASK_SFT (0x1 << 5)
2558 #define R_AUD_SDM_MUTE_R_MASK 0x1
2559 #define R_AUD_SDM_MUTE_R_MASK_SFT (0x1 << 4)
2561 #define R_AUD_SDM_MUTE_L_2ND_MASK 0x1
2562 #define R_AUD_SDM_MUTE_L_2ND_MASK_SFT (0x1 << 3)
2564 #define R_AUD_SDM_MUTE_R_2ND_MASK 0x1
2565 #define R_AUD_SDM_MUTE_R_2ND_MASK_SFT (0x1 << 2)
2569 #define C_SGEN_RCH_INV_5BIT_MASK 0x1
2570 #define C_SGEN_RCH_INV_5BIT_MASK_SFT (0x1 << 15)
2572 #define C_SGEN_RCH_INV_8BIT_MASK 0x1
2573 #define C_SGEN_RCH_INV_8BIT_MASK_SFT (0x1 << 14)
2580 #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK 0x1
2581 #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK_SFT (0x1 << 5)
2583 #define RG_UL_ASYNC_FIFO_SOFT_RST_MASK 0x1
2584 #define RG_UL_ASYNC_FIFO_SOFT_RST_MASK_SFT (0x1 << 4)
2586 #define RG_AMIC_UL_ADC_CLK_SEL_MASK 0x1
2587 #define RG_AMIC_UL_ADC_CLK_SEL_MASK_SFT (0x1 << 1)
2591 #define RG_UL2_ASYNC_FIFO_SOFT_RST_EN_MASK 0x1
2592 #define RG_UL2_ASYNC_FIFO_SOFT_RST_EN_MASK_SFT (0x1 << 5)
2594 #define RG_UL2_ASYNC_FIFO_SOFT_RST_MASK 0x1
2595 #define RG_UL2_ASYNC_FIFO_SOFT_RST_MASK_SFT (0x1 << 4)
2602 #define DCCLK_INV_MASK 0x1
2603 #define DCCLK_INV_MASK_SFT (0x1 << 4)
2608 #define DCCLK_PDN_MASK 0x1
2609 #define DCCLK_PDN_MASK_SFT (0x1 << 1)
2611 #define DCCLK_GEN_ON_MASK 0x1
2612 #define DCCLK_GEN_ON_MASK_SFT (0x1 << 0)
2619 #define RESYNC_SRC_CK_INV_MASK 0x1
2620 #define RESYNC_SRC_CK_INV_MASK_SFT (0x1 << 9)
2622 #define DCCLK_RESYNC_BYPASS_MASK 0x1
2623 #define DCCLK_RESYNC_BYPASS_MASK_SFT (0x1 << 8)
2630 #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK 0x1
2631 #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT (0x1 << 15)
2636 #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK 0x1
2637 #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT (0x1 << 7)
2644 #define RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK 0x1
2645 #define RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK_SFT (0x1 << 7)
2655 #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK 0x1
2656 #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK_SFT (0x1 << 11)
2658 #define RG_AUD_PAD_TOP_TX_FIFO_ON_MASK 0x1
2659 #define RG_AUD_PAD_TOP_TX_FIFO_ON_MASK_SFT (0x1 << 8)
2678 #define NLE_RCH_HPGAIN_SEL_MASK 0x1
2679 #define NLE_RCH_HPGAIN_SEL_MASK_SFT (0x1 << 10)
2681 #define NLE_RCH_CH_SEL_MASK 0x1
2682 #define NLE_RCH_CH_SEL_MASK_SFT (0x1 << 9)
2684 #define NLE_RCH_ON_MASK 0x1
2685 #define NLE_RCH_ON_MASK_SFT (0x1 << 8)
2687 #define NLE_LCH_HPGAIN_SEL_MASK 0x1
2688 #define NLE_LCH_HPGAIN_SEL_MASK_SFT (0x1 << 2)
2690 #define NLE_LCH_CH_SEL_MASK 0x1
2691 #define NLE_LCH_CH_SEL_MASK_SFT (0x1 << 1)
2693 #define NLE_LCH_ON_MASK 0x1
2694 #define NLE_LCH_ON_MASK_SFT (0x1 << 0)
2731 #define RG_CHOP_DIV_EN_MASK 0x1
2732 #define RG_CHOP_DIV_EN_MASK_SFT (0x1 << 0)
2736 #define RG_ADDA6_EN_SEL_MASK 0x1
2737 #define RG_ADDA6_EN_SEL_MASK_SFT (0x1 << 12)
2745 #define RG_ADDA_EN_SEL_MASK 0x1
2746 #define RG_ADDA_EN_SEL_MASK_SFT (0x1 << 4)
2764 #define RG_NCP_ADITH_MASK 0x1
2765 #define RG_NCP_ADITH_MASK_SFT (0x1 << 8)
2767 #define RG_NCP_DITHER_EN_MASK 0x1
2768 #define RG_NCP_DITHER_EN_MASK_SFT (0x1 << 7)
2776 #define RG_NCP_ON_MASK 0x1
2777 #define RG_NCP_ON_MASK_SFT (0x1 << 0)
2781 #define RG_XY_VAL_CFG_EN_MASK 0x1
2782 #define RG_XY_VAL_CFG_EN_MASK_SFT (0x1 << 15)
2792 #define RG_NCP_NONCLK_SET_MASK 0x1
2793 #define RG_NCP_NONCLK_SET_MASK_SFT (0x1 << 1)
2795 #define RG_NCP_PDDIS_EN_MASK 0x1
2796 #define RG_NCP_PDDIS_EN_MASK_SFT (0x1 << 0)
2800 #define RG_AUDPREAMPLON_MASK 0x1
2801 #define RG_AUDPREAMPLON_MASK_SFT (0x1 << 0)
2803 #define RG_AUDPREAMPLDCCEN_MASK 0x1
2804 #define RG_AUDPREAMPLDCCEN_MASK_SFT (0x1 << 1)
2806 #define RG_AUDPREAMPLDCPRECHARGE_MASK 0x1
2807 #define RG_AUDPREAMPLDCPRECHARGE_MASK_SFT (0x1 << 2)
2809 #define RG_AUDPREAMPLPGATEST_MASK 0x1
2810 #define RG_AUDPREAMPLPGATEST_MASK_SFT (0x1 << 3)
2821 #define RG_BULKL_VCM_EN_MASK 0x1
2822 #define RG_BULKL_VCM_EN_MASK_SFT (0x1 << 11)
2824 #define RG_AUDADCLPWRUP_MASK 0x1
2825 #define RG_AUDADCLPWRUP_MASK_SFT (0x1 << 12)
2832 #define RG_AUDPREAMPRON_MASK 0x1
2833 #define RG_AUDPREAMPRON_MASK_SFT (0x1 << 0)
2835 #define RG_AUDPREAMPRDCCEN_MASK 0x1
2836 #define RG_AUDPREAMPRDCCEN_MASK_SFT (0x1 << 1)
2838 #define RG_AUDPREAMPRDCPRECHARGE_MASK 0x1
2839 #define RG_AUDPREAMPRDCPRECHARGE_MASK_SFT (0x1 << 2)
2841 #define RG_AUDPREAMPRPGATEST_MASK 0x1
2842 #define RG_AUDPREAMPRPGATEST_MASK_SFT (0x1 << 3)
2853 #define RG_BULKR_VCM_EN_MASK 0x1
2854 #define RG_BULKR_VCM_EN_MASK_SFT (0x1 << 11)
2856 #define RG_AUDADCRPWRUP_MASK 0x1
2857 #define RG_AUDADCRPWRUP_MASK_SFT (0x1 << 12)
2864 #define RG_AUDPREAMP3ON_MASK 0x1
2865 #define RG_AUDPREAMP3ON_MASK_SFT (0x1 << 0)
2867 #define RG_AUDPREAMP3DCCEN_MASK 0x1
2868 #define RG_AUDPREAMP3DCCEN_MASK_SFT (0x1 << 1)
2870 #define RG_AUDPREAMP3DCPRECHARGE_MASK 0x1
2871 #define RG_AUDPREAMP3DCPRECHARGE_MASK_SFT (0x1 << 2)
2873 #define RG_AUDPREAMP3PGATEST_MASK 0x1
2874 #define RG_AUDPREAMP3PGATEST_MASK_SFT (0x1 << 3)
2885 #define RG_BULK3_VCM_EN_MASK 0x1
2886 #define RG_BULK3_VCM_EN_MASK_SFT (0x1 << 11)
2888 #define RG_AUDADC3PWRUP_MASK 0x1
2889 #define RG_AUDADC3PWRUP_MASK_SFT (0x1 << 12)
2896 #define RG_AUDULHALFBIAS_MASK 0x1
2897 #define RG_AUDULHALFBIAS_MASK_SFT (0x1 << 0)
2899 #define RG_AUDGLBVOWLPWEN_MASK 0x1
2900 #define RG_AUDGLBVOWLPWEN_MASK_SFT (0x1 << 1)
2902 #define RG_AUDPREAMPLPEN_MASK 0x1
2903 #define RG_AUDPREAMPLPEN_MASK_SFT (0x1 << 2)
2905 #define RG_AUDADC1STSTAGELPEN_MASK 0x1
2906 #define RG_AUDADC1STSTAGELPEN_MASK_SFT (0x1 << 3)
2908 #define RG_AUDADC2NDSTAGELPEN_MASK 0x1
2909 #define RG_AUDADC2NDSTAGELPEN_MASK_SFT (0x1 << 4)
2911 #define RG_AUDADCFLASHLPEN_MASK 0x1
2912 #define RG_AUDADCFLASHLPEN_MASK_SFT (0x1 << 5)
2931 #define RG_AUDRULHALFBIAS_MASK 0x1
2932 #define RG_AUDRULHALFBIAS_MASK_SFT (0x1 << 0)
2934 #define RG_AUDGLBRVOWLPWEN_MASK 0x1
2935 #define RG_AUDGLBRVOWLPWEN_MASK_SFT (0x1 << 1)
2937 #define RG_AUDRPREAMPLPEN_MASK 0x1
2938 #define RG_AUDRPREAMPLPEN_MASK_SFT (0x1 << 2)
2940 #define RG_AUDRADC1STSTAGELPEN_MASK 0x1
2941 #define RG_AUDRADC1STSTAGELPEN_MASK_SFT (0x1 << 3)
2943 #define RG_AUDRADC2NDSTAGELPEN_MASK 0x1
2944 #define RG_AUDRADC2NDSTAGELPEN_MASK_SFT (0x1 << 4)
2946 #define RG_AUDRADCFLASHLPEN_MASK 0x1
2947 #define RG_AUDRADCFLASHLPEN_MASK_SFT (0x1 << 5)
2966 #define RG_AUDADCCLKRSTB_MASK 0x1
2967 #define RG_AUDADCCLKRSTB_MASK_SFT (0x1 << 0)
2978 #define RG_AUDPREAMP_ACCFS_MASK 0x1
2979 #define RG_AUDPREAMP_ACCFS_MASK_SFT (0x1 << 7)
2981 #define RG_AUDPREAMPAAFEN_MASK 0x1
2982 #define RG_AUDPREAMPAAFEN_MASK_SFT (0x1 << 8)
2984 #define RG_DCCVCMBUFLPMODSEL_MASK 0x1
2985 #define RG_DCCVCMBUFLPMODSEL_MASK_SFT (0x1 << 9)
2987 #define RG_DCCVCMBUFLPSWEN_MASK 0x1
2988 #define RG_DCCVCMBUFLPSWEN_MASK_SFT (0x1 << 10)
2995 #define RG_AUDADC1STSTAGESDENB_MASK 0x1
2996 #define RG_AUDADC1STSTAGESDENB_MASK_SFT (0x1 << 0)
2998 #define RG_AUDADC2NDSTAGERESET_MASK 0x1
2999 #define RG_AUDADC2NDSTAGERESET_MASK_SFT (0x1 << 1)
3001 #define RG_AUDADC3RDSTAGERESET_MASK 0x1
3002 #define RG_AUDADC3RDSTAGERESET_MASK_SFT (0x1 << 2)
3004 #define RG_AUDADCFSRESET_MASK 0x1
3005 #define RG_AUDADCFSRESET_MASK_SFT (0x1 << 3)
3007 #define RG_AUDADCWIDECM_MASK 0x1
3008 #define RG_AUDADCWIDECM_MASK_SFT (0x1 << 4)
3010 #define RG_AUDADCNOPATEST_MASK 0x1
3011 #define RG_AUDADCNOPATEST_MASK_SFT (0x1 << 5)
3013 #define RG_AUDADCBYPASS_MASK 0x1
3014 #define RG_AUDADCBYPASS_MASK_SFT (0x1 << 6)
3016 #define RG_AUDADCFFBYPASS_MASK 0x1
3017 #define RG_AUDADCFFBYPASS_MASK_SFT (0x1 << 7)
3019 #define RG_AUDADCDACFBCURRENT_MASK 0x1
3020 #define RG_AUDADCDACFBCURRENT_MASK_SFT (0x1 << 8)
3025 #define RG_AUDADCDACNRZ_MASK 0x1
3026 #define RG_AUDADCDACNRZ_MASK_SFT (0x1 << 11)
3028 #define RG_AUDADCNODEM_MASK 0x1
3029 #define RG_AUDADCNODEM_MASK_SFT (0x1 << 12)
3031 #define RG_AUDADCDACTEST_MASK 0x1
3032 #define RG_AUDADCDACTEST_MASK_SFT (0x1 << 13)
3034 #define RG_AUDADCDAC0P25FS_MASK 0x1
3035 #define RG_AUDADCDAC0P25FS_MASK_SFT (0x1 << 14)
3037 #define RG_AUDADCRDAC0P25FS_MASK 0x1
3038 #define RG_AUDADCRDAC0P25FS_MASK_SFT (0x1 << 15)
3050 #define RG_AUDRCTUNELSEL_MASK 0x1
3051 #define RG_AUDRCTUNELSEL_MASK_SFT (0x1 << 5)
3056 #define RG_AUDRCTUNERSEL_MASK 0x1
3057 #define RG_AUDRCTUNERSEL_MASK_SFT (0x1 << 13)
3064 #define RG_AUD3CTUNELSEL_MASK 0x1
3065 #define RG_AUD3CTUNELSEL_MASK_SFT (0x1 << 5)
3091 #define RG_AUDPGA_DECAP_MASK 0x1
3092 #define RG_AUDPGA_DECAP_MASK_SFT (0x1 << 0)
3094 #define RG_AUDPGA_CAPRA_MASK 0x1
3095 #define RG_AUDPGA_CAPRA_MASK_SFT (0x1 << 1)
3097 #define RG_AUDPGA_ACCCMP_MASK 0x1
3098 #define RG_AUDPGA_ACCCMP_MASK_SFT (0x1 << 2)
3105 #define RG_AUDDIGMICEN_MASK 0x1
3106 #define RG_AUDDIGMICEN_MASK_SFT (0x1 << 0)
3111 #define RG_DMICHPCLKEN_MASK 0x1
3112 #define RG_DMICHPCLKEN_MASK_SFT (0x1 << 3)
3120 #define RG_DMICMONEN_MASK 0x1
3121 #define RG_DMICMONEN_MASK_SFT (0x1 << 8)
3128 #define RG_AUDDIGMIC1EN_MASK 0x1
3129 #define RG_AUDDIGMIC1EN_MASK_SFT (0x1 << 0)
3134 #define RG_DMIC1HPCLKEN_MASK 0x1
3135 #define RG_DMIC1HPCLKEN_MASK_SFT (0x1 << 3)
3143 #define RG_DMIC1MONEN_MASK 0x1
3144 #define RG_DMIC1MONEN_MASK_SFT (0x1 << 8)
3154 #define RG_AUDPWDBMICBIAS0_MASK 0x1
3155 #define RG_AUDPWDBMICBIAS0_MASK_SFT (0x1 << 0)
3157 #define RG_AUDMICBIAS0BYPASSEN_MASK 0x1
3158 #define RG_AUDMICBIAS0BYPASSEN_MASK_SFT (0x1 << 1)
3160 #define RG_AUDMICBIAS0LOWPEN_MASK 0x1
3161 #define RG_AUDMICBIAS0LOWPEN_MASK_SFT (0x1 << 2)
3163 #define RG_AUDPWDBMICBIAS3_MASK 0x1
3164 #define RG_AUDPWDBMICBIAS3_MASK_SFT (0x1 << 3)
3169 #define RG_AUDMICBIAS0DCSW0P1EN_MASK 0x1
3170 #define RG_AUDMICBIAS0DCSW0P1EN_MASK_SFT (0x1 << 8)
3172 #define RG_AUDMICBIAS0DCSW0P2EN_MASK 0x1
3173 #define RG_AUDMICBIAS0DCSW0P2EN_MASK_SFT (0x1 << 9)
3175 #define RG_AUDMICBIAS0DCSW0NEN_MASK 0x1
3176 #define RG_AUDMICBIAS0DCSW0NEN_MASK_SFT (0x1 << 10)
3178 #define RG_AUDMICBIAS0DCSW2P1EN_MASK 0x1
3179 #define RG_AUDMICBIAS0DCSW2P1EN_MASK_SFT (0x1 << 12)
3181 #define RG_AUDMICBIAS0DCSW2P2EN_MASK 0x1
3182 #define RG_AUDMICBIAS0DCSW2P2EN_MASK_SFT (0x1 << 13)
3184 #define RG_AUDMICBIAS0DCSW2NEN_MASK 0x1
3185 #define RG_AUDMICBIAS0DCSW2NEN_MASK_SFT (0x1 << 14)
3189 #define RG_AUDPWDBMICBIAS1_MASK 0x1
3190 #define RG_AUDPWDBMICBIAS1_MASK_SFT (0x1 << 0)
3192 #define RG_AUDMICBIAS1BYPASSEN_MASK 0x1
3193 #define RG_AUDMICBIAS1BYPASSEN_MASK_SFT (0x1 << 1)
3195 #define RG_AUDMICBIAS1LOWPEN_MASK 0x1
3196 #define RG_AUDMICBIAS1LOWPEN_MASK_SFT (0x1 << 2)
3201 #define RG_AUDMICBIAS1DCSW1PEN_MASK 0x1
3202 #define RG_AUDMICBIAS1DCSW1PEN_MASK_SFT (0x1 << 8)
3204 #define RG_AUDMICBIAS1DCSW1NEN_MASK 0x1
3205 #define RG_AUDMICBIAS1DCSW1NEN_MASK_SFT (0x1 << 9)
3207 #define RG_BANDGAPGEN_MASK 0x1
3208 #define RG_BANDGAPGEN_MASK_SFT (0x1 << 10)
3210 #define RG_AUDMICBIAS1HVEN_MASK 0x1
3211 #define RG_AUDMICBIAS1HVEN_MASK_SFT (0x1 << 12)
3213 #define RG_AUDMICBIAS1HVVREF_MASK 0x1
3214 #define RG_AUDMICBIAS1HVVREF_MASK_SFT (0x1 << 13)
3218 #define RG_AUDPWDBMICBIAS2_MASK 0x1
3219 #define RG_AUDPWDBMICBIAS2_MASK_SFT (0x1 << 0)
3221 #define RG_AUDMICBIAS2BYPASSEN_MASK 0x1
3222 #define RG_AUDMICBIAS2BYPASSEN_MASK_SFT (0x1 << 1)
3224 #define RG_AUDMICBIAS2LOWPEN_MASK 0x1
3225 #define RG_AUDMICBIAS2LOWPEN_MASK_SFT (0x1 << 2)
3230 #define RG_AUDMICBIAS2DCSW3P1EN_MASK 0x1
3231 #define RG_AUDMICBIAS2DCSW3P1EN_MASK_SFT (0x1 << 8)
3233 #define RG_AUDMICBIAS2DCSW3P2EN_MASK 0x1
3234 #define RG_AUDMICBIAS2DCSW3P2EN_MASK_SFT (0x1 << 9)
3236 #define RG_AUDMICBIAS2DCSW3NEN_MASK 0x1
3237 #define RG_AUDMICBIAS2DCSW3NEN_MASK_SFT (0x1 << 10)
3244 #define RG_AUDACCDETMICBIAS0PULLLOW_MASK 0x1
3245 #define RG_AUDACCDETMICBIAS0PULLLOW_MASK_SFT (0x1 << 0)
3247 #define RG_AUDACCDETMICBIAS1PULLLOW_MASK 0x1
3248 #define RG_AUDACCDETMICBIAS1PULLLOW_MASK_SFT (0x1 << 1)
3250 #define RG_AUDACCDETMICBIAS2PULLLOW_MASK 0x1
3251 #define RG_AUDACCDETMICBIAS2PULLLOW_MASK_SFT (0x1 << 2)
3253 #define RG_AUDACCDETVIN1PULLLOW_MASK 0x1
3254 #define RG_AUDACCDETVIN1PULLLOW_MASK_SFT (0x1 << 3)
3256 #define RG_AUDACCDETVTHACAL_MASK 0x1
3257 #define RG_AUDACCDETVTHACAL_MASK_SFT (0x1 << 4)
3259 #define RG_AUDACCDETVTHBCAL_MASK 0x1
3260 #define RG_AUDACCDETVTHBCAL_MASK_SFT (0x1 << 5)
3262 #define RG_AUDACCDETTVDET_MASK 0x1
3263 #define RG_AUDACCDETTVDET_MASK_SFT (0x1 << 6)
3265 #define RG_ACCDETSEL_MASK 0x1
3266 #define RG_ACCDETSEL_MASK_SFT (0x1 << 7)
3268 #define RG_SWBUFMODSEL_MASK 0x1
3269 #define RG_SWBUFMODSEL_MASK_SFT (0x1 << 8)
3271 #define RG_SWBUFSWEN_MASK 0x1
3272 #define RG_SWBUFSWEN_MASK_SFT (0x1 << 9)
3274 #define RG_EINT0NOHYS_MASK 0x1
3275 #define RG_EINT0NOHYS_MASK_SFT (0x1 << 10)
3277 #define RG_EINT0CONFIGACCDET_MASK 0x1
3278 #define RG_EINT0CONFIGACCDET_MASK_SFT (0x1 << 11)
3280 #define RG_EINT0HIRENB_MASK 0x1
3281 #define RG_EINT0HIRENB_MASK_SFT (0x1 << 12)
3283 #define RG_ACCDET2AUXRESBYPASS_MASK 0x1
3284 #define RG_ACCDET2AUXRESBYPASS_MASK_SFT (0x1 << 13)
3286 #define RG_ACCDET2AUXSWEN_MASK 0x1
3287 #define RG_ACCDET2AUXSWEN_MASK_SFT (0x1 << 14)
3289 #define RG_AUDACCDETMICBIAS3PULLLOW_MASK 0x1
3290 #define RG_AUDACCDETMICBIAS3PULLLOW_MASK_SFT (0x1 << 15)
3294 #define RG_EINT1CONFIGACCDET_MASK 0x1
3295 #define RG_EINT1CONFIGACCDET_MASK_SFT (0x1 << 0)
3297 #define RG_EINT1HIRENB_MASK 0x1
3298 #define RG_EINT1HIRENB_MASK_SFT (0x1 << 1)
3300 #define RG_EINT1NOHYS_MASK 0x1
3301 #define RG_EINT1NOHYS_MASK_SFT (0x1 << 2)
3306 #define RG_MTEST_EN_MASK 0x1
3307 #define RG_MTEST_EN_MASK_SFT (0x1 << 8)
3309 #define RG_MTEST_SEL_MASK 0x1
3310 #define RG_MTEST_SEL_MASK_SFT (0x1 << 9)
3312 #define RG_MTEST_CURRENT_MASK 0x1
3313 #define RG_MTEST_CURRENT_MASK_SFT (0x1 << 10)
3315 #define RG_ANALOGFDEN_MASK 0x1
3316 #define RG_ANALOGFDEN_MASK_SFT (0x1 << 12)
3318 #define RG_FDVIN1PPULLLOW_MASK 0x1
3319 #define RG_FDVIN1PPULLLOW_MASK_SFT (0x1 << 13)
3321 #define RG_FDEINT0TYPE_MASK 0x1
3322 #define RG_FDEINT0TYPE_MASK_SFT (0x1 << 14)
3324 #define RG_FDEINT1TYPE_MASK 0x1
3325 #define RG_FDEINT1TYPE_MASK_SFT (0x1 << 15)
3329 #define RG_EINT0CMPEN_MASK 0x1
3330 #define RG_EINT0CMPEN_MASK_SFT (0x1 << 0)
3332 #define RG_EINT0CMPMEN_MASK 0x1
3333 #define RG_EINT0CMPMEN_MASK_SFT (0x1 << 1)
3335 #define RG_EINT0EN_MASK 0x1
3336 #define RG_EINT0EN_MASK_SFT (0x1 << 2)
3338 #define RG_EINT0CEN_MASK 0x1
3339 #define RG_EINT0CEN_MASK_SFT (0x1 << 3)
3341 #define RG_EINT0INVEN_MASK 0x1
3342 #define RG_EINT0INVEN_MASK_SFT (0x1 << 4)
3347 #define RG_EINT1CMPEN_MASK 0x1
3348 #define RG_EINT1CMPEN_MASK_SFT (0x1 << 8)
3350 #define RG_EINT1CMPMEN_MASK 0x1
3351 #define RG_EINT1CMPMEN_MASK_SFT (0x1 << 9)
3353 #define RG_EINT1EN_MASK 0x1
3354 #define RG_EINT1EN_MASK_SFT (0x1 << 10)
3356 #define RG_EINT1CEN_MASK 0x1
3357 #define RG_EINT1CEN_MASK_SFT (0x1 << 11)
3359 #define RG_EINT1INVEN_MASK 0x1
3360 #define RG_EINT1INVEN_MASK_SFT (0x1 << 12)
3380 #define RG_CLKSQ_EN_MASK 0x1
3381 #define RG_CLKSQ_EN_MASK_SFT (0x1 << 0)
3383 #define RG_CLKSQ_IN_SEL_TEST_MASK 0x1
3384 #define RG_CLKSQ_IN_SEL_TEST_MASK_SFT (0x1 << 1)
3386 #define RG_CM_REFGENSEL_MASK 0x1
3387 #define RG_CM_REFGENSEL_MASK_SFT (0x1 << 2)
3389 #define RG_AUDIO_VOW_EN_MASK 0x1
3390 #define RG_AUDIO_VOW_EN_MASK_SFT (0x1 << 3)
3392 #define RG_CLKSQ_EN_VOW_MASK 0x1
3393 #define RG_CLKSQ_EN_VOW_MASK_SFT (0x1 << 4)
3395 #define RG_CLKAND_EN_VOW_MASK 0x1
3396 #define RG_CLKAND_EN_VOW_MASK_SFT (0x1 << 5)
3398 #define RG_VOWCLK_SEL_EN_VOW_MASK 0x1
3399 #define RG_VOWCLK_SEL_EN_VOW_MASK_SFT (0x1 << 6)
3406 #define RG_AUDDACLPWRUP_VAUDP32_MASK 0x1
3407 #define RG_AUDDACLPWRUP_VAUDP32_MASK_SFT (0x1 << 0)
3409 #define RG_AUDDACRPWRUP_VAUDP32_MASK 0x1
3410 #define RG_AUDDACRPWRUP_VAUDP32_MASK_SFT (0x1 << 1)
3412 #define RG_AUD_DAC_PWR_UP_VA32_MASK 0x1
3413 #define RG_AUD_DAC_PWR_UP_VA32_MASK_SFT (0x1 << 2)
3415 #define RG_AUD_DAC_PWL_UP_VA32_MASK 0x1
3416 #define RG_AUD_DAC_PWL_UP_VA32_MASK_SFT (0x1 << 3)
3418 #define RG_AUDHPLPWRUP_VAUDP32_MASK 0x1
3419 #define RG_AUDHPLPWRUP_VAUDP32_MASK_SFT (0x1 << 4)
3421 #define RG_AUDHPRPWRUP_VAUDP32_MASK 0x1
3422 #define RG_AUDHPRPWRUP_VAUDP32_MASK_SFT (0x1 << 5)
3424 #define RG_AUDHPLPWRUP_IBIAS_VAUDP32_MASK 0x1
3425 #define RG_AUDHPLPWRUP_IBIAS_VAUDP32_MASK_SFT (0x1 << 6)
3427 #define RG_AUDHPRPWRUP_IBIAS_VAUDP32_MASK 0x1
3428 #define RG_AUDHPRPWRUP_IBIAS_VAUDP32_MASK_SFT (0x1 << 7)
3436 #define RG_AUDHPLSCDISABLE_VAUDP32_MASK 0x1
3437 #define RG_AUDHPLSCDISABLE_VAUDP32_MASK_SFT (0x1 << 12)
3439 #define RG_AUDHPRSCDISABLE_VAUDP32_MASK 0x1
3440 #define RG_AUDHPRSCDISABLE_VAUDP32_MASK_SFT (0x1 << 13)
3442 #define RG_AUDHPLBSCCURRENT_VAUDP32_MASK 0x1
3443 #define RG_AUDHPLBSCCURRENT_VAUDP32_MASK_SFT (0x1 << 14)
3445 #define RG_AUDHPRBSCCURRENT_VAUDP32_MASK 0x1
3446 #define RG_AUDHPRBSCCURRENT_VAUDP32_MASK_SFT (0x1 << 15)
3450 #define RG_AUDHPLOUTPWRUP_VAUDP32_MASK 0x1
3451 #define RG_AUDHPLOUTPWRUP_VAUDP32_MASK_SFT (0x1 << 0)
3453 #define RG_AUDHPROUTPWRUP_VAUDP32_MASK 0x1
3454 #define RG_AUDHPROUTPWRUP_VAUDP32_MASK_SFT (0x1 << 1)
3456 #define RG_AUDHPLOUTAUXPWRUP_VAUDP32_MASK 0x1
3457 #define RG_AUDHPLOUTAUXPWRUP_VAUDP32_MASK_SFT (0x1 << 2)
3459 #define RG_AUDHPROUTAUXPWRUP_VAUDP32_MASK 0x1
3460 #define RG_AUDHPROUTAUXPWRUP_VAUDP32_MASK_SFT (0x1 << 3)
3462 #define RG_HPLAUXFBRSW_EN_VAUDP32_MASK 0x1
3463 #define RG_HPLAUXFBRSW_EN_VAUDP32_MASK_SFT (0x1 << 4)
3465 #define RG_HPRAUXFBRSW_EN_VAUDP32_MASK 0x1
3466 #define RG_HPRAUXFBRSW_EN_VAUDP32_MASK_SFT (0x1 << 5)
3468 #define RG_HPLSHORT2HPLAUX_EN_VAUDP32_MASK 0x1
3469 #define RG_HPLSHORT2HPLAUX_EN_VAUDP32_MASK_SFT (0x1 << 6)
3471 #define RG_HPRSHORT2HPRAUX_EN_VAUDP32_MASK 0x1
3472 #define RG_HPRSHORT2HPRAUX_EN_VAUDP32_MASK_SFT (0x1 << 7)
3488 #define RG_AUDHPSTARTUP_VAUDP32_MASK 0x1
3489 #define RG_AUDHPSTARTUP_VAUDP32_MASK_SFT (0x1 << 7)
3491 #define RG_AUDREFN_DERES_EN_VAUDP32_MASK 0x1
3492 #define RG_AUDREFN_DERES_EN_VAUDP32_MASK_SFT (0x1 << 8)
3494 #define RG_HPINPUTSTBENH_VAUDP32_MASK 0x1
3495 #define RG_HPINPUTSTBENH_VAUDP32_MASK_SFT (0x1 << 9)
3497 #define RG_HPINPUTRESET0_VAUDP32_MASK 0x1
3498 #define RG_HPINPUTRESET0_VAUDP32_MASK_SFT (0x1 << 10)
3500 #define RG_HPOUTPUTRESET0_VAUDP32_MASK 0x1
3501 #define RG_HPOUTPUTRESET0_VAUDP32_MASK_SFT (0x1 << 11)
3506 #define RG_AUDHPTRIM_EN_VAUDP32_MASK 0x1
3507 #define RG_AUDHPTRIM_EN_VAUDP32_MASK_SFT (0x1 << 15)
3537 #define RG_AUDHPCOMP_EN_VAUDP32_MASK 0x1
3538 #define RG_AUDHPCOMP_EN_VAUDP32_MASK_SFT (0x1 << 15)
3550 #define RG_AUDHSPWRUP_VAUDP32_MASK 0x1
3551 #define RG_AUDHSPWRUP_VAUDP32_MASK_SFT (0x1 << 0)
3553 #define RG_AUDHSPWRUP_IBIAS_VAUDP32_MASK 0x1
3554 #define RG_AUDHSPWRUP_IBIAS_VAUDP32_MASK_SFT (0x1 << 1)
3559 #define RG_AUDHSSCDISABLE_VAUDP32_MASK 0x1
3560 #define RG_AUDHSSCDISABLE_VAUDP32_MASK_SFT (0x1 << 4)
3562 #define RG_AUDHSBSCCURRENT_VAUDP32_MASK 0x1
3563 #define RG_AUDHSBSCCURRENT_VAUDP32_MASK_SFT (0x1 << 5)
3565 #define RG_AUDHSSTARTUP_VAUDP32_MASK 0x1
3566 #define RG_AUDHSSTARTUP_VAUDP32_MASK_SFT (0x1 << 6)
3568 #define RG_HSOUTPUTSTBENH_VAUDP32_MASK 0x1
3569 #define RG_HSOUTPUTSTBENH_VAUDP32_MASK_SFT (0x1 << 7)
3571 #define RG_HSINPUTSTBENH_VAUDP32_MASK 0x1
3572 #define RG_HSINPUTSTBENH_VAUDP32_MASK_SFT (0x1 << 8)
3574 #define RG_HSINPUTRESET0_VAUDP32_MASK 0x1
3575 #define RG_HSINPUTRESET0_VAUDP32_MASK_SFT (0x1 << 9)
3577 #define RG_HSOUTPUTRESET0_VAUDP32_MASK 0x1
3578 #define RG_HSOUTPUTRESET0_VAUDP32_MASK_SFT (0x1 << 10)
3580 #define RG_HSOUT_SHORTVCM_VAUDP32_MASK 0x1
3581 #define RG_HSOUT_SHORTVCM_VAUDP32_MASK_SFT (0x1 << 11)
3585 #define RG_AUDLOLPWRUP_VAUDP32_MASK 0x1
3586 #define RG_AUDLOLPWRUP_VAUDP32_MASK_SFT (0x1 << 0)
3588 #define RG_AUDLOLPWRUP_IBIAS_VAUDP32_MASK 0x1
3589 #define RG_AUDLOLPWRUP_IBIAS_VAUDP32_MASK_SFT (0x1 << 1)
3594 #define RG_AUDLOLSCDISABLE_VAUDP32_MASK 0x1
3595 #define RG_AUDLOLSCDISABLE_VAUDP32_MASK_SFT (0x1 << 4)
3597 #define RG_AUDLOLBSCCURRENT_VAUDP32_MASK 0x1
3598 #define RG_AUDLOLBSCCURRENT_VAUDP32_MASK_SFT (0x1 << 5)
3600 #define RG_AUDLOSTARTUP_VAUDP32_MASK 0x1
3601 #define RG_AUDLOSTARTUP_VAUDP32_MASK_SFT (0x1 << 6)
3603 #define RG_LOINPUTSTBENH_VAUDP32_MASK 0x1
3604 #define RG_LOINPUTSTBENH_VAUDP32_MASK_SFT (0x1 << 7)
3606 #define RG_LOOUTPUTSTBENH_VAUDP32_MASK 0x1
3607 #define RG_LOOUTPUTSTBENH_VAUDP32_MASK_SFT (0x1 << 8)
3609 #define RG_LOINPUTRESET0_VAUDP32_MASK 0x1
3610 #define RG_LOINPUTRESET0_VAUDP32_MASK_SFT (0x1 << 9)
3612 #define RG_LOOUTPUTRESET0_VAUDP32_MASK 0x1
3613 #define RG_LOOUTPUTRESET0_VAUDP32_MASK_SFT (0x1 << 10)
3615 #define RG_LOOUT_SHORTVCM_VAUDP32_MASK 0x1
3616 #define RG_LOOUT_SHORTVCM_VAUDP32_MASK_SFT (0x1 << 11)
3618 #define RG_AUDDACTPWRUP_VAUDP32_MASK 0x1
3619 #define RG_AUDDACTPWRUP_VAUDP32_MASK_SFT (0x1 << 12)
3621 #define RG_AUD_DAC_PWT_UP_VA32_MASK 0x1
3622 #define RG_AUD_DAC_PWT_UP_VA32_MASK_SFT (0x1 << 13)
3632 #define RG_AUDTRIMBUF_EN_VAUDP32_MASK 0x1
3633 #define RG_AUDTRIMBUF_EN_VAUDP32_MASK_SFT (0x1 << 6)
3641 #define RG_AUDHPSPKDET_EN_VAUDP32_MASK 0x1
3642 #define RG_AUDHPSPKDET_EN_VAUDP32_MASK_SFT (0x1 << 12)
3665 #define RG_AUDZCDCLKSEL_VAUDP32_MASK 0x1
3666 #define RG_AUDZCDCLKSEL_VAUDP32_MASK_SFT (0x1 << 3)
3676 #define RG_AUDIBIASPWRDN_VAUDP32_MASK 0x1
3677 #define RG_AUDIBIASPWRDN_VAUDP32_MASK_SFT (0x1 << 8)
3681 #define RG_RSTB_DECODER_VA32_MASK 0x1
3682 #define RG_RSTB_DECODER_VA32_MASK_SFT (0x1 << 0)
3684 #define RG_SEL_DECODER_96K_VA32_MASK 0x1
3685 #define RG_SEL_DECODER_96K_VA32_MASK_SFT (0x1 << 1)
3687 #define RG_SEL_DELAY_VCORE_MASK 0x1
3688 #define RG_SEL_DELAY_VCORE_MASK_SFT (0x1 << 2)
3690 #define RG_AUDGLB_PWRDN_VA32_MASK 0x1
3691 #define RG_AUDGLB_PWRDN_VA32_MASK_SFT (0x1 << 4)
3693 #define RG_AUDGLB_LP_VOW_EN_VA32_MASK 0x1
3694 #define RG_AUDGLB_LP_VOW_EN_VA32_MASK_SFT (0x1 << 5)
3696 #define RG_AUDGLB_LP2_VOW_EN_VA32_MASK 0x1
3697 #define RG_AUDGLB_LP2_VOW_EN_VA32_MASK_SFT (0x1 << 6)
3701 #define RG_LCLDO_DEC_EN_VA32_MASK 0x1
3702 #define RG_LCLDO_DEC_EN_VA32_MASK_SFT (0x1 << 0)
3704 #define RG_LCLDO_DEC_PDDIS_EN_VA18_MASK 0x1
3705 #define RG_LCLDO_DEC_PDDIS_EN_VA18_MASK_SFT (0x1 << 1)
3707 #define RG_LCLDO_DEC_REMOTE_SENSE_VA18_MASK 0x1
3708 #define RG_LCLDO_DEC_REMOTE_SENSE_VA18_MASK_SFT (0x1 << 2)
3710 #define RG_NVREG_EN_VAUDP32_MASK 0x1
3711 #define RG_NVREG_EN_VAUDP32_MASK_SFT (0x1 << 4)
3713 #define RG_NVREG_PULL0V_VAUDP32_MASK 0x1
3714 #define RG_NVREG_PULL0V_VAUDP32_MASK_SFT (0x1 << 5)
3721 #define RG_AUDZCDENABLE_MASK 0x1
3722 #define RG_AUDZCDENABLE_MASK_SFT (0x1 << 0)
3730 #define RG_AUDZCDTIMEOUTMODESEL_MASK 0x1
3731 #define RG_AUDZCDTIMEOUTMODESEL_MASK_SFT (0x1 << 6)