Lines Matching full:x1
21 #define RG_VOW13M_CK_PDN_MASK 0x1
22 #define RG_VOW13M_CK_PDN_MASK_SFT (0x1 << 13)
24 #define RG_VOW32K_CK_PDN_MASK 0x1
25 #define RG_VOW32K_CK_PDN_MASK_SFT (0x1 << 12)
27 #define RG_AUD_INTRP_CK_PDN_MASK 0x1
28 #define RG_AUD_INTRP_CK_PDN_MASK_SFT (0x1 << 8)
30 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK 0x1
31 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK_SFT (0x1 << 7)
33 #define RG_AUDNCP_CK_PDN_MASK 0x1
34 #define RG_AUDNCP_CK_PDN_MASK_SFT (0x1 << 6)
36 #define RG_ZCD13M_CK_PDN_MASK 0x1
37 #define RG_ZCD13M_CK_PDN_MASK_SFT (0x1 << 5)
39 #define RG_AUDIF_CK_PDN_MASK 0x1
40 #define RG_AUDIF_CK_PDN_MASK_SFT (0x1 << 2)
42 #define RG_AUD_CK_PDN_MASK 0x1
43 #define RG_AUD_CK_PDN_MASK_SFT (0x1 << 1)
45 #define RG_ACCDET_CK_PDN_MASK 0x1
46 #define RG_ACCDET_CK_PDN_MASK_SFT (0x1 << 0)
60 #define RG_AUDIF_CK_CKSEL_MASK 0x1
61 #define RG_AUDIF_CK_CKSEL_MASK_SFT (0x1 << 3)
63 #define RG_AUD_CK_CKSEL_MASK 0x1
64 #define RG_AUD_CK_CKSEL_MASK_SFT (0x1 << 2)
78 #define RG_VOW13M_CK_TSTSEL_MASK 0x1
79 #define RG_VOW13M_CK_TSTSEL_MASK_SFT (0x1 << 9)
81 #define RG_VOW13M_CK_TST_DIS_MASK 0x1
82 #define RG_VOW13M_CK_TST_DIS_MASK_SFT (0x1 << 8)
84 #define RG_AUD26M_CK_TSTSEL_MASK 0x1
85 #define RG_AUD26M_CK_TSTSEL_MASK_SFT (0x1 << 4)
87 #define RG_AUDIF_CK_TSTSEL_MASK 0x1
88 #define RG_AUDIF_CK_TSTSEL_MASK_SFT (0x1 << 3)
90 #define RG_AUD_CK_TSTSEL_MASK 0x1
91 #define RG_AUD_CK_TSTSEL_MASK_SFT (0x1 << 2)
93 #define RG_AUD26M_CK_TST_DIS_MASK 0x1
94 #define RG_AUD26M_CK_TST_DIS_MASK_SFT (0x1 << 0)
98 #define RG_AUD_INTRP_CK_PDN_HWEN_MASK 0x1
99 #define RG_AUD_INTRP_CK_PDN_HWEN_MASK_SFT (0x1 << 0)
113 #define RG_AUDNCP_RST_MASK 0x1
114 #define RG_AUDNCP_RST_MASK_SFT (0x1 << 3)
116 #define RG_ZCD_RST_MASK 0x1
117 #define RG_ZCD_RST_MASK_SFT (0x1 << 2)
119 #define RG_ACCDET_RST_MASK 0x1
120 #define RG_ACCDET_RST_MASK_SFT (0x1 << 1)
122 #define RG_AUDIO_RST_MASK 0x1
123 #define RG_AUDIO_RST_MASK_SFT (0x1 << 0)
137 #define BANK_AUDZCD_SWRST_MASK 0x1
138 #define BANK_AUDZCD_SWRST_MASK_SFT (0x1 << 2)
140 #define BANK_AUDIO_SWRST_MASK 0x1
141 #define BANK_AUDIO_SWRST_MASK_SFT (0x1 << 1)
143 #define BANK_ACCDET_SWRST_MASK 0x1
144 #define BANK_ACCDET_SWRST_MASK_SFT (0x1 << 0)
148 #define RG_INT_EN_AUDIO_MASK 0x1
149 #define RG_INT_EN_AUDIO_MASK_SFT (0x1 << 0)
151 #define RG_INT_EN_ACCDET_MASK 0x1
152 #define RG_INT_EN_ACCDET_MASK_SFT (0x1 << 5)
154 #define RG_INT_EN_ACCDET_EINT0_MASK 0x1
155 #define RG_INT_EN_ACCDET_EINT0_MASK_SFT (0x1 << 6)
157 #define RG_INT_EN_ACCDET_EINT1_MASK 0x1
158 #define RG_INT_EN_ACCDET_EINT1_MASK_SFT (0x1 << 7)
172 #define RG_INT_MASK_AUDIO_MASK 0x1
173 #define RG_INT_MASK_AUDIO_MASK_SFT (0x1 << 0)
175 #define RG_INT_MASK_ACCDET_MASK 0x1
176 #define RG_INT_MASK_ACCDET_MASK_SFT (0x1 << 5)
178 #define RG_INT_MASK_ACCDET_EINT0_MASK 0x1
179 #define RG_INT_MASK_ACCDET_EINT0_MASK_SFT (0x1 << 6)
181 #define RG_INT_MASK_ACCDET_EINT1_MASK 0x1
182 #define RG_INT_MASK_ACCDET_EINT1_MASK_SFT (0x1 << 7)
196 #define RG_INT_STATUS_AUDIO_MASK 0x1
197 #define RG_INT_STATUS_AUDIO_MASK_SFT (0x1 << 0)
199 #define RG_INT_STATUS_ACCDET_MASK 0x1
200 #define RG_INT_STATUS_ACCDET_MASK_SFT (0x1 << 5)
202 #define RG_INT_STATUS_ACCDET_EINT0_MASK 0x1
203 #define RG_INT_STATUS_ACCDET_EINT0_MASK_SFT (0x1 << 6)
205 #define RG_INT_STATUS_ACCDET_EINT1_MASK 0x1
206 #define RG_INT_STATUS_ACCDET_EINT1_MASK_SFT (0x1 << 7)
210 #define RG_INT_RAW_STATUS_AUDIO_MASK 0x1
211 #define RG_INT_RAW_STATUS_AUDIO_MASK_SFT (0x1 << 0)
213 #define RG_INT_RAW_STATUS_ACCDET_MASK 0x1
214 #define RG_INT_RAW_STATUS_ACCDET_MASK_SFT (0x1 << 5)
216 #define RG_INT_RAW_STATUS_ACCDET_EINT0_MASK 0x1
217 #define RG_INT_RAW_STATUS_ACCDET_EINT0_MASK_SFT (0x1 << 6)
219 #define RG_INT_RAW_STATUS_ACCDET_EINT1_MASK 0x1
220 #define RG_INT_RAW_STATUS_ACCDET_EINT1_MASK_SFT (0x1 << 7)
224 #define RG_AUD_TOP_INT_POLARITY_MASK 0x1
225 #define RG_AUD_TOP_INT_POLARITY_MASK_SFT (0x1 << 0)
229 #define RG_DIVCKS_CHG_MASK 0x1
230 #define RG_DIVCKS_CHG_MASK_SFT (0x1 << 0)
234 #define RG_DIVCKS_ON_MASK 0x1
235 #define RG_DIVCKS_ON_MASK_SFT (0x1 << 0)
244 #define RG_DIVCKS_PWD_NCP_MASK 0x1
245 #define RG_DIVCKS_PWD_NCP_MASK_SFT (0x1 << 0)
260 #define RG_AUD_CLK_INT_MON_FLAG_EN_MASK 0x1
261 #define RG_AUD_CLK_INT_MON_FLAG_EN_MASK_SFT (0x1 << 11)
303 #define AFE_UL_LR_SWAP_MASK 0x1
304 #define AFE_UL_LR_SWAP_MASK_SFT (0x1 << 15)
306 #define AFE_DL_LR_SWAP_MASK 0x1
307 #define AFE_DL_LR_SWAP_MASK_SFT (0x1 << 14)
309 #define AFE_ON_MASK 0x1
310 #define AFE_ON_MASK_SFT (0x1 << 0)
314 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK 0x1
315 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0)
325 #define C_TWO_DIGITAL_MIC_CTL_MASK 0x1
326 #define C_TWO_DIGITAL_MIC_CTL_MASK_SFT (0x1 << 7)
333 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1
334 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)
336 #define UL_LOOP_BACK_MODE_CTL_MASK 0x1
337 #define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)
339 #define UL_SDM_3_LEVEL_CTL_MASK 0x1
340 #define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)
342 #define UL_SRC_ON_TMP_CTL_MASK 0x1
343 #define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)
347 #define MTKAIF_SINE_ON_MASK 0x1
348 #define MTKAIF_SINE_ON_MASK_SFT (0x1 << 2)
350 #define UL_SINE_ON_MASK 0x1
351 #define UL_SINE_ON_MASK_SFT (0x1 << 1)
353 #define DL_SINE_ON_MASK 0x1
354 #define DL_SINE_ON_MASK_SFT (0x1 << 0)
358 #define PDN_AFE_CTL_MASK 0x1
359 #define PDN_AFE_CTL_MASK_SFT (0x1 << 7)
361 #define PDN_DAC_CTL_MASK 0x1
362 #define PDN_DAC_CTL_MASK_SFT (0x1 << 6)
364 #define PDN_ADC_CTL_MASK 0x1
365 #define PDN_ADC_CTL_MASK_SFT (0x1 << 5)
367 #define PDN_I2S_DL_CTL_MASK 0x1
368 #define PDN_I2S_DL_CTL_MASK_SFT (0x1 << 3)
370 #define PWR_CLK_DIS_CTL_MASK 0x1
371 #define PWR_CLK_DIS_CTL_MASK_SFT (0x1 << 2)
373 #define PDN_AFE_TESTMODEL_CTL_MASK 0x1
374 #define PDN_AFE_TESTMODEL_CTL_MASK_SFT (0x1 << 1)
376 #define PDN_RESERVED_MASK 0x1
377 #define PDN_RESERVED_MASK_SFT (0x1 << 0)
392 #define CCI_AUD_ANACK_SEL_MASK 0x1
393 #define CCI_AUD_ANACK_SEL_MASK_SFT (0x1 << 15)
398 #define CCI_SCRAMBLER_CG_EN_MASK 0x1
399 #define CCI_SCRAMBLER_CG_EN_MASK_SFT (0x1 << 11)
401 #define CCI_LCH_INV_MASK 0x1
402 #define CCI_LCH_INV_MASK_SFT (0x1 << 10)
404 #define CCI_RAND_EN_MASK 0x1
405 #define CCI_RAND_EN_MASK_SFT (0x1 << 9)
407 #define CCI_SPLT_SCRMB_CLK_ON_MASK 0x1
408 #define CCI_SPLT_SCRMB_CLK_ON_MASK_SFT (0x1 << 8)
410 #define CCI_SPLT_SCRMB_ON_MASK 0x1
411 #define CCI_SPLT_SCRMB_ON_MASK_SFT (0x1 << 7)
413 #define CCI_AUD_IDAC_TEST_EN_MASK 0x1
414 #define CCI_AUD_IDAC_TEST_EN_MASK_SFT (0x1 << 6)
416 #define CCI_ZERO_PAD_DISABLE_MASK 0x1
417 #define CCI_ZERO_PAD_DISABLE_MASK_SFT (0x1 << 5)
419 #define CCI_AUD_SPLIT_TEST_EN_MASK 0x1
420 #define CCI_AUD_SPLIT_TEST_EN_MASK_SFT (0x1 << 4)
422 #define CCI_AUD_SDM_MUTEL_MASK 0x1
423 #define CCI_AUD_SDM_MUTEL_MASK_SFT (0x1 << 3)
425 #define CCI_AUD_SDM_MUTER_MASK 0x1
426 #define CCI_AUD_SDM_MUTER_MASK_SFT (0x1 << 2)
428 #define CCI_AUD_SDM_7BIT_SEL_MASK 0x1
429 #define CCI_AUD_SDM_7BIT_SEL_MASK_SFT (0x1 << 1)
431 #define CCI_SCRAMBLER_EN_MASK 0x1
432 #define CCI_SCRAMBLER_EN_MASK_SFT (0x1 << 0)
444 #define CCI_AUD_DAC_ANA_MUTE_MASK 0x1
445 #define CCI_AUD_DAC_ANA_MUTE_MASK_SFT (0x1 << 7)
447 #define CCI_AUD_DAC_ANA_RSTB_SEL_MASK 0x1
448 #define CCI_AUD_DAC_ANA_RSTB_SEL_MASK_SFT (0x1 << 6)
450 #define CCI_AUDIO_FIFO_CLKIN_INV_MASK 0x1
451 #define CCI_AUDIO_FIFO_CLKIN_INV_MASK_SFT (0x1 << 4)
453 #define CCI_AUDIO_FIFO_ENABLE_MASK 0x1
454 #define CCI_AUDIO_FIFO_ENABLE_MASK_SFT (0x1 << 3)
456 #define CCI_ACD_MODE_MASK 0x1
457 #define CCI_ACD_MODE_MASK_SFT (0x1 << 2)
459 #define CCI_AFIFO_CLK_PWDB_MASK 0x1
460 #define CCI_AFIFO_CLK_PWDB_MASK_SFT (0x1 << 1)
462 #define CCI_ACD_FUNC_RSTB_MASK 0x1
463 #define CCI_ACD_FUNC_RSTB_MASK_SFT (0x1 << 0)
467 #define SDM_ANA13M_TESTCK_SEL_MASK 0x1
468 #define SDM_ANA13M_TESTCK_SEL_MASK_SFT (0x1 << 15)
479 #define DIGMIC_TESTCK_SEL_MASK 0x1
480 #define DIGMIC_TESTCK_SEL_MASK_SFT (0x1 << 0)
484 #define UL_FIFO_WCLK_INV_MASK 0x1
485 #define UL_FIFO_WCLK_INV_MASK_SFT (0x1 << 8)
487 #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK 0x1
488 #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 6)
490 #define UL_FIFO_WDATA_TESTEN_MASK 0x1
491 #define UL_FIFO_WDATA_TESTEN_MASK_SFT (0x1 << 5)
493 #define UL_FIFO_WDATA_TESTSRC_SEL_MASK 0x1
494 #define UL_FIFO_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 4)
496 #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK 0x1
497 #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK_SFT (0x1 << 3)
524 #define R_AUD_DAC_MONO_SEL_MASK 0x1
525 #define R_AUD_DAC_MONO_SEL_MASK_SFT (0x1 << 3)
527 #define R_AUD_DAC_SW_RSTB_MASK 0x1
528 #define R_AUD_DAC_SW_RSTB_MASK_SFT (0x1 << 0)
540 #define ASYNC_TEST_OUT_BCK_MASK 0x1
541 #define ASYNC_TEST_OUT_BCK_MASK_SFT (0x1 << 15)
554 #define RG_MTKAIF_RXIF_FIFO_INTEN_MASK 0x1
555 #define RG_MTKAIF_RXIF_FIFO_INTEN_MASK_SFT (0x1 << 0)
559 #define MTKAIF_RXIF_WR_FULL_STATUS_MASK 0x1
560 #define MTKAIF_RXIF_WR_FULL_STATUS_MASK_SFT (0x1 << 1)
562 #define MTKAIF_RXIF_RD_EMPTY_STATUS_MASK 0x1
563 #define MTKAIF_RXIF_RD_EMPTY_STATUS_MASK_SFT (0x1 << 0)
567 #define MTKAIFTX_V3_SYNC_OUT_MASK 0x1
568 #define MTKAIFTX_V3_SYNC_OUT_MASK_SFT (0x1 << 14)
570 #define MTKAIFTX_V3_SDATA_OUT2_MASK 0x1
571 #define MTKAIFTX_V3_SDATA_OUT2_MASK_SFT (0x1 << 13)
573 #define MTKAIFTX_V3_SDATA_OUT1_MASK 0x1
574 #define MTKAIFTX_V3_SDATA_OUT1_MASK_SFT (0x1 << 12)
581 #define MTKAIFRX_V3_SYNC_IN_MASK 0x1
582 #define MTKAIFRX_V3_SYNC_IN_MASK_SFT (0x1 << 14)
584 #define MTKAIFRX_V3_SDATA_IN2_MASK 0x1
585 #define MTKAIFRX_V3_SDATA_IN2_MASK_SFT (0x1 << 13)
587 #define MTKAIFRX_V3_SDATA_IN1_MASK 0x1
588 #define MTKAIFRX_V3_SDATA_IN1_MASK_SFT (0x1 << 12)
590 #define MTKAIF_RXIF_SEARCH_FAIL_FLAG_MASK 0x1
591 #define MTKAIF_RXIF_SEARCH_FAIL_FLAG_MASK_SFT (0x1 << 11)
593 #define MTKAIF_RXIF_INVALID_FLAG_MASK 0x1
594 #define MTKAIF_RXIF_INVALID_FLAG_MASK_SFT (0x1 << 8)
617 #define RG_MTKAIF_RXIF_CLKINV_MASK 0x1
618 #define RG_MTKAIF_RXIF_CLKINV_MASK_SFT (0x1 << 15)
620 #define RG_MTKAIF_RXIF_PROTOCOL2_MASK 0x1
621 #define RG_MTKAIF_RXIF_PROTOCOL2_MASK_SFT (0x1 << 8)
626 #define RG_MTKAIF_BYPASS_SRC_TEST_MASK 0x1
627 #define RG_MTKAIF_BYPASS_SRC_TEST_MASK_SFT (0x1 << 5)
629 #define RG_MTKAIF_TXIF_PROTOCOL2_MASK 0x1
630 #define RG_MTKAIF_TXIF_PROTOCOL2_MASK_SFT (0x1 << 4)
632 #define RG_MTKAIF_PMIC_TXIF_8TO5_MASK 0x1
633 #define RG_MTKAIF_PMIC_TXIF_8TO5_MASK_SFT (0x1 << 2)
635 #define RG_MTKAIF_LOOPBACK_TEST2_MASK 0x1
636 #define RG_MTKAIF_LOOPBACK_TEST2_MASK_SFT (0x1 << 1)
638 #define RG_MTKAIF_LOOPBACK_TEST1_MASK 0x1
639 #define RG_MTKAIF_LOOPBACK_TEST1_MASK_SFT (0x1 << 0)
652 #define RG_MTKAIF_RXIF_DETECT_ON_MASK 0x1
653 #define RG_MTKAIF_RXIF_DETECT_ON_MASK_SFT (0x1 << 3)
655 #define RG_MTKAIF_RXIF_DATA_MODE_MASK 0x1
656 #define RG_MTKAIF_RXIF_DATA_MODE_MASK_SFT (0x1 << 0)
674 #define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK 0x1
675 #define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK_SFT (0x1 << 12)
682 #define RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_MASK 0x1
683 #define RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_MASK_SFT (0x1 << 7)
688 #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK 0x1
689 #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT (0x1 << 3)
704 #define SGEN_DAC_EN_CTL_MASK 0x1
705 #define SGEN_DAC_EN_CTL_MASK_SFT (0x1 << 7)
707 #define SGEN_MUTE_SW_CTL_MASK 0x1
708 #define SGEN_MUTE_SW_CTL_MASK_SFT (0x1 << 6)
710 #define R_AUD_SDM_MUTE_L_MASK 0x1
711 #define R_AUD_SDM_MUTE_L_MASK_SFT (0x1 << 5)
713 #define R_AUD_SDM_MUTE_R_MASK 0x1
714 #define R_AUD_SDM_MUTE_R_MASK_SFT (0x1 << 4)
718 #define C_SGEN_RCH_INV_5BIT_MASK 0x1
719 #define C_SGEN_RCH_INV_5BIT_MASK_SFT (0x1 << 15)
721 #define C_SGEN_RCH_INV_8BIT_MASK 0x1
722 #define C_SGEN_RCH_INV_8BIT_MASK_SFT (0x1 << 14)
729 #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK 0x1
730 #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK_SFT (0x1 << 5)
732 #define RG_UL_ASYNC_FIFO_SOFT_RST_MASK 0x1
733 #define RG_UL_ASYNC_FIFO_SOFT_RST_MASK_SFT (0x1 << 4)
735 #define RG_AMIC_UL_ADC_CLK_SEL_MASK 0x1
736 #define RG_AMIC_UL_ADC_CLK_SEL_MASK_SFT (0x1 << 1)
743 #define DCCLK_INV_MASK 0x1
744 #define DCCLK_INV_MASK_SFT (0x1 << 4)
746 #define DCCLK_PDN_MASK 0x1
747 #define DCCLK_PDN_MASK_SFT (0x1 << 1)
749 #define DCCLK_GEN_ON_MASK 0x1
750 #define DCCLK_GEN_ON_MASK_SFT (0x1 << 0)
757 #define RESYNC_SRC_CK_INV_MASK 0x1
758 #define RESYNC_SRC_CK_INV_MASK_SFT (0x1 << 9)
760 #define DCCLK_RESYNC_BYPASS_MASK 0x1
761 #define DCCLK_RESYNC_BYPASS_MASK_SFT (0x1 << 8)
768 #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK 0x1
769 #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT (0x1 << 15)
774 #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK 0x1
775 #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT (0x1 << 7)
785 #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK 0x1
786 #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK_SFT (0x1 << 11)
788 #define RG_AUD_PAD_TOP_TX_FIFO_ON_MASK 0x1
789 #define RG_AUD_PAD_TOP_TX_FIFO_ON_MASK_SFT (0x1 << 8)
803 #define NLE_RCH_HPGAIN_SEL_MASK 0x1
804 #define NLE_RCH_HPGAIN_SEL_MASK_SFT (0x1 << 10)
806 #define NLE_RCH_CH_SEL_MASK 0x1
807 #define NLE_RCH_CH_SEL_MASK_SFT (0x1 << 9)
809 #define NLE_RCH_ON_MASK 0x1
810 #define NLE_RCH_ON_MASK_SFT (0x1 << 8)
812 #define NLE_LCH_HPGAIN_SEL_MASK 0x1
813 #define NLE_LCH_HPGAIN_SEL_MASK_SFT (0x1 << 2)
815 #define NLE_LCH_CH_SEL_MASK 0x1
816 #define NLE_LCH_CH_SEL_MASK_SFT (0x1 << 1)
818 #define NLE_LCH_ON_MASK 0x1
819 #define NLE_LCH_ON_MASK_SFT (0x1 << 0)
833 #define PDN_VOW_MASK 0x1
834 #define PDN_VOW_MASK_SFT (0x1 << 15)
836 #define VOW_1P6M_800K_SEL_MASK 0x1
837 #define VOW_1P6M_800K_SEL_MASK_SFT (0x1 << 14)
839 #define VOW_DIGMIC_ON_MASK 0x1
840 #define VOW_DIGMIC_ON_MASK_SFT (0x1 << 13)
842 #define VOW_CK_DIV_RST_MASK 0x1
843 #define VOW_CK_DIV_RST_MASK_SFT (0x1 << 12)
845 #define VOW_ON_MASK 0x1
846 #define VOW_ON_MASK_SFT (0x1 << 11)
851 #define MAIN_DMIC_CK_VOW_SEL_MASK 0x1
852 #define MAIN_DMIC_CK_VOW_SEL_MASK_SFT (0x1 << 7)
854 #define VOW_SDM_3_LEVEL_MASK 0x1
855 #define VOW_SDM_3_LEVEL_MASK_SFT (0x1 << 6)
857 #define VOW_LOOP_BACK_MODE_MASK 0x1
858 #define VOW_LOOP_BACK_MODE_MASK_SFT (0x1 << 5)
860 #define VOW_INTR_SOURCE_SEL_MASK 0x1
861 #define VOW_INTR_SOURCE_SEL_MASK_SFT (0x1 << 4)
863 #define VOW_INTR_CLR_MASK 0x1
864 #define VOW_INTR_CLR_MASK_SFT (0x1 << 3)
866 #define S_N_VALUE_RST_MASK 0x1
867 #define S_N_VALUE_RST_MASK_SFT (0x1 << 2)
869 #define SAMPLE_BASE_MODE_MASK 0x1
870 #define SAMPLE_BASE_MODE_MASK_SFT (0x1 << 1)
872 #define VOW_INTR_FLAG_MASK 0x1
873 #define VOW_INTR_FLAG_MASK_SFT (0x1 << 0)
915 #define VOW_TXIF_SCK_INV_MASK 0x1
916 #define VOW_TXIF_SCK_INV_MASK_SFT (0x1 << 15)
921 #define VOW_ADC_TESTCK_SEL_MASK 0x1
922 #define VOW_ADC_TESTCK_SEL_MASK_SFT (0x1 << 11)
924 #define VOW_ADC_CLK_INV_MASK 0x1
925 #define VOW_ADC_CLK_INV_MASK_SFT (0x1 << 10)
927 #define VOW_TXIF_MONO_MASK 0x1
928 #define VOW_TXIF_MONO_MASK_SFT (0x1 << 9)
943 #define RG_WINDOW_SIZE_SEL_MASK 0x1
944 #define RG_WINDOW_SIZE_SEL_MASK_SFT (0x1 << 12)
946 #define RG_FLR_BYPASS_MASK 0x1
947 #define RG_FLR_BYPASS_MASK_SFT (0x1 << 11)
952 #define RG_BUCK_DVFS_DONE_SW_CTL_MASK 0x1
953 #define RG_BUCK_DVFS_DONE_SW_CTL_MASK_SFT (0x1 << 7)
955 #define RG_BUCK_DVFS_DONE_HW_MODE_MASK 0x1
956 #define RG_BUCK_DVFS_DONE_HW_MODE_MASK_SFT (0x1 << 6)
980 #define SECOND_CNT_START_MASK 0x1
981 #define SECOND_CNT_START_MASK_SFT (0x1 << 0)
1005 #define VOW_SN_INI_CFG_EN_MASK 0x1
1006 #define VOW_SN_INI_CFG_EN_MASK_SFT (0x1 << 15)
1013 #define VOW_TGEN_EN_MASK 0x1
1014 #define VOW_TGEN_EN_MASK_SFT (0x1 << 15)
1016 #define VOW_TGEN_MUTE_SW_MASK 0x1
1017 #define VOW_TGEN_MUTE_SW_MASK_SFT (0x1 << 14)
1024 #define BUCK_DVFS_DONE_MASK 0x1
1025 #define BUCK_DVFS_DONE_MASK_SFT (0x1 << 15)
1027 #define VOW_32K_MODE_MASK 0x1
1028 #define VOW_32K_MODE_MASK_SFT (0x1 << 13)
1033 #define RG_A1P6M_EN_SEL_MASK 0x1
1034 #define RG_A1P6M_EN_SEL_MASK_SFT (0x1 << 7)
1036 #define VOW_CLK_SEL_MASK 0x1
1037 #define VOW_CLK_SEL_MASK_SFT (0x1 << 6)
1039 #define VOW_INTR_SW_MODE_MASK 0x1
1040 #define VOW_INTR_SW_MODE_MASK_SFT (0x1 << 5)
1042 #define VOW_INTR_SW_VAL_MASK 0x1
1043 #define VOW_INTR_SW_VAL_MASK_SFT (0x1 << 4)
1056 #define VOW_IRQ_LATCH_SNR_EN_MASK 0x1
1057 #define VOW_IRQ_LATCH_SNR_EN_MASK_SFT (0x1 << 10)
1059 #define VOW_DMICCLK_PDN_MASK 0x1
1060 #define VOW_DMICCLK_PDN_MASK_SFT (0x1 << 9)
1062 #define VOW_POSDIVCLK_PDN_MASK 0x1
1063 #define VOW_POSDIVCLK_PDN_MASK_SFT (0x1 << 8)
1068 #define RG_MTKAIF_HPF_BYPASS_MASK 0x1
1069 #define RG_MTKAIF_HPF_BYPASS_MASK_SFT (0x1 << 2)
1071 #define RG_SNRDET_HPF_BYPASS_MASK 0x1
1072 #define RG_SNRDET_HPF_BYPASS_MASK_SFT (0x1 << 1)
1074 #define RG_HPF_ON_MASK 0x1
1075 #define RG_HPF_ON_MASK_SFT (0x1 << 0)
1079 #define RG_PERIODIC_EN_MASK 0x1
1080 #define RG_PERIODIC_EN_MASK_SFT (0x1 << 15)
1082 #define RG_PERIODIC_CNT_CLR_MASK 0x1
1083 #define RG_PERIODIC_CNT_CLR_MASK_SFT (0x1 << 14)
1090 #define RG_PERIODIC_CNT_SET_MASK 0x1
1091 #define RG_PERIODIC_CNT_SET_MASK_SFT (0x1 << 15)
1093 #define RG_PERIODIC_CNT_PAUSE_MASK 0x1
1094 #define RG_PERIODIC_CNT_PAUSE_MASK_SFT (0x1 << 14)
1101 #define AUDPREAMPLON_PERIODIC_MODE_MASK 0x1
1102 #define AUDPREAMPLON_PERIODIC_MODE_MASK_SFT (0x1 << 15)
1104 #define AUDPREAMPLON_PERIODIC_INVERSE_MASK 0x1
1105 #define AUDPREAMPLON_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
1112 #define AUDPREAMPLDCPRECHARGE_PERIODIC_MODE_MASK 0x1
1113 #define AUDPREAMPLDCPRECHARGE_PERIODIC_MODE_MASK_SFT (0x1 << 15)
1115 #define AUDPREAMPLDCPRECHARGE_PERIODIC_INVERSE_MASK 0x1
1116 #define AUDPREAMPLDCPRECHARGE_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
1123 #define AUDADCLPWRUP_PERIODIC_MODE_MASK 0x1
1124 #define AUDADCLPWRUP_PERIODIC_MODE_MASK_SFT (0x1 << 15)
1126 #define AUDADCLPWRUP_PERIODIC_INVERSE_MASK 0x1
1127 #define AUDADCLPWRUP_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
1134 #define AUDGLBVOWLPWEN_PERIODIC_MODE_MASK 0x1
1135 #define AUDGLBVOWLPWEN_PERIODIC_MODE_MASK_SFT (0x1 << 15)
1137 #define AUDGLBVOWLPWEN_PERIODIC_INVERSE_MASK 0x1
1138 #define AUDGLBVOWLPWEN_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
1145 #define AUDDIGMICEN_PERIODIC_MODE_MASK 0x1
1146 #define AUDDIGMICEN_PERIODIC_MODE_MASK_SFT (0x1 << 15)
1148 #define AUDDIGMICEN_PERIODIC_INVERSE_MASK 0x1
1149 #define AUDDIGMICEN_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
1156 #define AUDPWDBMICBIAS0_PERIODIC_MODE_MASK 0x1
1157 #define AUDPWDBMICBIAS0_PERIODIC_MODE_MASK_SFT (0x1 << 15)
1159 #define AUDPWDBMICBIAS0_PERIODIC_INVERSE_MASK 0x1
1160 #define AUDPWDBMICBIAS0_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
1167 #define AUDPWDBMICBIAS1_PERIODIC_MODE_MASK 0x1
1168 #define AUDPWDBMICBIAS1_PERIODIC_MODE_MASK_SFT (0x1 << 15)
1170 #define AUDPWDBMICBIAS1_PERIODIC_INVERSE_MASK 0x1
1171 #define AUDPWDBMICBIAS1_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
1178 #define XO_VOW_CK_EN_PERIODIC_MODE_MASK 0x1
1179 #define XO_VOW_CK_EN_PERIODIC_MODE_MASK_SFT (0x1 << 15)
1181 #define XO_VOW_CK_EN_PERIODIC_INVERSE_MASK 0x1
1182 #define XO_VOW_CK_EN_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
1189 #define AUDGLB_PWRDN_PERIODIC_MODE_MASK 0x1
1190 #define AUDGLB_PWRDN_PERIODIC_MODE_MASK_SFT (0x1 << 15)
1192 #define AUDGLB_PWRDN_PERIODIC_INVERSE_MASK 0x1
1193 #define AUDGLB_PWRDN_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
1200 #define VOW_ON_PERIODIC_MODE_MASK 0x1
1201 #define VOW_ON_PERIODIC_MODE_MASK_SFT (0x1 << 15)
1203 #define VOW_ON_PERIODIC_INVERSE_MASK 0x1
1204 #define VOW_ON_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
1211 #define DMIC_ON_PERIODIC_MODE_MASK 0x1
1212 #define DMIC_ON_PERIODIC_MODE_MASK_SFT (0x1 << 15)
1214 #define DMIC_ON_PERIODIC_INVERSE_MASK 0x1
1215 #define DMIC_ON_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
1222 #define PDN_VOW_F32K_CK_MASK 0x1
1223 #define PDN_VOW_F32K_CK_MASK_SFT (0x1 << 15)
1230 #define VOW_SNRDET_PERIODIC_CFG_MASK 0x1
1231 #define VOW_SNRDET_PERIODIC_CFG_MASK_SFT (0x1 << 15)
1263 #define CLKSQ_EN_VOW_PERIODIC_MODE_MASK 0x1
1264 #define CLKSQ_EN_VOW_PERIODIC_MODE_MASK_SFT (0x1 << 15)
1334 #define RG_AUDPREAMPLON_MASK 0x1
1335 #define RG_AUDPREAMPLON_MASK_SFT (0x1 << 0)
1337 #define RG_AUDPREAMPLDCCEN_MASK 0x1
1338 #define RG_AUDPREAMPLDCCEN_MASK_SFT (0x1 << 1)
1340 #define RG_AUDPREAMPLDCPRECHARGE_MASK 0x1
1341 #define RG_AUDPREAMPLDCPRECHARGE_MASK_SFT (0x1 << 2)
1343 #define RG_AUDPREAMPLPGATEST_MASK 0x1
1344 #define RG_AUDPREAMPLPGATEST_MASK_SFT (0x1 << 3)
1355 #define RG_AUDADCLPWRUP_MASK 0x1
1356 #define RG_AUDADCLPWRUP_MASK_SFT (0x1 << 12)
1363 #define RG_AUDPREAMPRON_MASK 0x1
1364 #define RG_AUDPREAMPRON_MASK_SFT (0x1 << 0)
1366 #define RG_AUDPREAMPRDCCEN_MASK 0x1
1367 #define RG_AUDPREAMPRDCCEN_MASK_SFT (0x1 << 1)
1369 #define RG_AUDPREAMPRDCPRECHARGE_MASK 0x1
1370 #define RG_AUDPREAMPRDCPRECHARGE_MASK_SFT (0x1 << 2)
1372 #define RG_AUDPREAMPRPGATEST_MASK 0x1
1373 #define RG_AUDPREAMPRPGATEST_MASK_SFT (0x1 << 3)
1384 #define RG_AUDIO_VOW_EN_MASK 0x1
1385 #define RG_AUDIO_VOW_EN_MASK_SFT (0x1 << 11)
1387 #define RG_AUDADCRPWRUP_MASK 0x1
1388 #define RG_AUDADCRPWRUP_MASK_SFT (0x1 << 12)
1393 #define RG_CLKSQ_EN_VOW_MASK 0x1
1394 #define RG_CLKSQ_EN_VOW_MASK_SFT (0x1 << 15)
1398 #define RG_AUDULHALFBIAS_MASK 0x1
1399 #define RG_AUDULHALFBIAS_MASK_SFT (0x1 << 0)
1401 #define RG_AUDGLBVOWLPWEN_MASK 0x1
1402 #define RG_AUDGLBVOWLPWEN_MASK_SFT (0x1 << 1)
1404 #define RG_AUDPREAMPLPEN_MASK 0x1
1405 #define RG_AUDPREAMPLPEN_MASK_SFT (0x1 << 2)
1407 #define RG_AUDADC1STSTAGELPEN_MASK 0x1
1408 #define RG_AUDADC1STSTAGELPEN_MASK_SFT (0x1 << 3)
1410 #define RG_AUDADC2NDSTAGELPEN_MASK 0x1
1411 #define RG_AUDADC2NDSTAGELPEN_MASK_SFT (0x1 << 4)
1413 #define RG_AUDADCFLASHLPEN_MASK 0x1
1414 #define RG_AUDADCFLASHLPEN_MASK_SFT (0x1 << 5)
1433 #define RG_AUDADCDAC0P25FS_MASK 0x1
1434 #define RG_AUDADCDAC0P25FS_MASK_SFT (0x1 << 0)
1436 #define RG_AUDADCCLKSEL_MASK 0x1
1437 #define RG_AUDADCCLKSEL_MASK_SFT (0x1 << 1)
1442 #define RG_AUDPREAMPAAFEN_MASK 0x1
1443 #define RG_AUDPREAMPAAFEN_MASK_SFT (0x1 << 8)
1445 #define RG_DCCVCMBUFLPMODSEL_MASK 0x1
1446 #define RG_DCCVCMBUFLPMODSEL_MASK_SFT (0x1 << 9)
1448 #define RG_DCCVCMBUFLPSWEN_MASK 0x1
1449 #define RG_DCCVCMBUFLPSWEN_MASK_SFT (0x1 << 10)
1451 #define RG_CMSTBENH_MASK 0x1
1452 #define RG_CMSTBENH_MASK_SFT (0x1 << 11)
1454 #define RG_PGABODYSW_MASK 0x1
1455 #define RG_PGABODYSW_MASK_SFT (0x1 << 12)
1459 #define RG_AUDADC1STSTAGESDENB_MASK 0x1
1460 #define RG_AUDADC1STSTAGESDENB_MASK_SFT (0x1 << 0)
1462 #define RG_AUDADC2NDSTAGERESET_MASK 0x1
1463 #define RG_AUDADC2NDSTAGERESET_MASK_SFT (0x1 << 1)
1465 #define RG_AUDADC3RDSTAGERESET_MASK 0x1
1466 #define RG_AUDADC3RDSTAGERESET_MASK_SFT (0x1 << 2)
1468 #define RG_AUDADCFSRESET_MASK 0x1
1469 #define RG_AUDADCFSRESET_MASK_SFT (0x1 << 3)
1471 #define RG_AUDADCWIDECM_MASK 0x1
1472 #define RG_AUDADCWIDECM_MASK_SFT (0x1 << 4)
1474 #define RG_AUDADCNOPATEST_MASK 0x1
1475 #define RG_AUDADCNOPATEST_MASK_SFT (0x1 << 5)
1477 #define RG_AUDADCBYPASS_MASK 0x1
1478 #define RG_AUDADCBYPASS_MASK_SFT (0x1 << 6)
1480 #define RG_AUDADCFFBYPASS_MASK 0x1
1481 #define RG_AUDADCFFBYPASS_MASK_SFT (0x1 << 7)
1483 #define RG_AUDADCDACFBCURRENT_MASK 0x1
1484 #define RG_AUDADCDACFBCURRENT_MASK_SFT (0x1 << 8)
1489 #define RG_AUDADCDACNRZ_MASK 0x1
1490 #define RG_AUDADCDACNRZ_MASK_SFT (0x1 << 11)
1492 #define RG_AUDADCNODEM_MASK 0x1
1493 #define RG_AUDADCNODEM_MASK_SFT (0x1 << 12)
1495 #define RG_AUDADCDACTEST_MASK 0x1
1496 #define RG_AUDADCDACTEST_MASK_SFT (0x1 << 13)
1503 #define RG_AUDRCTUNELSEL_MASK 0x1
1504 #define RG_AUDRCTUNELSEL_MASK_SFT (0x1 << 5)
1509 #define RG_AUDRCTUNERSEL_MASK 0x1
1510 #define RG_AUDRCTUNERSEL_MASK_SFT (0x1 << 13)
1514 #define RG_CLKSQ_EN_MASK 0x1
1515 #define RG_CLKSQ_EN_MASK_SFT (0x1 << 0)
1517 #define RG_CLKSQ_IN_SEL_TEST_MASK 0x1
1518 #define RG_CLKSQ_IN_SEL_TEST_MASK_SFT (0x1 << 1)
1520 #define RG_CM_REFGENSEL_MASK 0x1
1521 #define RG_CM_REFGENSEL_MASK_SFT (0x1 << 2)
1536 #define RG_AUDDIGMICEN_MASK 0x1
1537 #define RG_AUDDIGMICEN_MASK_SFT (0x1 << 0)
1542 #define RG_DMICHPCLKEN_MASK 0x1
1543 #define RG_DMICHPCLKEN_MASK_SFT (0x1 << 3)
1551 #define RG_DMICMONEN_MASK 0x1
1552 #define RG_DMICMONEN_MASK_SFT (0x1 << 8)
1562 #define RG_AUDPWDBMICBIAS0_MASK 0x1
1563 #define RG_AUDPWDBMICBIAS0_MASK_SFT (0x1 << 0)
1565 #define RG_AUDMICBIAS0BYPASSEN_MASK 0x1
1566 #define RG_AUDMICBIAS0BYPASSEN_MASK_SFT (0x1 << 1)
1568 #define RG_AUDMICBIAS0LOWPEN_MASK 0x1
1569 #define RG_AUDMICBIAS0LOWPEN_MASK_SFT (0x1 << 2)
1574 #define RG_AUDMICBIAS0DCSW0P1EN_MASK 0x1
1575 #define RG_AUDMICBIAS0DCSW0P1EN_MASK_SFT (0x1 << 8)
1577 #define RG_AUDMICBIAS0DCSW0P2EN_MASK 0x1
1578 #define RG_AUDMICBIAS0DCSW0P2EN_MASK_SFT (0x1 << 9)
1580 #define RG_AUDMICBIAS0DCSW0NEN_MASK 0x1
1581 #define RG_AUDMICBIAS0DCSW0NEN_MASK_SFT (0x1 << 10)
1583 #define RG_AUDMICBIAS0DCSW2P1EN_MASK 0x1
1584 #define RG_AUDMICBIAS0DCSW2P1EN_MASK_SFT (0x1 << 12)
1586 #define RG_AUDMICBIAS0DCSW2P2EN_MASK 0x1
1587 #define RG_AUDMICBIAS0DCSW2P2EN_MASK_SFT (0x1 << 13)
1589 #define RG_AUDMICBIAS0DCSW2NEN_MASK 0x1
1590 #define RG_AUDMICBIAS0DCSW2NEN_MASK_SFT (0x1 << 14)
1594 #define RG_AUDPWDBMICBIAS1_MASK 0x1
1595 #define RG_AUDPWDBMICBIAS1_MASK_SFT (0x1 << 0)
1597 #define RG_AUDMICBIAS1BYPASSEN_MASK 0x1
1598 #define RG_AUDMICBIAS1BYPASSEN_MASK_SFT (0x1 << 1)
1600 #define RG_AUDMICBIAS1LOWPEN_MASK 0x1
1601 #define RG_AUDMICBIAS1LOWPEN_MASK_SFT (0x1 << 2)
1606 #define RG_AUDMICBIAS1DCSW1PEN_MASK 0x1
1607 #define RG_AUDMICBIAS1DCSW1PEN_MASK_SFT (0x1 << 8)
1609 #define RG_AUDMICBIAS1DCSW1NEN_MASK 0x1
1610 #define RG_AUDMICBIAS1DCSW1NEN_MASK_SFT (0x1 << 9)
1612 #define RG_BANDGAPGEN_MASK 0x1
1613 #define RG_BANDGAPGEN_MASK_SFT (0x1 << 12)
1615 #define RG_MTEST_EN_MASK 0x1
1616 #define RG_MTEST_EN_MASK_SFT (0x1 << 13)
1618 #define RG_MTEST_SEL_MASK 0x1
1619 #define RG_MTEST_SEL_MASK_SFT (0x1 << 14)
1621 #define RG_MTEST_CURRENT_MASK 0x1
1622 #define RG_MTEST_CURRENT_MASK_SFT (0x1 << 15)
1626 #define RG_AUDACCDETMICBIAS0PULLLOW_MASK 0x1
1627 #define RG_AUDACCDETMICBIAS0PULLLOW_MASK_SFT (0x1 << 0)
1629 #define RG_AUDACCDETMICBIAS1PULLLOW_MASK 0x1
1630 #define RG_AUDACCDETMICBIAS1PULLLOW_MASK_SFT (0x1 << 1)
1632 #define RG_AUDACCDETVIN1PULLLOW_MASK 0x1
1633 #define RG_AUDACCDETVIN1PULLLOW_MASK_SFT (0x1 << 2)
1635 #define RG_AUDACCDETVTHACAL_MASK 0x1
1636 #define RG_AUDACCDETVTHACAL_MASK_SFT (0x1 << 4)
1638 #define RG_AUDACCDETVTHBCAL_MASK 0x1
1639 #define RG_AUDACCDETVTHBCAL_MASK_SFT (0x1 << 5)
1641 #define RG_AUDACCDETTVDET_MASK 0x1
1642 #define RG_AUDACCDETTVDET_MASK_SFT (0x1 << 6)
1644 #define RG_ACCDETSEL_MASK 0x1
1645 #define RG_ACCDETSEL_MASK_SFT (0x1 << 7)
1647 #define RG_SWBUFMODSEL_MASK 0x1
1648 #define RG_SWBUFMODSEL_MASK_SFT (0x1 << 8)
1650 #define RG_SWBUFSWEN_MASK 0x1
1651 #define RG_SWBUFSWEN_MASK_SFT (0x1 << 9)
1653 #define RG_EINTCOMPVTH_MASK 0x1
1654 #define RG_EINTCOMPVTH_MASK_SFT (0x1 << 10)
1656 #define RG_EINTCONFIGACCDET_MASK 0x1
1657 #define RG_EINTCONFIGACCDET_MASK_SFT (0x1 << 11)
1659 #define RG_EINTHIRENB_MASK 0x1
1660 #define RG_EINTHIRENB_MASK_SFT (0x1 << 12)
1662 #define RG_ACCDET2AUXRESBYPASS_MASK 0x1
1663 #define RG_ACCDET2AUXRESBYPASS_MASK_SFT (0x1 << 13)
1665 #define RG_ACCDET2AUXBUFFERBYPASS_MASK 0x1
1666 #define RG_ACCDET2AUXBUFFERBYPASS_MASK_SFT (0x1 << 14)
1668 #define RG_ACCDET2AUXSWEN_MASK 0x1
1669 #define RG_ACCDET2AUXSWEN_MASK_SFT (0x1 << 15)
1719 #define RG_AUDDACLPWRUP_VAUDP15_MASK 0x1
1720 #define RG_AUDDACLPWRUP_VAUDP15_MASK_SFT (0x1 << 0)
1722 #define RG_AUDDACRPWRUP_VAUDP15_MASK 0x1
1723 #define RG_AUDDACRPWRUP_VAUDP15_MASK_SFT (0x1 << 1)
1725 #define RG_AUD_DAC_PWR_UP_VA28_MASK 0x1
1726 #define RG_AUD_DAC_PWR_UP_VA28_MASK_SFT (0x1 << 2)
1728 #define RG_AUD_DAC_PWL_UP_VA28_MASK 0x1
1729 #define RG_AUD_DAC_PWL_UP_VA28_MASK_SFT (0x1 << 3)
1731 #define RG_AUDHPLPWRUP_VAUDP15_MASK 0x1
1732 #define RG_AUDHPLPWRUP_VAUDP15_MASK_SFT (0x1 << 4)
1734 #define RG_AUDHPRPWRUP_VAUDP15_MASK 0x1
1735 #define RG_AUDHPRPWRUP_VAUDP15_MASK_SFT (0x1 << 5)
1737 #define RG_AUDHPLPWRUP_IBIAS_VAUDP15_MASK 0x1
1738 #define RG_AUDHPLPWRUP_IBIAS_VAUDP15_MASK_SFT (0x1 << 6)
1740 #define RG_AUDHPRPWRUP_IBIAS_VAUDP15_MASK 0x1
1741 #define RG_AUDHPRPWRUP_IBIAS_VAUDP15_MASK_SFT (0x1 << 7)
1749 #define RG_AUDHPLSCDISABLE_VAUDP15_MASK 0x1
1750 #define RG_AUDHPLSCDISABLE_VAUDP15_MASK_SFT (0x1 << 12)
1752 #define RG_AUDHPRSCDISABLE_VAUDP15_MASK 0x1
1753 #define RG_AUDHPRSCDISABLE_VAUDP15_MASK_SFT (0x1 << 13)
1755 #define RG_AUDHPLBSCCURRENT_VAUDP15_MASK 0x1
1756 #define RG_AUDHPLBSCCURRENT_VAUDP15_MASK_SFT (0x1 << 14)
1758 #define RG_AUDHPRBSCCURRENT_VAUDP15_MASK 0x1
1759 #define RG_AUDHPRBSCCURRENT_VAUDP15_MASK_SFT (0x1 << 15)
1763 #define RG_AUDHPLOUTPWRUP_VAUDP15_MASK 0x1
1764 #define RG_AUDHPLOUTPWRUP_VAUDP15_MASK_SFT (0x1 << 0)
1766 #define RG_AUDHPROUTPWRUP_VAUDP15_MASK 0x1
1767 #define RG_AUDHPROUTPWRUP_VAUDP15_MASK_SFT (0x1 << 1)
1769 #define RG_AUDHPLOUTAUXPWRUP_VAUDP15_MASK 0x1
1770 #define RG_AUDHPLOUTAUXPWRUP_VAUDP15_MASK_SFT (0x1 << 2)
1772 #define RG_AUDHPROUTAUXPWRUP_VAUDP15_MASK 0x1
1773 #define RG_AUDHPROUTAUXPWRUP_VAUDP15_MASK_SFT (0x1 << 3)
1775 #define RG_HPLAUXFBRSW_EN_VAUDP15_MASK 0x1
1776 #define RG_HPLAUXFBRSW_EN_VAUDP15_MASK_SFT (0x1 << 4)
1778 #define RG_HPRAUXFBRSW_EN_VAUDP15_MASK 0x1
1779 #define RG_HPRAUXFBRSW_EN_VAUDP15_MASK_SFT (0x1 << 5)
1781 #define RG_HPLSHORT2HPLAUX_EN_VAUDP15_MASK 0x1
1782 #define RG_HPLSHORT2HPLAUX_EN_VAUDP15_MASK_SFT (0x1 << 6)
1784 #define RG_HPRSHORT2HPRAUX_EN_VAUDP15_MASK 0x1
1785 #define RG_HPRSHORT2HPRAUX_EN_VAUDP15_MASK_SFT (0x1 << 7)
1801 #define RG_AUDHPSTARTUP_VAUDP15_MASK 0x1
1802 #define RG_AUDHPSTARTUP_VAUDP15_MASK_SFT (0x1 << 13)
1804 #define RG_AUDREFN_DERES_EN_VAUDP15_MASK 0x1
1805 #define RG_AUDREFN_DERES_EN_VAUDP15_MASK_SFT (0x1 << 14)
1807 #define RG_HPPSHORT2VCM_VAUDP15_MASK 0x1
1808 #define RG_HPPSHORT2VCM_VAUDP15_MASK_SFT (0x1 << 15)
1812 #define RG_HPINPUTSTBENH_VAUDP15_MASK 0x1
1813 #define RG_HPINPUTSTBENH_VAUDP15_MASK_SFT (0x1 << 13)
1815 #define RG_HPINPUTRESET0_VAUDP15_MASK 0x1
1816 #define RG_HPINPUTRESET0_VAUDP15_MASK_SFT (0x1 << 14)
1818 #define RG_HPOUTPUTRESET0_VAUDP15_MASK 0x1
1819 #define RG_HPOUTPUTRESET0_VAUDP15_MASK_SFT (0x1 << 15)
1836 #define RG_AUDHSPWRUP_VAUDP15_MASK 0x1
1837 #define RG_AUDHSPWRUP_VAUDP15_MASK_SFT (0x1 << 0)
1839 #define RG_AUDHSPWRUP_IBIAS_VAUDP15_MASK 0x1
1840 #define RG_AUDHSPWRUP_IBIAS_VAUDP15_MASK_SFT (0x1 << 1)
1845 #define RG_AUDHSSCDISABLE_VAUDP15_MASK 0x1
1846 #define RG_AUDHSSCDISABLE_VAUDP15_MASK_SFT (0x1 << 4)
1848 #define RG_AUDHSBSCCURRENT_VAUDP15_MASK 0x1
1849 #define RG_AUDHSBSCCURRENT_VAUDP15_MASK_SFT (0x1 << 5)
1851 #define RG_AUDHSSTARTUP_VAUDP15_MASK 0x1
1852 #define RG_AUDHSSTARTUP_VAUDP15_MASK_SFT (0x1 << 6)
1854 #define RG_HSOUTPUTSTBENH_VAUDP15_MASK 0x1
1855 #define RG_HSOUTPUTSTBENH_VAUDP15_MASK_SFT (0x1 << 7)
1857 #define RG_HSINPUTSTBENH_VAUDP15_MASK 0x1
1858 #define RG_HSINPUTSTBENH_VAUDP15_MASK_SFT (0x1 << 8)
1860 #define RG_HSINPUTRESET0_VAUDP15_MASK 0x1
1861 #define RG_HSINPUTRESET0_VAUDP15_MASK_SFT (0x1 << 9)
1863 #define RG_HSOUTPUTRESET0_VAUDP15_MASK 0x1
1864 #define RG_HSOUTPUTRESET0_VAUDP15_MASK_SFT (0x1 << 10)
1866 #define RG_HSOUT_SHORTVCM_VAUDP15_MASK 0x1
1867 #define RG_HSOUT_SHORTVCM_VAUDP15_MASK_SFT (0x1 << 11)
1871 #define RG_AUDLOLPWRUP_VAUDP15_MASK 0x1
1872 #define RG_AUDLOLPWRUP_VAUDP15_MASK_SFT (0x1 << 0)
1874 #define RG_AUDLOLPWRUP_IBIAS_VAUDP15_MASK 0x1
1875 #define RG_AUDLOLPWRUP_IBIAS_VAUDP15_MASK_SFT (0x1 << 1)
1880 #define RG_AUDLOLSCDISABLE_VAUDP15_MASK 0x1
1881 #define RG_AUDLOLSCDISABLE_VAUDP15_MASK_SFT (0x1 << 4)
1883 #define RG_AUDLOLBSCCURRENT_VAUDP15_MASK 0x1
1884 #define RG_AUDLOLBSCCURRENT_VAUDP15_MASK_SFT (0x1 << 5)
1886 #define RG_AUDLOSTARTUP_VAUDP15_MASK 0x1
1887 #define RG_AUDLOSTARTUP_VAUDP15_MASK_SFT (0x1 << 6)
1889 #define RG_LOINPUTSTBENH_VAUDP15_MASK 0x1
1890 #define RG_LOINPUTSTBENH_VAUDP15_MASK_SFT (0x1 << 7)
1892 #define RG_LOOUTPUTSTBENH_VAUDP15_MASK 0x1
1893 #define RG_LOOUTPUTSTBENH_VAUDP15_MASK_SFT (0x1 << 8)
1895 #define RG_LOINPUTRESET0_VAUDP15_MASK 0x1
1896 #define RG_LOINPUTRESET0_VAUDP15_MASK_SFT (0x1 << 9)
1898 #define RG_LOOUTPUTRESET0_VAUDP15_MASK 0x1
1899 #define RG_LOOUTPUTRESET0_VAUDP15_MASK_SFT (0x1 << 10)
1901 #define RG_LOOUT_SHORTVCM_VAUDP15_MASK 0x1
1902 #define RG_LOOUT_SHORTVCM_VAUDP15_MASK_SFT (0x1 << 11)
1912 #define RG_AUDTRIMBUF_EN_VAUDP15_MASK 0x1
1913 #define RG_AUDTRIMBUF_EN_VAUDP15_MASK_SFT (0x1 << 6)
1921 #define RG_AUDHPSPKDET_EN_VAUDP15_MASK 0x1
1922 #define RG_AUDHPSPKDET_EN_VAUDP15_MASK_SFT (0x1 << 12)
1945 #define RG_AUDZCDCLKSEL_VAUDP15_MASK 0x1
1946 #define RG_AUDZCDCLKSEL_VAUDP15_MASK_SFT (0x1 << 3)
1956 #define RG_AUDIBIASPWRDN_VAUDP15_MASK 0x1
1957 #define RG_AUDIBIASPWRDN_VAUDP15_MASK_SFT (0x1 << 8)
1961 #define RG_RSTB_DECODER_VA28_MASK 0x1
1962 #define RG_RSTB_DECODER_VA28_MASK_SFT (0x1 << 0)
1964 #define RG_SEL_DECODER_96K_VA28_MASK 0x1
1965 #define RG_SEL_DECODER_96K_VA28_MASK_SFT (0x1 << 1)
1967 #define RG_SEL_DELAY_VCORE_MASK 0x1
1968 #define RG_SEL_DELAY_VCORE_MASK_SFT (0x1 << 2)
1970 #define RG_AUDGLB_PWRDN_VA28_MASK 0x1
1971 #define RG_AUDGLB_PWRDN_VA28_MASK_SFT (0x1 << 4)
1973 #define RG_RSTB_ENCODER_VA28_MASK 0x1
1974 #define RG_RSTB_ENCODER_VA28_MASK_SFT (0x1 << 5)
1976 #define RG_SEL_ENCODER_96K_VA28_MASK 0x1
1977 #define RG_SEL_ENCODER_96K_VA28_MASK_SFT (0x1 << 6)
1981 #define RG_HCLDO_EN_VA18_MASK 0x1
1982 #define RG_HCLDO_EN_VA18_MASK_SFT (0x1 << 0)
1984 #define RG_HCLDO_PDDIS_EN_VA18_MASK 0x1
1985 #define RG_HCLDO_PDDIS_EN_VA18_MASK_SFT (0x1 << 1)
1987 #define RG_HCLDO_REMOTE_SENSE_VA18_MASK 0x1
1988 #define RG_HCLDO_REMOTE_SENSE_VA18_MASK_SFT (0x1 << 2)
1990 #define RG_LCLDO_EN_VA18_MASK 0x1
1991 #define RG_LCLDO_EN_VA18_MASK_SFT (0x1 << 4)
1993 #define RG_LCLDO_PDDIS_EN_VA18_MASK 0x1
1994 #define RG_LCLDO_PDDIS_EN_VA18_MASK_SFT (0x1 << 5)
1996 #define RG_LCLDO_REMOTE_SENSE_VA18_MASK 0x1
1997 #define RG_LCLDO_REMOTE_SENSE_VA18_MASK_SFT (0x1 << 6)
1999 #define RG_LCLDO_ENC_EN_VA28_MASK 0x1
2000 #define RG_LCLDO_ENC_EN_VA28_MASK_SFT (0x1 << 8)
2002 #define RG_LCLDO_ENC_PDDIS_EN_VA28_MASK 0x1
2003 #define RG_LCLDO_ENC_PDDIS_EN_VA28_MASK_SFT (0x1 << 9)
2005 #define RG_LCLDO_ENC_REMOTE_SENSE_VA28_MASK 0x1
2006 #define RG_LCLDO_ENC_REMOTE_SENSE_VA28_MASK_SFT (0x1 << 10)
2008 #define RG_VA33REFGEN_EN_VA18_MASK 0x1
2009 #define RG_VA33REFGEN_EN_VA18_MASK_SFT (0x1 << 12)
2011 #define RG_VA28REFGEN_EN_VA28_MASK 0x1
2012 #define RG_VA28REFGEN_EN_VA28_MASK_SFT (0x1 << 13)
2014 #define RG_HCLDO_VOSEL_VA18_MASK 0x1
2015 #define RG_HCLDO_VOSEL_VA18_MASK_SFT (0x1 << 14)
2017 #define RG_LCLDO_VOSEL_VA18_MASK 0x1
2018 #define RG_LCLDO_VOSEL_VA18_MASK_SFT (0x1 << 15)
2022 #define RG_NVREG_EN_VAUDP15_MASK 0x1
2023 #define RG_NVREG_EN_VAUDP15_MASK_SFT (0x1 << 0)
2025 #define RG_NVREG_PULL0V_VAUDP15_MASK 0x1
2026 #define RG_NVREG_PULL0V_VAUDP15_MASK_SFT (0x1 << 1)
2039 #define RG_AUDZCDENABLE_MASK 0x1
2040 #define RG_AUDZCDENABLE_MASK_SFT (0x1 << 0)
2048 #define RG_AUDZCDTIMEOUTMODESEL_MASK 0x1
2049 #define RG_AUDZCDTIMEOUTMODESEL_MASK_SFT (0x1 << 6)