Lines Matching +full:dc +full:- +full:dc +full:- +full:freq +full:- +full:hz
1 // SPDX-License-Identifier: GPL-2.0-only
3 * cs43130.c -- CS43130 ALSA Soc Audio driver
26 #include <sound/soc-dapm.h>
242 dev_dbg(component->dev, "cs43130->mclk = %u, cs43130->mclk_int = %u\n", in cs43130_pll_config()
243 cs43130->mclk, cs43130->mclk_int); in cs43130_pll_config()
245 pll_entry = cs43130_get_pll_table(cs43130->mclk, cs43130->mclk_int); in cs43130_pll_config()
247 return -EINVAL; in cs43130_pll_config()
249 if (pll_entry->pll_cal_ratio == 0) { in cs43130_pll_config()
250 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_1, in cs43130_pll_config()
253 cs43130->pll_bypass = true; in cs43130_pll_config()
257 cs43130->pll_bypass = false; in cs43130_pll_config()
259 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_2, in cs43130_pll_config()
261 pll_entry->pll_div_frac >> in cs43130_pll_config()
263 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_3, in cs43130_pll_config()
265 pll_entry->pll_div_frac >> in cs43130_pll_config()
267 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_4, in cs43130_pll_config()
269 pll_entry->pll_div_frac >> in cs43130_pll_config()
271 regmap_write(cs43130->regmap, CS43130_PLL_SET_5, in cs43130_pll_config()
272 pll_entry->pll_div_int); in cs43130_pll_config()
273 regmap_write(cs43130->regmap, CS43130_PLL_SET_6, pll_entry->pll_divout); in cs43130_pll_config()
274 regmap_write(cs43130->regmap, CS43130_PLL_SET_7, in cs43130_pll_config()
275 pll_entry->pll_cal_ratio); in cs43130_pll_config()
276 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_8, in cs43130_pll_config()
278 pll_entry->pll_mode << CS43130_PLL_MODE_SHIFT); in cs43130_pll_config()
279 regmap_write(cs43130->regmap, CS43130_PLL_SET_9, in cs43130_pll_config()
280 pll_entry->sclk_prediv); in cs43130_pll_config()
281 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_1, in cs43130_pll_config()
304 cs43130->mclk = freq_in; in cs43130_set_pll()
307 dev_err(component->dev, in cs43130_set_pll()
309 return -EINVAL; in cs43130_set_pll()
314 cs43130->mclk_int = freq_out; in cs43130_set_pll()
317 cs43130->mclk_int = freq_out; in cs43130_set_pll()
320 dev_err(component->dev, in cs43130_set_pll()
322 return -EINVAL; in cs43130_set_pll()
326 dev_dbg(component->dev, "cs43130->pll_bypass = %d", cs43130->pll_bypass); in cs43130_set_pll()
337 if (src == cs43130->mclk_int_src) { in cs43130_change_clksrc()
342 switch (cs43130->mclk_int) { in cs43130_change_clksrc()
350 dev_err(component->dev, "Invalid MCLK INT freq: %u\n", cs43130->mclk_int); in cs43130_change_clksrc()
351 return -EINVAL; in cs43130_change_clksrc()
356 cs43130->pll_bypass = true; in cs43130_change_clksrc()
357 cs43130->mclk_int_src = CS43130_MCLK_SRC_EXT; in cs43130_change_clksrc()
358 if (cs43130->xtal_ibias == CS43130_XTAL_UNUSED) { in cs43130_change_clksrc()
359 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, in cs43130_change_clksrc()
363 reinit_completion(&cs43130->xtal_rdy); in cs43130_change_clksrc()
364 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, in cs43130_change_clksrc()
366 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, in cs43130_change_clksrc()
368 ret = wait_for_completion_timeout(&cs43130->xtal_rdy, in cs43130_change_clksrc()
370 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, in cs43130_change_clksrc()
374 dev_err(component->dev, "Timeout waiting for XTAL_READY interrupt\n"); in cs43130_change_clksrc()
375 return -ETIMEDOUT; in cs43130_change_clksrc()
379 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1, in cs43130_change_clksrc()
382 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1, in cs43130_change_clksrc()
387 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, in cs43130_change_clksrc()
392 cs43130->pll_bypass = false; in cs43130_change_clksrc()
393 cs43130->mclk_int_src = CS43130_MCLK_SRC_PLL; in cs43130_change_clksrc()
394 if (cs43130->xtal_ibias == CS43130_XTAL_UNUSED) { in cs43130_change_clksrc()
395 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, in cs43130_change_clksrc()
399 reinit_completion(&cs43130->xtal_rdy); in cs43130_change_clksrc()
400 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, in cs43130_change_clksrc()
402 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, in cs43130_change_clksrc()
404 ret = wait_for_completion_timeout(&cs43130->xtal_rdy, in cs43130_change_clksrc()
406 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, in cs43130_change_clksrc()
410 dev_err(component->dev, "Timeout waiting for XTAL_READY interrupt\n"); in cs43130_change_clksrc()
411 return -ETIMEDOUT; in cs43130_change_clksrc()
415 reinit_completion(&cs43130->pll_rdy); in cs43130_change_clksrc()
416 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, in cs43130_change_clksrc()
418 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, in cs43130_change_clksrc()
420 ret = wait_for_completion_timeout(&cs43130->pll_rdy, in cs43130_change_clksrc()
422 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, in cs43130_change_clksrc()
426 dev_err(component->dev, "Timeout waiting for PLL_READY interrupt\n"); in cs43130_change_clksrc()
427 return -ETIMEDOUT; in cs43130_change_clksrc()
430 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1, in cs43130_change_clksrc()
433 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1, in cs43130_change_clksrc()
439 cs43130->mclk_int_src = CS43130_MCLK_SRC_RCO; in cs43130_change_clksrc()
441 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1, in cs43130_change_clksrc()
444 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1, in cs43130_change_clksrc()
449 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, in cs43130_change_clksrc()
452 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, in cs43130_change_clksrc()
457 dev_err(component->dev, "Invalid MCLK source value\n"); in cs43130_change_clksrc()
458 return -EINVAL; in cs43130_change_clksrc()
491 return -EINVAL; in cs43130_set_bitwidth()
497 CS43130_CH_BITSIZE_MASK, bw_map->ch_bit); in cs43130_set_bitwidth()
499 CS43130_CH_BITSIZE_MASK, bw_map->ch_bit); in cs43130_set_bitwidth()
501 CS43130_ASP_BITSIZE_MASK, bw_map->sp_bit); in cs43130_set_bitwidth()
505 CS43130_CH_BITSIZE_MASK, bw_map->ch_bit); in cs43130_set_bitwidth()
507 CS43130_CH_BITSIZE_MASK, bw_map->ch_bit); in cs43130_set_bitwidth()
509 CS43130_XSP_BITSIZE_MASK, bw_map->sp_bit << in cs43130_set_bitwidth()
513 return -EINVAL; in cs43130_set_bitwidth()
574 switch (cs43130->dais[dai_id].dai_format) { in cs43130_set_sp_fmt()
596 return -EINVAL; in cs43130_set_sp_fmt()
599 switch (cs43130->dais[dai_id].dai_mode) { in cs43130_set_sp_fmt()
607 return -EINVAL; in cs43130_set_sp_fmt()
614 loc_ch2 = bitwidth_sclk * (params_channels(params) - 1); in cs43130_set_sp_fmt()
632 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_1, in cs43130_set_sp_fmt()
633 CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >> in cs43130_set_sp_fmt()
635 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_2, in cs43130_set_sp_fmt()
636 CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >> in cs43130_set_sp_fmt()
638 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_1, in cs43130_set_sp_fmt()
639 CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >> in cs43130_set_sp_fmt()
641 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_2, in cs43130_set_sp_fmt()
642 CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >> in cs43130_set_sp_fmt()
644 regmap_write(cs43130->regmap, CS43130_ASP_FRAME_CONF, frm_data); in cs43130_set_sp_fmt()
645 regmap_write(cs43130->regmap, CS43130_ASP_CH_1_LOC, loc_ch1); in cs43130_set_sp_fmt()
646 regmap_write(cs43130->regmap, CS43130_ASP_CH_2_LOC, loc_ch2); in cs43130_set_sp_fmt()
647 regmap_update_bits(cs43130->regmap, CS43130_ASP_CH_1_SZ_EN, in cs43130_set_sp_fmt()
649 regmap_update_bits(cs43130->regmap, CS43130_ASP_CH_2_SZ_EN, in cs43130_set_sp_fmt()
651 regmap_write(cs43130->regmap, CS43130_ASP_CLOCK_CONF, clk_data); in cs43130_set_sp_fmt()
654 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_PERIOD_1, in cs43130_set_sp_fmt()
655 CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >> in cs43130_set_sp_fmt()
657 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_PERIOD_2, in cs43130_set_sp_fmt()
658 CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >> in cs43130_set_sp_fmt()
660 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_HI_TIME_1, in cs43130_set_sp_fmt()
661 CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >> in cs43130_set_sp_fmt()
663 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_HI_TIME_2, in cs43130_set_sp_fmt()
664 CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >> in cs43130_set_sp_fmt()
666 regmap_write(cs43130->regmap, CS43130_XSP_FRAME_CONF, frm_data); in cs43130_set_sp_fmt()
667 regmap_write(cs43130->regmap, CS43130_XSP_CH_1_LOC, loc_ch1); in cs43130_set_sp_fmt()
668 regmap_write(cs43130->regmap, CS43130_XSP_CH_2_LOC, loc_ch2); in cs43130_set_sp_fmt()
669 regmap_update_bits(cs43130->regmap, CS43130_XSP_CH_1_SZ_EN, in cs43130_set_sp_fmt()
671 regmap_update_bits(cs43130->regmap, CS43130_XSP_CH_2_SZ_EN, in cs43130_set_sp_fmt()
673 regmap_write(cs43130->regmap, CS43130_XSP_CLOCK_CONF, clk_data); in cs43130_set_sp_fmt()
676 return -EINVAL; in cs43130_set_sp_fmt()
681 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int, in cs43130_set_sp_fmt()
687 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int, in cs43130_set_sp_fmt()
693 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int, in cs43130_set_sp_fmt()
699 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int, in cs43130_set_sp_fmt()
705 return -EINVAL; in cs43130_set_sp_fmt()
709 return -EINVAL; in cs43130_set_sp_fmt()
714 regmap_write(cs43130->regmap, CS43130_ASP_DEN_1, in cs43130_set_sp_fmt()
715 (clk_gen->v.denominator & CS43130_SP_M_LSB_DATA_MASK) >> in cs43130_set_sp_fmt()
717 regmap_write(cs43130->regmap, CS43130_ASP_DEN_2, in cs43130_set_sp_fmt()
718 (clk_gen->v.denominator & CS43130_SP_M_MSB_DATA_MASK) >> in cs43130_set_sp_fmt()
720 regmap_write(cs43130->regmap, CS43130_ASP_NUM_1, in cs43130_set_sp_fmt()
721 (clk_gen->v.numerator & CS43130_SP_N_LSB_DATA_MASK) >> in cs43130_set_sp_fmt()
723 regmap_write(cs43130->regmap, CS43130_ASP_NUM_2, in cs43130_set_sp_fmt()
724 (clk_gen->v.numerator & CS43130_SP_N_MSB_DATA_MASK) >> in cs43130_set_sp_fmt()
728 regmap_write(cs43130->regmap, CS43130_XSP_DEN_1, in cs43130_set_sp_fmt()
729 (clk_gen->v.denominator & CS43130_SP_M_LSB_DATA_MASK) >> in cs43130_set_sp_fmt()
731 regmap_write(cs43130->regmap, CS43130_XSP_DEN_2, in cs43130_set_sp_fmt()
732 (clk_gen->v.denominator & CS43130_SP_M_MSB_DATA_MASK) >> in cs43130_set_sp_fmt()
734 regmap_write(cs43130->regmap, CS43130_XSP_NUM_1, in cs43130_set_sp_fmt()
735 (clk_gen->v.numerator & CS43130_SP_N_LSB_DATA_MASK) >> in cs43130_set_sp_fmt()
737 regmap_write(cs43130->regmap, CS43130_XSP_NUM_2, in cs43130_set_sp_fmt()
738 (clk_gen->v.numerator & CS43130_SP_N_MSB_DATA_MASK) >> in cs43130_set_sp_fmt()
742 return -EINVAL; in cs43130_set_sp_fmt()
775 struct snd_soc_component *component = dai->component; in cs43130_dsd_hw_params()
780 mutex_lock(&cs43130->clk_mutex); in cs43130_dsd_hw_params()
781 if (!cs43130->clk_req) { in cs43130_dsd_hw_params()
788 cs43130_set_pll(component, 0, 0, cs43130->mclk, required_clk); in cs43130_dsd_hw_params()
789 if (cs43130->pll_bypass) in cs43130_dsd_hw_params()
795 cs43130->clk_req++; in cs43130_dsd_hw_params()
796 if (cs43130->clk_req == 2) in cs43130_dsd_hw_params()
797 cs43130_pcm_dsd_mix(true, cs43130->regmap); in cs43130_dsd_hw_params()
798 mutex_unlock(&cs43130->clk_mutex); in cs43130_dsd_hw_params()
808 dev_err(component->dev, "Rate(%u) not supported\n", in cs43130_dsd_hw_params()
810 return -EINVAL; in cs43130_dsd_hw_params()
813 if (cs43130->dais[dai->id].dai_mode == SND_SOC_DAIFMT_CBM_CFM) in cs43130_dsd_hw_params()
814 regmap_update_bits(cs43130->regmap, CS43130_DSD_INT_CFG, in cs43130_dsd_hw_params()
817 regmap_update_bits(cs43130->regmap, CS43130_DSD_INT_CFG, in cs43130_dsd_hw_params()
820 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2, in cs43130_dsd_hw_params()
823 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2, in cs43130_dsd_hw_params()
834 struct snd_soc_component *component = dai->component; in cs43130_hw_params()
837 unsigned int sclk = cs43130->dais[dai->id].sclk; in cs43130_hw_params()
843 mutex_lock(&cs43130->clk_mutex); in cs43130_hw_params()
844 if (!cs43130->clk_req) { in cs43130_hw_params()
851 cs43130_set_pll(component, 0, 0, cs43130->mclk, required_clk); in cs43130_hw_params()
852 if (cs43130->pll_bypass) in cs43130_hw_params()
858 cs43130->clk_req++; in cs43130_hw_params()
859 if (cs43130->clk_req == 2) in cs43130_hw_params()
860 cs43130_pcm_dsd_mix(true, cs43130->regmap); in cs43130_hw_params()
861 mutex_unlock(&cs43130->clk_mutex); in cs43130_hw_params()
863 switch (dai->id) { in cs43130_hw_params()
866 /* DoP bitwidth is always 24-bit */ in cs43130_hw_params()
879 dev_err(component->dev, "Rate(%u) not supported\n", in cs43130_hw_params()
881 return -EINVAL; in cs43130_hw_params()
884 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2, in cs43130_hw_params()
891 return -EINVAL; in cs43130_hw_params()
893 regmap_write(cs43130->regmap, CS43130_SP_SRATE, rate_map->val); in cs43130_hw_params()
896 dev_err(component->dev, "Invalid DAI (%d)\n", dai->id); in cs43130_hw_params()
897 return -EINVAL; in cs43130_hw_params()
900 switch (dai->id) { in cs43130_hw_params()
902 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2, in cs43130_hw_params()
907 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2, in cs43130_hw_params()
913 if (!sclk && cs43130->dais[dai->id].dai_mode == SND_SOC_DAIFMT_CBM_CFM) in cs43130_hw_params()
920 dev_err(component->dev, "SCLK freq is not set\n"); in cs43130_hw_params()
921 return -EINVAL; in cs43130_hw_params()
926 dev_err(component->dev, "Format not supported: SCLK freq is too low\n"); in cs43130_hw_params()
927 return -EINVAL; in cs43130_hw_params()
930 dev_dbg(component->dev, in cs43130_hw_params()
934 dev_dbg(component->dev, in cs43130_hw_params()
938 cs43130_set_bitwidth(dai->id, bitwidth_dai, cs43130->regmap); in cs43130_hw_params()
939 cs43130_set_sp_fmt(dai->id, bitwidth_sclk, params, cs43130); in cs43130_hw_params()
947 struct snd_soc_component *component = dai->component; in cs43130_hw_free()
950 mutex_lock(&cs43130->clk_mutex); in cs43130_hw_free()
951 cs43130->clk_req--; in cs43130_hw_free()
952 if (!cs43130->clk_req) { in cs43130_hw_free()
955 cs43130_pcm_dsd_mix(false, cs43130->regmap); in cs43130_hw_free()
957 mutex_unlock(&cs43130->clk_mutex); in cs43130_hw_free()
962 static const DECLARE_TLV_DB_SCALE(pcm_vol_tlv, -12750, 50, 1);
965 "Left-Right Ch",
966 "Left-Left Ch",
967 "Right-Left Ch",
968 "Right-Right Ch",
1022 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in cs43130_pcm_ch_put()
1023 unsigned int *item = ucontrol->value.enumerated.item; in cs43130_pcm_ch_put()
1028 if (item[0] >= e->items) in cs43130_pcm_ch_put()
1029 return -EINVAL; in cs43130_pcm_ch_put()
1030 val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l; in cs43130_pcm_ch_put()
1032 switch (cs43130->dev_id) { in cs43130_pcm_ch_put()
1036 regmap_multi_reg_write(cs43130->regmap, pcm_ch_en_seq, in cs43130_pcm_ch_put()
1039 regmap_multi_reg_write(cs43130->regmap, pcm_ch_dis_seq, in cs43130_pcm_ch_put()
1085 SOC_SINGLE("PCM High-pass Filter", CS43130_PCM_FILT_OPT, 1, 1, 0),
1086 SOC_SINGLE("PCM De-emphasis Filter", CS43130_PCM_FILT_OPT, 0, 1, 0),
1145 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in cs43130_dsd_event()
1150 switch (cs43130->dev_id) { in cs43130_dsd_event()
1153 regmap_multi_reg_write(cs43130->regmap, dsd_seq, in cs43130_dsd_event()
1159 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_1, in cs43130_dsd_event()
1161 switch (cs43130->dev_id) { in cs43130_dsd_event()
1164 regmap_multi_reg_write(cs43130->regmap, unmute_seq, in cs43130_dsd_event()
1170 switch (cs43130->dev_id) { in cs43130_dsd_event()
1173 regmap_multi_reg_write(cs43130->regmap, mute_seq, in cs43130_dsd_event()
1175 regmap_update_bits(cs43130->regmap, in cs43130_dsd_event()
1186 regmap_update_bits(cs43130->regmap, in cs43130_dsd_event()
1193 dev_err(component->dev, "Invalid event = 0x%x\n", event); in cs43130_dsd_event()
1194 return -EINVAL; in cs43130_dsd_event()
1202 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in cs43130_pcm_event()
1207 switch (cs43130->dev_id) { in cs43130_pcm_event()
1210 regmap_multi_reg_write(cs43130->regmap, pcm_seq, in cs43130_pcm_event()
1216 regmap_update_bits(cs43130->regmap, CS43130_PCM_PATH_CTL_1, in cs43130_pcm_event()
1218 switch (cs43130->dev_id) { in cs43130_pcm_event()
1221 regmap_multi_reg_write(cs43130->regmap, unmute_seq, in cs43130_pcm_event()
1227 switch (cs43130->dev_id) { in cs43130_pcm_event()
1230 regmap_multi_reg_write(cs43130->regmap, mute_seq, in cs43130_pcm_event()
1232 regmap_update_bits(cs43130->regmap, in cs43130_pcm_event()
1243 regmap_update_bits(cs43130->regmap, in cs43130_pcm_event()
1250 dev_err(component->dev, "Invalid event = 0x%x\n", event); in cs43130_pcm_event()
1251 return -EINVAL; in cs43130_pcm_event()
1271 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in cs43130_dac_event()
1276 switch (cs43130->dev_id) { in cs43130_dac_event()
1279 regmap_multi_reg_write(cs43130->regmap, pop_free_seq, in cs43130_dac_event()
1284 regmap_multi_reg_write(cs43130->regmap, pop_free_seq2, in cs43130_dac_event()
1292 regmap_write(cs43130->regmap, CS43130_DXD1, 0x99); in cs43130_dac_event()
1294 switch (cs43130->dev_id) { in cs43130_dac_event()
1297 regmap_multi_reg_write(cs43130->regmap, dac_postpmu_seq, in cs43130_dac_event()
1300 * Per datasheet, Sec. PCM Power-Up Sequence. in cs43130_dac_event()
1305 regmap_write(cs43130->regmap, CS43130_DXD12, 0); in cs43130_dac_event()
1310 regmap_write(cs43130->regmap, CS43130_DXD13, 0); in cs43130_dac_event()
1314 regmap_write(cs43130->regmap, CS43130_DXD1, 0); in cs43130_dac_event()
1317 switch (cs43130->dev_id) { in cs43130_dac_event()
1320 regmap_multi_reg_write(cs43130->regmap, dac_postpmd_seq, in cs43130_dac_event()
1326 dev_err(component->dev, "Invalid DAC event = 0x%x\n", event); in cs43130_dac_event()
1327 return -EINVAL; in cs43130_dac_event()
1351 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in cs43130_hpin_event()
1356 regmap_multi_reg_write(cs43130->regmap, hpin_prepmd_seq, in cs43130_hpin_event()
1360 regmap_multi_reg_write(cs43130->regmap, hpin_postpmu_seq, in cs43130_hpin_event()
1364 dev_err(component->dev, "Invalid HPIN event = 0x%x\n", event); in cs43130_hpin_event()
1365 return -EINVAL; in cs43130_hpin_event()
1448 return snd_pcm_hw_constraint_list(substream->runtime, 0, in cs43130_pcm_startup()
1465 return snd_pcm_hw_constraint_list(substream->runtime, 0, in cs43130_dop_startup()
1472 struct snd_soc_component *component = codec_dai->component; in cs43130_pcm_set_fmt()
1477 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBS_CFS; in cs43130_pcm_set_fmt()
1480 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBM_CFM; in cs43130_pcm_set_fmt()
1483 dev_err(component->dev, "unsupported mode\n"); in cs43130_pcm_set_fmt()
1484 return -EINVAL; in cs43130_pcm_set_fmt()
1489 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_I2S; in cs43130_pcm_set_fmt()
1492 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_LEFT_J; in cs43130_pcm_set_fmt()
1495 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_DSP_A; in cs43130_pcm_set_fmt()
1498 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_DSP_B; in cs43130_pcm_set_fmt()
1501 dev_err(component->dev, in cs43130_pcm_set_fmt()
1503 return -EINVAL; in cs43130_pcm_set_fmt()
1506 dev_dbg(component->dev, "dai_id = %d, dai_mode = %u, dai_format = %u\n", in cs43130_pcm_set_fmt()
1507 codec_dai->id, in cs43130_pcm_set_fmt()
1508 cs43130->dais[codec_dai->id].dai_mode, in cs43130_pcm_set_fmt()
1509 cs43130->dais[codec_dai->id].dai_format); in cs43130_pcm_set_fmt()
1516 struct snd_soc_component *component = codec_dai->component; in cs43130_dsd_set_fmt()
1521 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBS_CFS; in cs43130_dsd_set_fmt()
1524 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBM_CFM; in cs43130_dsd_set_fmt()
1527 dev_err(component->dev, "Unsupported DAI format.\n"); in cs43130_dsd_set_fmt()
1528 return -EINVAL; in cs43130_dsd_set_fmt()
1531 dev_dbg(component->dev, "dai_mode = 0x%x\n", in cs43130_dsd_set_fmt()
1532 cs43130->dais[codec_dai->id].dai_mode); in cs43130_dsd_set_fmt()
1538 int clk_id, unsigned int freq, int dir) in cs43130_set_sysclk() argument
1540 struct snd_soc_component *component = codec_dai->component; in cs43130_set_sysclk()
1543 cs43130->dais[codec_dai->id].sclk = freq; in cs43130_set_sysclk()
1544 dev_dbg(component->dev, "dai_id = %d, sclk = %u\n", codec_dai->id, in cs43130_set_sysclk()
1545 cs43130->dais[codec_dai->id].sclk); in cs43130_set_sysclk()
1575 .name = "cs43130-asp-pcm",
1588 .name = "cs43130-asp-dop",
1601 .name = "cs43130-xsp-dop",
1614 .name = "cs43130-xsp-dsd",
1629 int clk_id, int source, unsigned int freq, in cs43130_component_set_sysclk() argument
1634 dev_dbg(component->dev, "clk_id = %d, source = %d, freq = %d, dir = %d\n", in cs43130_component_set_sysclk()
1635 clk_id, source, freq, dir); in cs43130_component_set_sysclk()
1637 switch (freq) { in cs43130_component_set_sysclk()
1640 cs43130->mclk = freq; in cs43130_component_set_sysclk()
1643 dev_err(component->dev, "Invalid MCLK INT freq: %u\n", freq); in cs43130_component_set_sysclk()
1644 return -EINVAL; in cs43130_component_set_sysclk()
1648 cs43130->pll_bypass = true; in cs43130_component_set_sysclk()
1650 dev_err(component->dev, "Invalid MCLK source\n"); in cs43130_component_set_sysclk()
1651 return -EINVAL; in cs43130_component_set_sysclk()
1659 /* AC freq is counted in 5.94Hz step. */ in cs43130_get_ac_reg_val()
1668 if (!cs43130->hpload_done) in cs43130_show_dc()
1671 return sysfs_emit(buf, "%u\n", cs43130->hpload_dc[ch]); in cs43130_show_dc()
1705 if (cs43130->hpload_done && cs43130->ac_meas) { in cs43130_show_ac()
1708 cs43130->hpload_ac[i][ch]); in cs43130_show_ac()
1937 struct snd_soc_component *component = cs43130->component; in cs43130_update_hpload()
1947 regmap_read(cs43130->regmap, CS43130_HP_LOAD_1, ®); in cs43130_update_hpload()
1956 regmap_read(cs43130->regmap, addr, ®); in cs43130_update_hpload()
1958 regmap_read(cs43130->regmap, addr + 1, ®); in cs43130_update_hpload()
1963 cs43130->hpload_dc[HP_LEFT] = impedance; in cs43130_update_hpload()
1965 cs43130->hpload_dc[HP_RIGHT] = impedance; in cs43130_update_hpload()
1967 dev_dbg(component->dev, "HP DC impedance (Ch %u): %u\n", !left_ch, in cs43130_update_hpload()
1971 cs43130->hpload_ac[ac_idx][HP_LEFT] = impedance; in cs43130_update_hpload()
1973 cs43130->hpload_ac[ac_idx][HP_RIGHT] = impedance; in cs43130_update_hpload()
1975 dev_dbg(component->dev, "HP AC (%u Hz) impedance (Ch %u): %u\n", in cs43130_update_hpload()
1976 cs43130->ac_freq[ac_idx], !left_ch, impedance); in cs43130_update_hpload()
1989 struct snd_soc_component *component = cs43130->component; in cs43130_hpload_proc()
1991 reinit_completion(&cs43130->hpload_evt); in cs43130_hpload_proc()
1994 ac_reg_val = cs43130_get_ac_reg_val(cs43130->ac_freq[ac_idx]); in cs43130_hpload_proc()
1995 regmap_update_bits(cs43130->regmap, CS43130_HP_LOAD_1, in cs43130_hpload_proc()
1997 regmap_update_bits(cs43130->regmap, CS43130_HP_MEAS_LOAD_1, in cs43130_hpload_proc()
2000 regmap_update_bits(cs43130->regmap, CS43130_HP_MEAS_LOAD_2, in cs43130_hpload_proc()
2005 regmap_multi_reg_write(cs43130->regmap, seq, in cs43130_hpload_proc()
2008 ret = wait_for_completion_timeout(&cs43130->hpload_evt, in cs43130_hpload_proc()
2010 regmap_read(cs43130->regmap, CS43130_INT_MASK_4, &msk); in cs43130_hpload_proc()
2012 dev_err(component->dev, "Timeout waiting for HPLOAD interrupt\n"); in cs43130_hpload_proc()
2013 return -1; in cs43130_hpload_proc()
2016 dev_dbg(component->dev, "HP load stat: %x, INT_MASK_4: %x\n", in cs43130_hpload_proc()
2017 cs43130->hpload_stat, msk); in cs43130_hpload_proc()
2018 if ((cs43130->hpload_stat & (CS43130_HPLOAD_NO_DC_INT | in cs43130_hpload_proc()
2021 !(cs43130->hpload_stat & rslt_msk)) { in cs43130_hpload_proc()
2022 dev_dbg(component->dev, "HP load measure failed\n"); in cs43130_hpload_proc()
2023 return -1; in cs43130_hpload_proc()
2068 component = cs43130->component; in cs43130_imp_meas()
2070 if (!cs43130->mclk) in cs43130_imp_meas()
2073 cs43130->hpload_done = false; in cs43130_imp_meas()
2075 mutex_lock(&cs43130->clk_mutex); in cs43130_imp_meas()
2076 if (!cs43130->clk_req) { in cs43130_imp_meas()
2078 cs43130_set_pll(component, 0, 0, cs43130->mclk, CS43130_MCLK_22M); in cs43130_imp_meas()
2079 if (cs43130->pll_bypass) in cs43130_imp_meas()
2085 cs43130->clk_req++; in cs43130_imp_meas()
2086 mutex_unlock(&cs43130->clk_mutex); in cs43130_imp_meas()
2088 regmap_read(cs43130->regmap, CS43130_INT_STATUS_4, ®); in cs43130_imp_meas()
2090 switch (cs43130->dev_id) { in cs43130_imp_meas()
2100 WARN(1, "Invalid dev_id for meas: %d", cs43130->dev_id); in cs43130_imp_meas()
2115 if (cs43130->ac_meas && in cs43130_imp_meas()
2117 ac_idx < CS43130_AC_FREQ - 1) { in cs43130_imp_meas()
2124 cs43130->hpload_done = true; in cs43130_imp_meas()
2126 if (cs43130->hpload_dc[HP_LEFT] >= CS43130_LINEOUT_LOAD) in cs43130_imp_meas()
2127 snd_soc_jack_report(&cs43130->jack, CS43130_JACK_LINEOUT, in cs43130_imp_meas()
2130 snd_soc_jack_report(&cs43130->jack, CS43130_JACK_HEADPHONE, in cs43130_imp_meas()
2133 dev_dbg(component->dev, "Set HP output control. DC threshold\n"); in cs43130_imp_meas()
2135 dev_dbg(component->dev, "DC threshold[%d]: %u.\n", i, in cs43130_imp_meas()
2136 cs43130->dc_threshold[i]); in cs43130_imp_meas()
2138 cs43130_set_hv(cs43130->regmap, cs43130->hpload_dc[HP_LEFT], in cs43130_imp_meas()
2139 cs43130->dc_threshold); in cs43130_imp_meas()
2142 switch (cs43130->dev_id) { in cs43130_imp_meas()
2155 regmap_multi_reg_write(cs43130->regmap, hp_cln_seq, in cs43130_imp_meas()
2158 mutex_lock(&cs43130->clk_mutex); in cs43130_imp_meas()
2159 cs43130->clk_req--; in cs43130_imp_meas()
2161 if (!cs43130->clk_req) in cs43130_imp_meas()
2163 mutex_unlock(&cs43130->clk_mutex); in cs43130_imp_meas()
2169 struct snd_soc_component *component = cs43130->component; in cs43130_irq_thread()
2176 regmap_read(cs43130->regmap, CS43130_INT_STATUS_1 + i, in cs43130_irq_thread()
2178 regmap_read(cs43130->regmap, CS43130_INT_MASK_1 + i, in cs43130_irq_thread()
2187 dev_dbg(component->dev, "number of interrupts occurred (%u)\n", in cs43130_irq_thread()
2194 complete(&cs43130->xtal_rdy); in cs43130_irq_thread()
2199 complete(&cs43130->pll_rdy); in cs43130_irq_thread()
2204 cs43130->hpload_stat = stickies[3]; in cs43130_irq_thread()
2205 dev_err(component->dev, in cs43130_irq_thread()
2206 "DC load has not completed before AC load (%x)\n", in cs43130_irq_thread()
2207 cs43130->hpload_stat); in cs43130_irq_thread()
2208 complete(&cs43130->hpload_evt); in cs43130_irq_thread()
2213 cs43130->hpload_stat = stickies[3]; in cs43130_irq_thread()
2214 dev_err(component->dev, "HP unplugged during measurement (%x)\n", in cs43130_irq_thread()
2215 cs43130->hpload_stat); in cs43130_irq_thread()
2216 complete(&cs43130->hpload_evt); in cs43130_irq_thread()
2221 cs43130->hpload_stat = stickies[3]; in cs43130_irq_thread()
2222 dev_err(component->dev, "HP load out of range (%x)\n", in cs43130_irq_thread()
2223 cs43130->hpload_stat); in cs43130_irq_thread()
2224 complete(&cs43130->hpload_evt); in cs43130_irq_thread()
2229 cs43130->hpload_stat = stickies[3]; in cs43130_irq_thread()
2230 dev_dbg(component->dev, "HP AC load measurement done (%x)\n", in cs43130_irq_thread()
2231 cs43130->hpload_stat); in cs43130_irq_thread()
2232 complete(&cs43130->hpload_evt); in cs43130_irq_thread()
2237 cs43130->hpload_stat = stickies[3]; in cs43130_irq_thread()
2238 dev_dbg(component->dev, "HP DC load measurement done (%x)\n", in cs43130_irq_thread()
2239 cs43130->hpload_stat); in cs43130_irq_thread()
2240 complete(&cs43130->hpload_evt); in cs43130_irq_thread()
2245 cs43130->hpload_stat = stickies[3]; in cs43130_irq_thread()
2246 dev_dbg(component->dev, "HP load state machine on done (%x)\n", in cs43130_irq_thread()
2247 cs43130->hpload_stat); in cs43130_irq_thread()
2248 complete(&cs43130->hpload_evt); in cs43130_irq_thread()
2253 cs43130->hpload_stat = stickies[3]; in cs43130_irq_thread()
2254 dev_dbg(component->dev, "HP load state machine off done (%x)\n", in cs43130_irq_thread()
2255 cs43130->hpload_stat); in cs43130_irq_thread()
2256 complete(&cs43130->hpload_evt); in cs43130_irq_thread()
2261 dev_err(component->dev, "Crystal err: clock is not running\n"); in cs43130_irq_thread()
2266 dev_dbg(component->dev, "HP unplugged\n"); in cs43130_irq_thread()
2267 cs43130->hpload_done = false; in cs43130_irq_thread()
2268 snd_soc_jack_report(&cs43130->jack, 0, CS43130_JACK_MASK); in cs43130_irq_thread()
2273 if (cs43130->dc_meas && !cs43130->hpload_done && in cs43130_irq_thread()
2274 !work_busy(&cs43130->work)) { in cs43130_irq_thread()
2275 dev_dbg(component->dev, "HP load queue work\n"); in cs43130_irq_thread()
2276 queue_work(cs43130->wq, &cs43130->work); in cs43130_irq_thread()
2279 snd_soc_jack_report(&cs43130->jack, SND_JACK_MECHANICAL, in cs43130_irq_thread()
2291 struct snd_soc_card *card = component->card; in cs43130_probe()
2294 cs43130->component = component; in cs43130_probe()
2296 if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED) { in cs43130_probe()
2297 regmap_update_bits(cs43130->regmap, CS43130_CRYSTAL_SET, in cs43130_probe()
2299 cs43130->xtal_ibias); in cs43130_probe()
2300 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, in cs43130_probe()
2305 &cs43130->jack); in cs43130_probe()
2307 dev_err(component->dev, "Cannot create jack\n"); in cs43130_probe()
2311 cs43130->hpload_done = false; in cs43130_probe()
2312 if (cs43130->dc_meas) { in cs43130_probe()
2313 ret = sysfs_create_groups(&component->dev->kobj, hpload_groups); in cs43130_probe()
2317 cs43130->wq = create_singlethread_workqueue("cs43130_hp"); in cs43130_probe()
2318 if (!cs43130->wq) { in cs43130_probe()
2319 sysfs_remove_groups(&component->dev->kobj, hpload_groups); in cs43130_probe()
2320 return -ENOMEM; in cs43130_probe()
2322 INIT_WORK(&cs43130->work, cs43130_imp_meas); in cs43130_probe()
2325 regmap_read(cs43130->regmap, CS43130_INT_STATUS_1, ®); in cs43130_probe()
2326 regmap_read(cs43130->regmap, CS43130_HP_STATUS, ®); in cs43130_probe()
2327 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, in cs43130_probe()
2329 regmap_update_bits(cs43130->regmap, CS43130_HP_DETECT, in cs43130_probe()
2331 regmap_update_bits(cs43130->regmap, CS43130_HP_DETECT, in cs43130_probe()
2374 struct device_node *np = i2c_client->dev.of_node; in cs43130_handle_device_data()
2378 if (of_property_read_u32(np, "cirrus,xtal-ibias", &val) < 0) { in cs43130_handle_device_data()
2380 cs43130->xtal_ibias = CS43130_XTAL_UNUSED; in cs43130_handle_device_data()
2386 cs43130->xtal_ibias = CS43130_XTAL_IBIAS_7_5UA; in cs43130_handle_device_data()
2389 cs43130->xtal_ibias = CS43130_XTAL_IBIAS_12_5UA; in cs43130_handle_device_data()
2392 cs43130->xtal_ibias = CS43130_XTAL_IBIAS_15UA; in cs43130_handle_device_data()
2395 dev_err(&i2c_client->dev, in cs43130_handle_device_data()
2396 "Invalid cirrus,xtal-ibias value: %d\n", val); in cs43130_handle_device_data()
2397 return -EINVAL; in cs43130_handle_device_data()
2400 cs43130->dc_meas = of_property_read_bool(np, "cirrus,dc-measure"); in cs43130_handle_device_data()
2401 cs43130->ac_meas = of_property_read_bool(np, "cirrus,ac-measure"); in cs43130_handle_device_data()
2403 if (of_property_read_u16_array(np, "cirrus,ac-freq", cs43130->ac_freq, in cs43130_handle_device_data()
2406 cs43130->ac_freq[i] = cs43130_ac_freq[i]; in cs43130_handle_device_data()
2409 if (of_property_read_u16_array(np, "cirrus,dc-threshold", in cs43130_handle_device_data()
2410 cs43130->dc_threshold, in cs43130_handle_device_data()
2413 cs43130->dc_threshold[i] = cs43130_dc_threshold[i]; in cs43130_handle_device_data()
2426 cs43130 = devm_kzalloc(&client->dev, sizeof(*cs43130), GFP_KERNEL); in cs43130_i2c_probe()
2428 return -ENOMEM; in cs43130_i2c_probe()
2432 cs43130->regmap = devm_regmap_init_i2c(client, &cs43130_regmap); in cs43130_i2c_probe()
2433 if (IS_ERR(cs43130->regmap)) { in cs43130_i2c_probe()
2434 ret = PTR_ERR(cs43130->regmap); in cs43130_i2c_probe()
2438 if (client->dev.of_node) { in cs43130_i2c_probe()
2443 for (i = 0; i < ARRAY_SIZE(cs43130->supplies); i++) in cs43130_i2c_probe()
2444 cs43130->supplies[i].supply = cs43130_supply_names[i]; in cs43130_i2c_probe()
2446 ret = devm_regulator_bulk_get(&client->dev, in cs43130_i2c_probe()
2447 ARRAY_SIZE(cs43130->supplies), in cs43130_i2c_probe()
2448 cs43130->supplies); in cs43130_i2c_probe()
2450 dev_err(&client->dev, "Failed to request supplies: %d\n", ret); in cs43130_i2c_probe()
2453 ret = regulator_bulk_enable(ARRAY_SIZE(cs43130->supplies), in cs43130_i2c_probe()
2454 cs43130->supplies); in cs43130_i2c_probe()
2456 dev_err(&client->dev, "Failed to enable supplies: %d\n", ret); in cs43130_i2c_probe()
2460 cs43130->reset_gpio = devm_gpiod_get_optional(&client->dev, in cs43130_i2c_probe()
2462 if (IS_ERR(cs43130->reset_gpio)) { in cs43130_i2c_probe()
2463 ret = PTR_ERR(cs43130->reset_gpio); in cs43130_i2c_probe()
2467 gpiod_set_value_cansleep(cs43130->reset_gpio, 1); in cs43130_i2c_probe()
2471 devid = cirrus_read_device_id(cs43130->regmap, CS43130_DEVID_AB); in cs43130_i2c_probe()
2474 dev_err(&client->dev, "Failed to read device ID: %d\n", ret); in cs43130_i2c_probe()
2485 dev_err(&client->dev, in cs43130_i2c_probe()
2489 ret = -ENODEV; in cs43130_i2c_probe()
2493 cs43130->dev_id = devid; in cs43130_i2c_probe()
2494 ret = regmap_read(cs43130->regmap, CS43130_REV_ID, ®); in cs43130_i2c_probe()
2496 dev_err(&client->dev, "Get Revision ID failed\n"); in cs43130_i2c_probe()
2500 dev_info(&client->dev, in cs43130_i2c_probe()
2504 mutex_init(&cs43130->clk_mutex); in cs43130_i2c_probe()
2506 init_completion(&cs43130->xtal_rdy); in cs43130_i2c_probe()
2507 init_completion(&cs43130->pll_rdy); in cs43130_i2c_probe()
2508 init_completion(&cs43130->hpload_evt); in cs43130_i2c_probe()
2510 ret = devm_request_threaded_irq(&client->dev, client->irq, in cs43130_i2c_probe()
2515 dev_err(&client->dev, "Failed to request IRQ: %d\n", ret); in cs43130_i2c_probe()
2519 cs43130->mclk_int_src = CS43130_MCLK_SRC_RCO; in cs43130_i2c_probe()
2521 pm_runtime_set_autosuspend_delay(&client->dev, 100); in cs43130_i2c_probe()
2522 pm_runtime_use_autosuspend(&client->dev); in cs43130_i2c_probe()
2523 pm_runtime_set_active(&client->dev); in cs43130_i2c_probe()
2524 pm_runtime_enable(&client->dev); in cs43130_i2c_probe()
2526 switch (cs43130->dev_id) { in cs43130_i2c_probe()
2560 ret = devm_snd_soc_register_component(&client->dev, in cs43130_i2c_probe()
2564 dev_err(&client->dev, in cs43130_i2c_probe()
2569 regmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG, in cs43130_i2c_probe()
2571 regmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG, in cs43130_i2c_probe()
2577 gpiod_set_value_cansleep(cs43130->reset_gpio, 0); in cs43130_i2c_probe()
2579 regulator_bulk_disable(ARRAY_SIZE(cs43130->supplies), in cs43130_i2c_probe()
2580 cs43130->supplies); in cs43130_i2c_probe()
2589 if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED) in cs43130_i2c_remove()
2590 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, in cs43130_i2c_remove()
2594 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, in cs43130_i2c_remove()
2598 if (cs43130->dc_meas) { in cs43130_i2c_remove()
2599 cancel_work_sync(&cs43130->work); in cs43130_i2c_remove()
2600 flush_workqueue(cs43130->wq); in cs43130_i2c_remove()
2602 device_remove_file(&client->dev, &dev_attr_hpload_dc_l); in cs43130_i2c_remove()
2603 device_remove_file(&client->dev, &dev_attr_hpload_dc_r); in cs43130_i2c_remove()
2604 device_remove_file(&client->dev, &dev_attr_hpload_ac_l); in cs43130_i2c_remove()
2605 device_remove_file(&client->dev, &dev_attr_hpload_ac_r); in cs43130_i2c_remove()
2608 gpiod_set_value_cansleep(cs43130->reset_gpio, 0); in cs43130_i2c_remove()
2610 pm_runtime_disable(&client->dev); in cs43130_i2c_remove()
2611 regulator_bulk_disable(CS43130_NUM_SUPPLIES, cs43130->supplies); in cs43130_i2c_remove()
2618 if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED) in cs43130_runtime_suspend()
2619 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, in cs43130_runtime_suspend()
2623 regcache_cache_only(cs43130->regmap, true); in cs43130_runtime_suspend()
2624 regcache_mark_dirty(cs43130->regmap); in cs43130_runtime_suspend()
2626 gpiod_set_value_cansleep(cs43130->reset_gpio, 0); in cs43130_runtime_suspend()
2628 regulator_bulk_disable(CS43130_NUM_SUPPLIES, cs43130->supplies); in cs43130_runtime_suspend()
2638 ret = regulator_bulk_enable(CS43130_NUM_SUPPLIES, cs43130->supplies); in cs43130_runtime_resume()
2644 regcache_cache_only(cs43130->regmap, false); in cs43130_runtime_resume()
2646 gpiod_set_value_cansleep(cs43130->reset_gpio, 1); in cs43130_runtime_resume()
2650 ret = regcache_sync(cs43130->regmap); in cs43130_runtime_resume()
2656 if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED) in cs43130_runtime_resume()
2657 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, in cs43130_runtime_resume()
2662 regcache_cache_only(cs43130->regmap, true); in cs43130_runtime_resume()
2663 regulator_bulk_disable(CS43130_NUM_SUPPLIES, cs43130->supplies); in cs43130_runtime_resume()