214 	u32 wcreg;    /* cached write control register value */  member
256 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
257 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
513 	writel(rme96->wcreg | RME96_WCR_PD,  in snd_rme96_reset_dac()
515 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_reset_dac()
521 	return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +  in snd_rme96_getmontracks()
522 		(((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);  in snd_rme96_getmontracks()
530 		rme96->wcreg |= RME96_WCR_MONITOR_0;  in snd_rme96_setmontracks()
532 		rme96->wcreg &= ~RME96_WCR_MONITOR_0;  in snd_rme96_setmontracks()
535 		rme96->wcreg |= RME96_WCR_MONITOR_1;  in snd_rme96_setmontracks()
537 		rme96->wcreg &= ~RME96_WCR_MONITOR_1;  in snd_rme96_setmontracks()
539 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_setmontracks()
546 	return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +  in snd_rme96_getattenuation()
547 		(((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);  in snd_rme96_getattenuation()
556 		rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &  in snd_rme96_setattenuation()
560 		rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &  in snd_rme96_setattenuation()
564 		rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |  in snd_rme96_setattenuation()
568 		rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |  in snd_rme96_setattenuation()
574 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_setattenuation()
646 	if (!(rme96->wcreg & RME96_WCR_MASTER) &&  in snd_rme96_playback_getrate()
655 	rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +  in snd_rme96_playback_getrate()
656 		(((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);  in snd_rme96_playback_getrate()
670 	return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;  in snd_rme96_playback_getrate()
679 	ds = rme96->wcreg & RME96_WCR_DS;  in snd_rme96_playback_setrate()
682 		rme96->wcreg &= ~RME96_WCR_DS;  in snd_rme96_playback_setrate()
683 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &  in snd_rme96_playback_setrate()
687 		rme96->wcreg &= ~RME96_WCR_DS;  in snd_rme96_playback_setrate()
688 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &  in snd_rme96_playback_setrate()
692 		rme96->wcreg &= ~RME96_WCR_DS;  in snd_rme96_playback_setrate()
693 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |  in snd_rme96_playback_setrate()
697 		rme96->wcreg |= RME96_WCR_DS;  in snd_rme96_playback_setrate()
698 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &  in snd_rme96_playback_setrate()
702 		rme96->wcreg |= RME96_WCR_DS;  in snd_rme96_playback_setrate()
703 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &  in snd_rme96_playback_setrate()
707 		rme96->wcreg |= RME96_WCR_DS;  in snd_rme96_playback_setrate()
708 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |  in snd_rme96_playback_setrate()
714 	if ((!ds && rme96->wcreg & RME96_WCR_DS) ||  in snd_rme96_playback_setrate()
715 	    (ds && !(rme96->wcreg & RME96_WCR_DS)))  in snd_rme96_playback_setrate()
721 		writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_playback_setrate()
775 		rme96->wcreg &= ~RME96_WCR_MASTER;  in snd_rme96_setclockmode()
780 		rme96->wcreg |= RME96_WCR_MASTER;  in snd_rme96_setclockmode()
785 		rme96->wcreg |= RME96_WCR_MASTER;   in snd_rme96_setclockmode()
791 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_setclockmode()
802 	return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :  in snd_rme96_getclockmode()
814 		rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &  in snd_rme96_setinputtype()
818 		rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &  in snd_rme96_setinputtype()
822 		rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |  in snd_rme96_setinputtype()
834 		rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |  in snd_rme96_setinputtype()
863 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_setinputtype()
873 	return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +  in snd_rme96_getinputtype()
874 		(((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);  in snd_rme96_getinputtype()
891 		frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;  in snd_rme96_setframelog()
894 		frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;  in snd_rme96_setframelog()
904 		rme96->wcreg &= ~RME96_WCR_MODE24;  in snd_rme96_playback_setformat()
907 		rme96->wcreg |= RME96_WCR_MODE24;  in snd_rme96_playback_setformat()
912 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_playback_setformat()
921 		rme96->wcreg &= ~RME96_WCR_MODE24_2;  in snd_rme96_capture_setformat()
924 		rme96->wcreg |= RME96_WCR_MODE24_2;  in snd_rme96_capture_setformat()
929 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_capture_setformat()
939 		rme96->wcreg &= ~RME96_WCR_ISEL;  in snd_rme96_set_period_properties()
942 		rme96->wcreg |= RME96_WCR_ISEL;  in snd_rme96_set_period_properties()
948 	rme96->wcreg &= ~RME96_WCR_IDIS;  in snd_rme96_set_period_properties()
949 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_set_period_properties()
968 	if (!(rme96->wcreg & RME96_WCR_MASTER) &&  in snd_rme96_playback_hw_params()
1000 	if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {  in snd_rme96_playback_hw_params()
1001 		rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);  in snd_rme96_playback_hw_params()
1002 		writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_playback_hw_params()
1091 		rme96->wcreg |= RME96_WCR_START;  in snd_rme96_trigger()
1093 		rme96->wcreg &= ~RME96_WCR_START;  in snd_rme96_trigger()
1095 		rme96->wcreg |= RME96_WCR_START_2;  in snd_rme96_trigger()
1097 		rme96->wcreg &= ~RME96_WCR_START_2;  in snd_rme96_trigger()
1098 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_trigger()
1172 	rme96->wcreg &= ~RME96_WCR_ADAT;  in snd_rme96_playback_spdif_open()
1173 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_playback_spdif_open()
1178 	if (!(rme96->wcreg & RME96_WCR_MASTER) &&  in snd_rme96_playback_spdif_open()
1242 	rme96->wcreg |= RME96_WCR_ADAT;  in snd_rme96_playback_adat_open()
1243 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_playback_adat_open()
1248 	if (!(rme96->wcreg & RME96_WCR_MASTER) &&  in snd_rme96_playback_adat_open()
1311 	spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;  in snd_rme96_playback_close()
1642 	rme96->wcreg =  in snd_rme96_create()
1650 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_create()
1700 	if (rme96->wcreg & RME96_WCR_IDIS) {  in snd_rme96_proc_read()
1703 	} else if (rme96->wcreg & RME96_WCR_ISEL) {  in snd_rme96_proc_read()
1737 	if (rme96->wcreg & RME96_WCR_MODE24_2) {  in snd_rme96_proc_read()
1744 	if (rme96->wcreg & RME96_WCR_SEL) {  in snd_rme96_proc_read()
1751 	if (rme96->wcreg & RME96_WCR_MODE24) {  in snd_rme96_proc_read()
1758 	} else if (rme96->wcreg & RME96_WCR_MASTER) {  in snd_rme96_proc_read()
1767 	if (rme96->wcreg & RME96_WCR_PRO) {  in snd_rme96_proc_read()
1772 	if (rme96->wcreg & RME96_WCR_EMP) {  in snd_rme96_proc_read()
1777 	if (rme96->wcreg & RME96_WCR_DOLBY) {  in snd_rme96_proc_read()
1834 	ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;  in snd_rme96_get_loopback_control()
1847 	val = (rme96->wcreg & ~RME96_WCR_SEL) | val;  in snd_rme96_put_loopback_control()
1848 	change = val != rme96->wcreg;  in snd_rme96_put_loopback_control()
1849 	rme96->wcreg = val;  in snd_rme96_put_loopback_control()
2147 	rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);  in snd_rme96_control_spdif_stream_put()
2148 	rme96->wcreg |= val;  in snd_rme96_control_spdif_stream_put()
2149 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_control_spdif_stream_put()