Lines Matching full:1200
705 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
713 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
721 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
729 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
737 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
745 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
838 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
846 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
853 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
860 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
867 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \