Lines Matching full:layout
46 * format and data layout of the buffer, and should be the only way to describe
49 * Having multiple fourcc:modifier pairs which describe the same layout should
61 * Modifiers must uniquely encode buffer layout. In other words, a buffer must
287 * then V), but the exact Linear layout is undefined.
439 * When adding a new token please document the layout with a code comment,
455 * In future cases where a generic layout is identified before merging with a
479 * Linear Layout
481 * Just plain linear layout. Note that this is different from no specifying any
492 * implicit, instead it means that the layout is linear. Whether modifiers are
501 * Intel X-tiling layout
503 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
504 * in row-major layout. Within the tile bytes are laid out row-major, with
508 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
511 * identify the layout in a simple way for i915-specific userspace, which
518 * Intel Y-tiling layout
520 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
521 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
526 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
529 * identify the layout in a simple way for i915-specific userspace, which
536 * Intel Yf-tiling layout
538 * This is a tiled layout using 4Kb tiles in row-major layout.
540 * are arranged in four groups (two wide, two high) with column-major layout.
614 * Intel Tile 4 layout
616 * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
721 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
722 * layout. For YCbCr formats Cb/Cr components are taken in such a way that
765 * Vivante 4x4 tiling layout
767 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
768 * layout.
773 * Vivante 64x64 super-tiling layout
775 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
777 * major layout.
785 * Vivante 4x4 tiling layout for dual-pipe
787 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
789 * compared to the non-split tiled layout.
794 * Vivante 64x64 super-tiling layout for dual-pipe
796 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
798 * therefore halved compared to the non-split super-tiled layout.
810 * clear/compression modifiers, as future cores might add some more TS layout
834 * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
841 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80,
844 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies
861 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
878 * tables of all GPUs >= NV50. It affects the exact layout of bits
886 * since the modifier should define the layout of the associated
892 * kind and bit layout has changed at various points.
899 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
901 * page kind and block linear swizzles. This causes the layout of
905 * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
906 * 1 = Desktop GPU and Tegra Xavier+ Layout
911 * 1 = ROP/3D, layout 1, exact compression format implied by Page
913 * 2 = ROP/3D, layout 2, exact compression format implied by Page
931 /* To grandfather in prior block linear format modifiers to the above layout,
947 * 16Bx2 Block Linear layout, used by Tegra K1 and later
1003 * This is the primary layout that the V3D GPU can texture from (it
1155 * AFBC sparse layout
1176 * AFBC tiled layout
1178 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
1182 * When the tiled layout is used, the buffer size (in pixels) must be aligned
1198 * Indicates that the buffer is allocated in a layout safe for front-buffer
1215 * The buffer layout is the same as for AFBC buffers without USM set, this only
1251 * scanline (SCAN layout) or rotated (ROT layout) access.
1253 * Layout Paging Tile Width Paging Tile Height
1260 * scanline (SCAN layout) or rotated (ROT layout) access.
1262 * Number of Components in Plane Layout Coding Unit Width Coding Unit Height
1317 * AFRC scanline memory layout.
1319 * Indicates if the buffer uses the scanline-optimised layout
1320 * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout.
1321 * The memory layout is the same for all planes.
1364 * The first 8 bits of the mode defines the layout, then the following 8 bits
1365 * defines the options changing the layout.
1368 * combinations of layout and options.
1383 * Amlogic FBC Basic Layout
1385 * The basic layout is composed of:
1390 * This layout is transferrable between Amlogic SoCs supporting this modifier.
1395 * Amlogic FBC Scatter Memory layout
1398 * frames content to optimize memory access and layout.
1405 * Due to the nature of the layout, these buffers are not expected to
1414 /* Amlogic FBC Layout Options Bit Mask */
1423 * This mode reduces body layout to 3072 bytes per 64x32 superblock with
1424 * the basic layout and 3200 bytes per 64x32 superblock combined with
1425 * the scatter layout.
1432 * Memory layout: