Lines Matching +full:0 +full:x644

76 #define GENI_FORCE_DEFAULT_REG		0x20
77 #define GENI_OUTPUT_CTRL		0x24
78 #define SE_GENI_STATUS			0x40
79 #define GENI_SER_M_CLK_CFG		0x48
80 #define GENI_SER_S_CLK_CFG		0x4c
81 #define GENI_IF_DISABLE_RO		0x64
82 #define GENI_FW_REVISION_RO		0x68
83 #define SE_GENI_CLK_SEL			0x7c
84 #define SE_GENI_CFG_SEQ_START		0x84
85 #define SE_GENI_DMA_MODE_EN		0x258
86 #define SE_GENI_M_CMD0			0x600
87 #define SE_GENI_M_CMD_CTRL_REG		0x604
88 #define SE_GENI_M_IRQ_STATUS		0x610
89 #define SE_GENI_M_IRQ_EN		0x614
90 #define SE_GENI_M_IRQ_CLEAR		0x618
91 #define SE_GENI_S_CMD0			0x630
92 #define SE_GENI_S_CMD_CTRL_REG		0x634
93 #define SE_GENI_S_IRQ_STATUS		0x640
94 #define SE_GENI_S_IRQ_EN		0x644
95 #define SE_GENI_S_IRQ_CLEAR		0x648
96 #define SE_GENI_TX_FIFOn		0x700
97 #define SE_GENI_RX_FIFOn		0x780
98 #define SE_GENI_TX_FIFO_STATUS		0x800
99 #define SE_GENI_RX_FIFO_STATUS		0x804
100 #define SE_GENI_TX_WATERMARK_REG	0x80c
101 #define SE_GENI_RX_WATERMARK_REG	0x810
102 #define SE_GENI_RX_RFR_WATERMARK_REG	0x814
103 #define SE_GENI_IOS			0x908
104 #define SE_DMA_TX_IRQ_STAT		0xc40
105 #define SE_DMA_TX_IRQ_CLR		0xc44
106 #define SE_DMA_TX_FSM_RST		0xc58
107 #define SE_DMA_RX_IRQ_STAT		0xd40
108 #define SE_DMA_RX_IRQ_CLR		0xd44
109 #define SE_DMA_RX_LEN_IN		0xd54
110 #define SE_DMA_RX_FSM_RST		0xd58
111 #define SE_HW_PARAM_0			0xe24
112 #define SE_HW_PARAM_1			0xe28
115 #define FORCE_DEFAULT	BIT(0)
118 #define GENI_IO_MUX_0_EN		BIT(0)
121 #define M_GENI_CMD_ACTIVE		BIT(0)
125 #define SER_CLK_EN			BIT(0)
130 #define FIFO_IF_DISABLE			(BIT(0))
137 #define CLK_SEL_MSK			GENMASK(2, 0)
140 #define START_TRIGGER			BIT(0)
143 #define GENI_DMA_MODE_EN		BIT(0)
148 #define M_PARAMS_MSK			GENMASK(26, 0)
153 #define M_GENI_DISABLE			BIT(0)
158 #define S_PARAMS_MSK			GENMASK(26, 0)
163 #define S_GENI_DISABLE			BIT(0)
166 #define M_CMD_DONE_EN			BIT(0)
198 #define S_CMD_DONE_EN			BIT(0)
221 #define WATERMARK_MSK			GENMASK(5, 0)
224 #define TX_FIFO_WC			GENMASK(27, 0)
230 #define RX_FIFO_WC_MSK			GENMASK(24, 0)
234 #define RX_DATA_IN			BIT(0)
237 #define TX_DMA_DONE			BIT(0)
243 #define RX_DMA_DONE			BIT(0)
280 #define HW_VER_STEP_MASK		GENMASK(15, 0)
287 #define QUP_SE_VERSION_2_5                  0x20050000