Lines Matching +full:0 +full:x418
12 #define DEBUG_QMGR 0
25 #define QUEUE_WATERMARK_0_ENTRIES 0
35 #define QUEUE_IRQ_SRC_EMPTY 0
45 u32 acc[QUEUES][MAX_QUEUE_LENGTH]; /* 0x000 - 0x3FF */
46 u32 stat1[4]; /* 0x400 - 0x40F */
47 u32 stat2[2]; /* 0x410 - 0x417 */
48 u32 statne_h; /* 0x418 - queue nearly empty */
49 u32 statf_h; /* 0x41C - queue full */
50 u32 irqsrc[4]; /* 0x420 - 0x42F IRC source */
51 u32 irqen[2]; /* 0x430 - 0x437 IRQ enabled */
52 u32 irqstat[2]; /* 0x438 - 0x43F - IRQ access only */
54 u32 sram[2048]; /* 0x2000 - 0x3FFF - config and buffer */