1258 #define MLX5_CAP_GEN(mdev, cap) \  argument
1259 	MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1261 #define MLX5_CAP_GEN_64(mdev, cap) \  argument
1262 	MLX5_GET64(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1264 #define MLX5_CAP_GEN_MAX(mdev, cap) \  argument
1265 	MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->max, cap)
1267 #define MLX5_CAP_GEN_2(mdev, cap) \  argument
1268 	MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1270 #define MLX5_CAP_GEN_2_64(mdev, cap) \  argument
1271 	MLX5_GET64(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1273 #define MLX5_CAP_GEN_2_MAX(mdev, cap) \  argument
1274 	MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->max, cap)
1276 #define MLX5_CAP_ETH(mdev, cap) \  argument
1278 		 mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->cur, cap)
1280 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \  argument
1282 		 mdev->caps.hca[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS]->cur, cap)
1284 #define MLX5_CAP_ROCE(mdev, cap) \  argument
1285 	MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->cur, cap)
1287 #define MLX5_CAP_ROCE_MAX(mdev, cap) \  argument
1288 	MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->max, cap)
1290 #define MLX5_CAP_ATOMIC(mdev, cap) \  argument
1291 	MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->cur, cap)
1293 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \  argument
1294 	MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->max, cap)
1296 #define MLX5_CAP_FLOWTABLE(mdev, cap) \  argument
1297 	MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1299 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \  argument
1300 	MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1302 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \  argument
1303 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1305 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \  argument
1306 		MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap)
1308 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \  argument
1309 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1311 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \  argument
1312 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1314 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \  argument
1315 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap)
1317 #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \  argument
1318 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap)
1320 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \  argument
1322 		 mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1324 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \  argument
1325 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1327 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \  argument
1328 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1330 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \  argument
1331 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1333 #define MLX5_CAP_ESW_FT_FIELD_SUPPORT_2(mdev, cap) \  argument
1334 	MLX5_CAP_ESW_FLOWTABLE(mdev, ft_field_support_2_esw_fdb.cap)
1336 #define MLX5_CAP_ESW(mdev, cap) \  argument
1338 		 mdev->caps.hca[MLX5_CAP_ESWITCH]->cur, cap)
1340 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \  argument
1342 		(mdev)->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1344 #define MLX5_CAP_PORT_SELECTION(mdev, cap) \  argument
1346 		 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur, cap)
1348 #define MLX5_CAP_PORT_SELECTION_MAX(mdev, cap) \  argument
1350 		 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->max, cap)
1352 #define MLX5_CAP_ADV_VIRTUALIZATION(mdev, cap) \  argument
1354 		 mdev->caps.hca[MLX5_CAP_ADV_VIRTUALIZATION]->cur, cap)
1356 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \  argument
1357 	MLX5_CAP_PORT_SELECTION(mdev, flow_table_properties_port_selection.cap)
1359 #define MLX5_CAP_ODP(mdev, cap)\  argument
1360 	MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, cap)
1362 #define MLX5_CAP_ODP_MAX(mdev, cap)\  argument
1363 	MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->max, cap)
1365 #define MLX5_CAP_QOS(mdev, cap)\  argument
1366 	MLX5_GET(qos_cap, mdev->caps.hca[MLX5_CAP_QOS]->cur, cap)
1368 #define MLX5_CAP_DEBUG(mdev, cap)\  argument
1369 	MLX5_GET(debug_cap, mdev->caps.hca[MLX5_CAP_DEBUG]->cur, cap)
1394 #define MLX5_CAP_FPGA(mdev, cap) \  argument
1395 	MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1397 #define MLX5_CAP64_FPGA(mdev, cap) \  argument
1398 	MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1400 #define MLX5_CAP_DEV_MEM(mdev, cap)\  argument
1401 	MLX5_GET(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1403 #define MLX5_CAP64_DEV_MEM(mdev, cap)\  argument
1404 	MLX5_GET64(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1406 #define MLX5_CAP_TLS(mdev, cap) \  argument
1407 	MLX5_GET(tls_cap, (mdev)->caps.hca[MLX5_CAP_TLS]->cur, cap)
1409 #define MLX5_CAP_DEV_EVENT(mdev, cap)\  argument
1410 	MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca[MLX5_CAP_DEV_EVENT]->cur, cap)
1412 #define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\  argument
1414 		(mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1416 #define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\  argument
1418 		(mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1420 #define MLX5_CAP_IPSEC(mdev, cap)\  argument
1421 	MLX5_GET(ipsec_cap, (mdev)->caps.hca[MLX5_CAP_IPSEC]->cur, cap)
1423 #define MLX5_CAP_CRYPTO(mdev, cap)\  argument
1424 	MLX5_GET(crypto_cap, (mdev)->caps.hca[MLX5_CAP_CRYPTO]->cur, cap)
1426 #define MLX5_CAP_MACSEC(mdev, cap)\  argument
1427 	MLX5_GET(macsec_cap, (mdev)->caps.hca[MLX5_CAP_MACSEC]->cur, cap)