Lines Matching +full:0 +full:xf0
18 #define TPS65217 0xF0
21 #define TPS65217_I2C_ID 0x24
24 #define TPS65217_REG_CHIPID 0X00
25 #define TPS65217_REG_PPATH 0X01
26 #define TPS65217_REG_INT 0X02
27 #define TPS65217_REG_CHGCONFIG0 0X03
28 #define TPS65217_REG_CHGCONFIG1 0X04
29 #define TPS65217_REG_CHGCONFIG2 0X05
30 #define TPS65217_REG_CHGCONFIG3 0X06
31 #define TPS65217_REG_WLEDCTRL1 0X07
32 #define TPS65217_REG_WLEDCTRL2 0X08
33 #define TPS65217_REG_MUXCTRL 0X09
34 #define TPS65217_REG_STATUS 0X0A
35 #define TPS65217_REG_PASSWORD 0X0B
36 #define TPS65217_REG_PGOOD 0X0C
37 #define TPS65217_REG_DEFPG 0X0D
38 #define TPS65217_REG_DEFDCDC1 0X0E
39 #define TPS65217_REG_DEFDCDC2 0X0F
40 #define TPS65217_REG_DEFDCDC3 0X10
41 #define TPS65217_REG_DEFSLEW 0X11
42 #define TPS65217_REG_DEFLDO1 0X12
43 #define TPS65217_REG_DEFLDO2 0X13
44 #define TPS65217_REG_DEFLS1 0X14
45 #define TPS65217_REG_DEFLS2 0X15
46 #define TPS65217_REG_ENABLE 0X16
47 #define TPS65217_REG_DEFUVLO 0X18
48 #define TPS65217_REG_SEQ1 0X19
49 #define TPS65217_REG_SEQ2 0X1A
50 #define TPS65217_REG_SEQ3 0X1B
51 #define TPS65217_REG_SEQ4 0X1C
52 #define TPS65217_REG_SEQ5 0X1D
53 #define TPS65217_REG_SEQ6 0X1E
58 #define TPS65217_CHIPID_CHIP_MASK 0xF0
59 #define TPS65217_CHIPID_REV_MASK 0x0F
65 #define TPS65217_PPATH_AC_CURRENT_MASK 0x0C
66 #define TPS65217_PPATH_USB_CURRENT_MASK 0x03
73 #define TPS65217_INT_USBI BIT(0)
85 #define TPS65217_CHGCONFIG0_BATTEMP BIT(0)
87 #define TPS65217_CHGCONFIG1_TMR_MASK 0xC0
93 #define TPS65217_CHGCONFIG1_CHG_EN BIT(0)
97 #define TPS65217_CHGCONFIG2_VOREG_MASK 0x30
99 #define TPS65217_CHGCONFIG3_ICHRG_MASK 0xC0
100 #define TPS65217_CHGCONFIG3_DPPMTH_MASK 0x30
102 #define TPS65217_CHGCONFIG2_TERMIF 0x06
103 #define TPS65217_CHGCONFIG2_TRANGE BIT(0)
107 #define TPS65217_WLEDCTRL1_FDIM_MASK 0x03
109 #define TPS65217_WLEDCTRL2_DUTY_MASK 0x7F
111 #define TPS65217_MUXCTRL_MUX_MASK 0x07
116 #define TPS65217_STATUS_PB BIT(0)
118 #define TPS65217_PASSWORD_REGS_UNLOCK 0x7D
126 #define TPS65217_PGOOD_LDO2_PG BIT(0)
130 #define TPS65217_DEFPG_PGDLY_MASK 0x03
133 #define TPS65217_DEFDCDCX_DCDC_MASK 0x3F
140 #define TPS65217_DEFSLEW_SLEW_MASK 0x07
142 #define TPS65217_DEFLDO1_LDO1_MASK 0x0F
145 #define TPS65217_DEFLDO2_LDO2_MASK 0x3F
148 #define TPS65217_DEFLDO3_LDO3_MASK 0x1F
151 #define TPS65217_DEFLDO4_LDO4_MASK 0x1F
159 #define TPS65217_ENABLE_LDO2_EN BIT(0)
162 #define TPS65217_DEFUVLO_UVLO_MASK 0x03
164 #define TPS65217_SEQ1_DC1_SEQ_MASK 0xF0
165 #define TPS65217_SEQ1_DC2_SEQ_MASK 0x0F
167 #define TPS65217_SEQ2_DC3_SEQ_MASK 0xF0
168 #define TPS65217_SEQ2_LDO1_SEQ_MASK 0x0F
170 #define TPS65217_SEQ3_LDO2_SEQ_MASK 0xF0
171 #define TPS65217_SEQ3_LDO3_SEQ_MASK 0x0F
173 #define TPS65217_SEQ4_LDO4_SEQ_MASK 0xF0
175 #define TPS65217_SEQ5_DLY1_MASK 0xC0
176 #define TPS65217_SEQ5_DLY2_MASK 0x30
177 #define TPS65217_SEQ5_DLY3_MASK 0x0C
178 #define TPS65217_SEQ5_DLY4_MASK 0x03
180 #define TPS65217_SEQ6_DLY5_MASK 0xC0
181 #define TPS65217_SEQ6_DLY6_MASK 0x30
184 #define TPS65217_SEQ6_INSTDWN BIT(0)
186 #define TPS65217_MAX_REGISTER 0x1E
187 #define TPS65217_PROTECT_NONE 0
232 #define TPS65217_IRQ_USB 0