Lines Matching full:register
12 /* 8-bit shared register offsets macros */
13 #define RZ_MTU3_TSTRA 0x080 /* Timer start register A */
14 #define RZ_MTU3_TSTRB 0x880 /* Timer start register B */
16 /* 16-bit shared register offset macros */
17 #define RZ_MTU3_TDDRA 0x016 /* Timer dead time data register A */
18 #define RZ_MTU3_TDDRB 0x816 /* Timer dead time data register B */
19 #define RZ_MTU3_TCDRA 0x014 /* Timer cycle data register A */
20 #define RZ_MTU3_TCDRB 0x814 /* Timer cycle data register B */
21 #define RZ_MTU3_TCBRA 0x022 /* Timer cycle buffer register A */
22 #define RZ_MTU3_TCBRB 0x822 /* Timer cycle buffer register B */
31 /* 8-bit register offset macros of MTU3 channels except MTU5 */
32 #define RZ_MTU3_TIER 0 /* Timer interrupt register */
33 #define RZ_MTU3_NFCR 1 /* Noise filter control register */
34 #define RZ_MTU3_TSR 2 /* Timer status register */
35 #define RZ_MTU3_TCR 3 /* Timer control register */
36 #define RZ_MTU3_TCR2 4 /* Timer control register 2 */
38 /* Timer mode register 1 */
44 #define RZ_MTU3_TIOR 6 /* Timer I/O control register */
45 #define RZ_MTU3_TIORH 6 /* Timer I/O control register H */
46 #define RZ_MTU3_TIORL 7 /* Timer I/O control register L */
48 #define RZ_MTU3_TBTM 8 /* Timer buffer operation transfer mode register */
50 /* 8-bit MTU5 register offset macros */
51 #define RZ_MTU3_TSTR 2 /* MTU5 Timer start register */
52 #define RZ_MTU3_TCNTCMPCLR 3 /* MTU5 Timer compare match clear register */
53 #define RZ_MTU3_TCRU 4 /* Timer control register U */
54 #define RZ_MTU3_TCR2U 5 /* Timer control register 2U */
55 #define RZ_MTU3_TIORU 6 /* Timer I/O control register U */
56 #define RZ_MTU3_TCRV 7 /* Timer control register V */
57 #define RZ_MTU3_TCR2V 8 /* Timer control register 2V */
58 #define RZ_MTU3_TIORV 9 /* Timer I/O control register V */
59 #define RZ_MTU3_TCRW 10 /* Timer control register W */
60 #define RZ_MTU3_TCR2W 11 /* Timer control register 2W */
61 #define RZ_MTU3_TIORW 12 /* Timer I/O control register W */
63 /* 16-bit register offset macros of MTU3 channels except MTU5 */
65 #define RZ_MTU3_TGRA 1 /* Timer general register A */
66 #define RZ_MTU3_TGRB 2 /* Timer general register B */
67 #define RZ_MTU3_TGRC 3 /* Timer general register C */
68 #define RZ_MTU3_TGRD 4 /* Timer general register D */
69 #define RZ_MTU3_TGRE 5 /* Timer general register E */
70 #define RZ_MTU3_TGRF 6 /* Timer general register F */
72 #define RZ_MTU3_TADCR 7 /* control register */
73 #define RZ_MTU3_TADCORA 8 /* cycle set register A */
74 #define RZ_MTU3_TADCORB 9 /* cycle set register B */
75 #define RZ_MTU3_TADCOBRA 10 /* cycle set buffer register A */
76 #define RZ_MTU3_TADCOBRB 11 /* cycle set buffer register B */
78 /* 16-bit MTU5 register offset macros */
80 #define RZ_MTU3_TGRU 1 /* MTU5 Timer general register U */
82 #define RZ_MTU3_TGRV 3 /* MTU5 Timer general register V */
84 #define RZ_MTU3_TGRW 5 /* MTU5 Timer general register W */
86 /* 32-bit register offset */
88 #define RZ_MTU3_TGRALW 1 /* Timer longword general register A */
89 #define RZ_MTU3_TGRBLW 2 /* Timer longowrd general register B */
91 #define RZ_MTU3_TMDR3 0x191 /* MTU1 Timer Mode Register 3 */