1 /* SPDX-License-Identifier: GPL-2.0 */
12 /* 8-bit shared register offsets macros */
16 /* 16-bit shared register offset macros */
31 /* 8-bit register offset macros of MTU3 channels except MTU5 */
36 #define RZ_MTU3_TCR2	4 /* Timer control register 2 */
47 /* Only MTU3/4/6/7 have TBTM registers */
50 /* 8-bit MTU5 register offset macros */
53 #define RZ_MTU3_TCRU		4 /* Timer control register U */
63 /* 16-bit register offset macros of MTU3 channels except MTU5 */
68 #define RZ_MTU3_TGRD		4 /* Timer general register D */
78 /* 16-bit MTU5 register offset macros */
83 #define RZ_MTU3_TCNTW		4 /* MTU5 Timer counter W */
86 /* 32-bit register offset */
95 #define RZ_MTU3_TCR_CKEG	GENMASK(4, 3)
101 #define RZ_MTU3_TIOR_IOB			GENMASK(7, 4)
126  * struct rz_mtu3_channel - MTU3 channel private data
141  * struct rz_mtu3 - MTU3 core private data
154 static inline bool rz_mtu3_request_channel(struct rz_mtu3_channel *ch)  in rz_mtu3_request_channel()  argument
156 	mutex_lock(&ch->lock);  in rz_mtu3_request_channel()
157 	if (ch->is_busy) {  in rz_mtu3_request_channel()
158 		mutex_unlock(&ch->lock);  in rz_mtu3_request_channel()
162 	ch->is_busy = true;  in rz_mtu3_request_channel()
163 	mutex_unlock(&ch->lock);  in rz_mtu3_request_channel()
168 static inline void rz_mtu3_release_channel(struct rz_mtu3_channel *ch)  in rz_mtu3_release_channel()  argument
170 	mutex_lock(&ch->lock);  in rz_mtu3_release_channel()
171 	ch->is_busy = false;  in rz_mtu3_release_channel()
172 	mutex_unlock(&ch->lock);  in rz_mtu3_release_channel()
175 bool rz_mtu3_is_enabled(struct rz_mtu3_channel *ch);
176 void rz_mtu3_disable(struct rz_mtu3_channel *ch);
177 int rz_mtu3_enable(struct rz_mtu3_channel *ch);
179 u8 rz_mtu3_8bit_ch_read(struct rz_mtu3_channel *ch, u16 off);
180 u16 rz_mtu3_16bit_ch_read(struct rz_mtu3_channel *ch, u16 off);
181 u32 rz_mtu3_32bit_ch_read(struct rz_mtu3_channel *ch, u16 off);
182 u16 rz_mtu3_shared_reg_read(struct rz_mtu3_channel *ch, u16 off);
184 void rz_mtu3_8bit_ch_write(struct rz_mtu3_channel *ch, u16 off, u8 val);
185 void rz_mtu3_16bit_ch_write(struct rz_mtu3_channel *ch, u16 off, u16 val);
186 void rz_mtu3_32bit_ch_write(struct rz_mtu3_channel *ch, u16 off, u32 val);
187 void rz_mtu3_shared_reg_write(struct rz_mtu3_channel *ch, u16 off, u16 val);
188 void rz_mtu3_shared_reg_update_bit(struct rz_mtu3_channel *ch, u16 off,