Lines Matching +full:0 +full:x7f
10 #define MT6359_SWCID 0xa
11 #define MT6359_TOPSTATUS 0x2a
12 #define MT6359_TOP_RST_MISC 0x14c
13 #define MT6359_MISC_TOP_INT_CON0 0x188
14 #define MT6359_MISC_TOP_INT_STATUS0 0x194
15 #define MT6359_TOP_INT_STATUS0 0x19e
16 #define MT6359_SCK_TOP_INT_CON0 0x528
17 #define MT6359_SCK_TOP_INT_STATUS0 0x534
18 #define MT6359_EOSC_CALI_CON0 0x53a
19 #define MT6359_EOSC_CALI_CON1 0x53c
20 #define MT6359_RTC_MIX_CON0 0x53e
21 #define MT6359_RTC_MIX_CON1 0x540
22 #define MT6359_RTC_MIX_CON2 0x542
23 #define MT6359_RTC_DSN_ID 0x580
24 #define MT6359_RTC_DSN_REV0 0x582
25 #define MT6359_RTC_DBI 0x584
26 #define MT6359_RTC_DXI 0x586
27 #define MT6359_RTC_BBPU 0x588
28 #define MT6359_RTC_IRQ_STA 0x58a
29 #define MT6359_RTC_IRQ_EN 0x58c
30 #define MT6359_RTC_CII_EN 0x58e
31 #define MT6359_RTC_AL_MASK 0x590
32 #define MT6359_RTC_TC_SEC 0x592
33 #define MT6359_RTC_TC_MIN 0x594
34 #define MT6359_RTC_TC_HOU 0x596
35 #define MT6359_RTC_TC_DOM 0x598
36 #define MT6359_RTC_TC_DOW 0x59a
37 #define MT6359_RTC_TC_MTH 0x59c
38 #define MT6359_RTC_TC_YEA 0x59e
39 #define MT6359_RTC_AL_SEC 0x5a0
40 #define MT6359_RTC_AL_MIN 0x5a2
41 #define MT6359_RTC_AL_HOU 0x5a4
42 #define MT6359_RTC_AL_DOM 0x5a6
43 #define MT6359_RTC_AL_DOW 0x5a8
44 #define MT6359_RTC_AL_MTH 0x5aa
45 #define MT6359_RTC_AL_YEA 0x5ac
46 #define MT6359_RTC_OSC32CON 0x5ae
47 #define MT6359_RTC_POWERKEY1 0x5b0
48 #define MT6359_RTC_POWERKEY2 0x5b2
49 #define MT6359_RTC_PDN1 0x5b4
50 #define MT6359_RTC_PDN2 0x5b6
51 #define MT6359_RTC_SPAR0 0x5b8
52 #define MT6359_RTC_SPAR1 0x5ba
53 #define MT6359_RTC_PROT 0x5bc
54 #define MT6359_RTC_DIFF 0x5be
55 #define MT6359_RTC_CALI 0x5c0
56 #define MT6359_RTC_WRTGR 0x5c2
57 #define MT6359_RTC_CON 0x5c4
58 #define MT6359_RTC_SEC_CTRL 0x5c6
59 #define MT6359_RTC_INT_CNT 0x5c8
60 #define MT6359_RTC_SEC_DAT0 0x5ca
61 #define MT6359_RTC_SEC_DAT1 0x5cc
62 #define MT6359_RTC_SEC_DAT2 0x5ce
63 #define MT6359_RTC_SEC_DSN_ID 0x600
64 #define MT6359_RTC_SEC_DSN_REV0 0x602
65 #define MT6359_RTC_SEC_DBI 0x604
66 #define MT6359_RTC_SEC_DXI 0x606
67 #define MT6359_RTC_TC_SEC_SEC 0x608
68 #define MT6359_RTC_TC_MIN_SEC 0x60a
69 #define MT6359_RTC_TC_HOU_SEC 0x60c
70 #define MT6359_RTC_TC_DOM_SEC 0x60e
71 #define MT6359_RTC_TC_DOW_SEC 0x610
72 #define MT6359_RTC_TC_MTH_SEC 0x612
73 #define MT6359_RTC_TC_YEA_SEC 0x614
74 #define MT6359_RTC_SEC_CK_PDN 0x616
75 #define MT6359_RTC_SEC_WRTGR 0x618
76 #define MT6359_PSC_TOP_INT_CON0 0x910
77 #define MT6359_PSC_TOP_INT_STATUS0 0x91c
78 #define MT6359_BM_TOP_INT_CON0 0xc32
79 #define MT6359_BM_TOP_INT_CON1 0xc38
80 #define MT6359_BM_TOP_INT_STATUS0 0xc4a
81 #define MT6359_BM_TOP_INT_STATUS1 0xc4c
82 #define MT6359_HK_TOP_INT_CON0 0xf92
83 #define MT6359_HK_TOP_INT_STATUS0 0xf9e
84 #define MT6359_BUCK_TOP_INT_CON0 0x1418
85 #define MT6359_BUCK_TOP_INT_STATUS0 0x1424
86 #define MT6359_BUCK_VPU_CON0 0x1488
87 #define MT6359_BUCK_VPU_DBG0 0x14a6
88 #define MT6359_BUCK_VPU_DBG1 0x14a8
89 #define MT6359_BUCK_VPU_ELR0 0x14ac
90 #define MT6359_BUCK_VCORE_CON0 0x1508
91 #define MT6359_BUCK_VCORE_DBG0 0x1526
92 #define MT6359_BUCK_VCORE_DBG1 0x1528
93 #define MT6359_BUCK_VCORE_SSHUB_CON0 0x152a
94 #define MT6359_BUCK_VCORE_ELR0 0x1534
95 #define MT6359_BUCK_VGPU11_CON0 0x1588
96 #define MT6359_BUCK_VGPU11_DBG0 0x15a6
97 #define MT6359_BUCK_VGPU11_DBG1 0x15a8
98 #define MT6359_BUCK_VGPU11_ELR0 0x15ac
99 #define MT6359_BUCK_VMODEM_CON0 0x1688
100 #define MT6359_BUCK_VMODEM_DBG0 0x16a6
101 #define MT6359_BUCK_VMODEM_DBG1 0x16a8
102 #define MT6359_BUCK_VMODEM_ELR0 0x16ae
103 #define MT6359_BUCK_VPROC1_CON0 0x1708
104 #define MT6359_BUCK_VPROC1_DBG0 0x1726
105 #define MT6359_BUCK_VPROC1_DBG1 0x1728
106 #define MT6359_BUCK_VPROC1_ELR0 0x172e
107 #define MT6359_BUCK_VPROC2_CON0 0x1788
108 #define MT6359_BUCK_VPROC2_DBG0 0x17a6
109 #define MT6359_BUCK_VPROC2_DBG1 0x17a8
110 #define MT6359_BUCK_VPROC2_ELR0 0x17b2
111 #define MT6359_BUCK_VS1_CON0 0x1808
112 #define MT6359_BUCK_VS1_DBG0 0x1826
113 #define MT6359_BUCK_VS1_DBG1 0x1828
114 #define MT6359_BUCK_VS1_ELR0 0x1834
115 #define MT6359_BUCK_VS2_CON0 0x1888
116 #define MT6359_BUCK_VS2_DBG0 0x18a6
117 #define MT6359_BUCK_VS2_DBG1 0x18a8
118 #define MT6359_BUCK_VS2_ELR0 0x18b4
119 #define MT6359_BUCK_VPA_CON0 0x1908
120 #define MT6359_BUCK_VPA_CON1 0x190e
121 #define MT6359_BUCK_VPA_CFG0 0x1910
122 #define MT6359_BUCK_VPA_CFG1 0x1912
123 #define MT6359_BUCK_VPA_DBG0 0x1914
124 #define MT6359_BUCK_VPA_DBG1 0x1916
125 #define MT6359_VGPUVCORE_ANA_CON2 0x198e
126 #define MT6359_VGPUVCORE_ANA_CON13 0x19a4
127 #define MT6359_VPROC1_ANA_CON3 0x19b2
128 #define MT6359_VPROC2_ANA_CON3 0x1a0e
129 #define MT6359_VMODEM_ANA_CON3 0x1a1a
130 #define MT6359_VPU_ANA_CON3 0x1a26
131 #define MT6359_VS1_ANA_CON0 0x1a2c
132 #define MT6359_VS2_ANA_CON0 0x1a34
133 #define MT6359_VPA_ANA_CON0 0x1a3c
134 #define MT6359_LDO_TOP_INT_CON0 0x1b14
135 #define MT6359_LDO_TOP_INT_CON1 0x1b1a
136 #define MT6359_LDO_TOP_INT_STATUS0 0x1b28
137 #define MT6359_LDO_TOP_INT_STATUS1 0x1b2a
138 #define MT6359_LDO_VSRAM_PROC1_ELR 0x1b40
139 #define MT6359_LDO_VSRAM_PROC2_ELR 0x1b42
140 #define MT6359_LDO_VSRAM_OTHERS_ELR 0x1b44
141 #define MT6359_LDO_VSRAM_MD_ELR 0x1b46
142 #define MT6359_LDO_VFE28_CON0 0x1b88
143 #define MT6359_LDO_VFE28_MON 0x1b8a
144 #define MT6359_LDO_VXO22_CON0 0x1b98
145 #define MT6359_LDO_VXO22_MON 0x1b9a
146 #define MT6359_LDO_VRF18_CON0 0x1ba8
147 #define MT6359_LDO_VRF18_MON 0x1baa
148 #define MT6359_LDO_VRF12_CON0 0x1bb8
149 #define MT6359_LDO_VRF12_MON 0x1bba
150 #define MT6359_LDO_VEFUSE_CON0 0x1bc8
151 #define MT6359_LDO_VEFUSE_MON 0x1bca
152 #define MT6359_LDO_VCN33_1_CON0 0x1bd8
153 #define MT6359_LDO_VCN33_1_MON 0x1bda
154 #define MT6359_LDO_VCN33_1_MULTI_SW 0x1be8
155 #define MT6359_LDO_VCN33_2_CON0 0x1c08
156 #define MT6359_LDO_VCN33_2_MON 0x1c0a
157 #define MT6359_LDO_VCN33_2_MULTI_SW 0x1c18
158 #define MT6359_LDO_VCN13_CON0 0x1c1a
159 #define MT6359_LDO_VCN13_MON 0x1c1c
160 #define MT6359_LDO_VCN18_CON0 0x1c2a
161 #define MT6359_LDO_VCN18_MON 0x1c2c
162 #define MT6359_LDO_VA09_CON0 0x1c3a
163 #define MT6359_LDO_VA09_MON 0x1c3c
164 #define MT6359_LDO_VCAMIO_CON0 0x1c4a
165 #define MT6359_LDO_VCAMIO_MON 0x1c4c
166 #define MT6359_LDO_VA12_CON0 0x1c5a
167 #define MT6359_LDO_VA12_MON 0x1c5c
168 #define MT6359_LDO_VAUX18_CON0 0x1c88
169 #define MT6359_LDO_VAUX18_MON 0x1c8a
170 #define MT6359_LDO_VAUD18_CON0 0x1c98
171 #define MT6359_LDO_VAUD18_MON 0x1c9a
172 #define MT6359_LDO_VIO18_CON0 0x1ca8
173 #define MT6359_LDO_VIO18_MON 0x1caa
174 #define MT6359_LDO_VEMC_CON0 0x1cb8
175 #define MT6359_LDO_VEMC_MON 0x1cba
176 #define MT6359_LDO_VSIM1_CON0 0x1cc8
177 #define MT6359_LDO_VSIM1_MON 0x1cca
178 #define MT6359_LDO_VSIM2_CON0 0x1cd8
179 #define MT6359_LDO_VSIM2_MON 0x1cda
180 #define MT6359_LDO_VUSB_CON0 0x1d08
181 #define MT6359_LDO_VUSB_MON 0x1d0a
182 #define MT6359_LDO_VUSB_MULTI_SW 0x1d18
183 #define MT6359_LDO_VRFCK_CON0 0x1d1a
184 #define MT6359_LDO_VRFCK_MON 0x1d1c
185 #define MT6359_LDO_VBBCK_CON0 0x1d2a
186 #define MT6359_LDO_VBBCK_MON 0x1d2c
187 #define MT6359_LDO_VBIF28_CON0 0x1d3a
188 #define MT6359_LDO_VBIF28_MON 0x1d3c
189 #define MT6359_LDO_VIBR_CON0 0x1d4a
190 #define MT6359_LDO_VIBR_MON 0x1d4c
191 #define MT6359_LDO_VIO28_CON0 0x1d5a
192 #define MT6359_LDO_VIO28_MON 0x1d5c
193 #define MT6359_LDO_VM18_CON0 0x1d88
194 #define MT6359_LDO_VM18_MON 0x1d8a
195 #define MT6359_LDO_VUFS_CON0 0x1d98
196 #define MT6359_LDO_VUFS_MON 0x1d9a
197 #define MT6359_LDO_VSRAM_PROC1_CON0 0x1e88
198 #define MT6359_LDO_VSRAM_PROC1_MON 0x1e8a
199 #define MT6359_LDO_VSRAM_PROC1_VOSEL1 0x1e8e
200 #define MT6359_LDO_VSRAM_PROC2_CON0 0x1ea6
201 #define MT6359_LDO_VSRAM_PROC2_MON 0x1ea8
202 #define MT6359_LDO_VSRAM_PROC2_VOSEL1 0x1eac
203 #define MT6359_LDO_VSRAM_OTHERS_CON0 0x1f08
204 #define MT6359_LDO_VSRAM_OTHERS_MON 0x1f0a
205 #define MT6359_LDO_VSRAM_OTHERS_VOSEL1 0x1f0e
206 #define MT6359_LDO_VSRAM_OTHERS_SSHUB 0x1f26
207 #define MT6359_LDO_VSRAM_MD_CON0 0x1f2c
208 #define MT6359_LDO_VSRAM_MD_MON 0x1f2e
209 #define MT6359_LDO_VSRAM_MD_VOSEL1 0x1f32
210 #define MT6359_VFE28_ANA_CON0 0x1f88
211 #define MT6359_VAUX18_ANA_CON0 0x1f8c
212 #define MT6359_VUSB_ANA_CON0 0x1f90
213 #define MT6359_VBIF28_ANA_CON0 0x1f94
214 #define MT6359_VCN33_1_ANA_CON0 0x1f98
215 #define MT6359_VCN33_2_ANA_CON0 0x1f9c
216 #define MT6359_VEMC_ANA_CON0 0x1fa0
217 #define MT6359_VSIM1_ANA_CON0 0x1fa4
218 #define MT6359_VSIM2_ANA_CON0 0x1fa8
219 #define MT6359_VIO28_ANA_CON0 0x1fac
220 #define MT6359_VIBR_ANA_CON0 0x1fb0
221 #define MT6359_VRF18_ANA_CON0 0x2008
222 #define MT6359_VEFUSE_ANA_CON0 0x200c
223 #define MT6359_VCN18_ANA_CON0 0x2010
224 #define MT6359_VCAMIO_ANA_CON0 0x2014
225 #define MT6359_VAUD18_ANA_CON0 0x2018
226 #define MT6359_VIO18_ANA_CON0 0x201c
227 #define MT6359_VM18_ANA_CON0 0x2020
228 #define MT6359_VUFS_ANA_CON0 0x2024
229 #define MT6359_VRF12_ANA_CON0 0x202a
230 #define MT6359_VCN13_ANA_CON0 0x202e
231 #define MT6359_VA09_ANA_CON0 0x2032
232 #define MT6359_VA12_ANA_CON0 0x2036
233 #define MT6359_VXO22_ANA_CON0 0x2088
234 #define MT6359_VRFCK_ANA_CON0 0x208c
235 #define MT6359_VBBCK_ANA_CON0 0x2094
236 #define MT6359_AUD_TOP_INT_CON0 0x2328
237 #define MT6359_AUD_TOP_INT_STATUS0 0x2334
243 #define MT6359_DA_VPU_VOSEL_MASK 0x7F
244 #define MT6359_DA_VPU_VOSEL_SHIFT 0
247 #define MT6359_RG_BUCK_VPU_VOSEL_MASK 0x7F
248 #define MT6359_RG_BUCK_VPU_VOSEL_SHIFT 0
253 #define MT6359_DA_VCORE_VOSEL_MASK 0x7F
254 #define MT6359_DA_VCORE_VOSEL_SHIFT 0
258 #define MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_MASK 0x7F
261 #define MT6359_RG_BUCK_VCORE_VOSEL_MASK 0x7F
262 #define MT6359_RG_BUCK_VCORE_VOSEL_SHIFT 0
267 #define MT6359_DA_VGPU11_VOSEL_MASK 0x7F
268 #define MT6359_DA_VGPU11_VOSEL_SHIFT 0
271 #define MT6359_RG_BUCK_VGPU11_VOSEL_MASK 0x7F
272 #define MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT 0
277 #define MT6359_DA_VMODEM_VOSEL_MASK 0x7F
278 #define MT6359_DA_VMODEM_VOSEL_SHIFT 0
281 #define MT6359_RG_BUCK_VMODEM_VOSEL_MASK 0x7F
282 #define MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT 0
287 #define MT6359_DA_VPROC1_VOSEL_MASK 0x7F
288 #define MT6359_DA_VPROC1_VOSEL_SHIFT 0
291 #define MT6359_RG_BUCK_VPROC1_VOSEL_MASK 0x7F
292 #define MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT 0
297 #define MT6359_DA_VPROC2_VOSEL_MASK 0x7F
298 #define MT6359_DA_VPROC2_VOSEL_SHIFT 0
301 #define MT6359_RG_BUCK_VPROC2_VOSEL_MASK 0x7F
302 #define MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT 0
307 #define MT6359_DA_VS1_VOSEL_MASK 0x7F
308 #define MT6359_DA_VS1_VOSEL_SHIFT 0
311 #define MT6359_RG_BUCK_VS1_VOSEL_MASK 0x7F
312 #define MT6359_RG_BUCK_VS1_VOSEL_SHIFT 0
317 #define MT6359_DA_VS2_VOSEL_MASK 0x7F
318 #define MT6359_DA_VS2_VOSEL_SHIFT 0
321 #define MT6359_RG_BUCK_VS2_VOSEL_MASK 0x7F
322 #define MT6359_RG_BUCK_VS2_VOSEL_SHIFT 0
327 #define MT6359_RG_BUCK_VPA_VOSEL_MASK 0x3F
328 #define MT6359_RG_BUCK_VPA_VOSEL_SHIFT 0
330 #define MT6359_DA_VPA_VOSEL_MASK 0x3F
331 #define MT6359_DA_VPA_VOSEL_SHIFT 0
352 #define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK 0x7F
353 #define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT 0
355 #define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK 0x7F
356 #define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT 0
358 #define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK 0x7F
359 #define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT 0
361 #define MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK 0x7F
362 #define MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT 0
366 #define MT6359_RG_LDO_VXO22_EN_SHIFT 0
369 #define MT6359_RG_LDO_VRF18_EN_SHIFT 0
372 #define MT6359_RG_LDO_VRF12_EN_SHIFT 0
375 #define MT6359_RG_LDO_VEFUSE_EN_SHIFT 0
378 #define MT6359_RG_LDO_VCN33_1_EN_0_MASK 0x1
379 #define MT6359_RG_LDO_VCN33_1_EN_0_SHIFT 0
384 #define MT6359_RG_LDO_VCN33_2_EN_0_SHIFT 0
387 #define MT6359_RG_LDO_VCN33_2_EN_1_MASK 0x1
390 #define MT6359_RG_LDO_VCN13_EN_SHIFT 0
395 #define MT6359_RG_LDO_VA09_EN_SHIFT 0
398 #define MT6359_RG_LDO_VCAMIO_EN_SHIFT 0
401 #define MT6359_RG_LDO_VA12_EN_SHIFT 0
408 #define MT6359_RG_LDO_VIO18_EN_SHIFT 0
411 #define MT6359_RG_LDO_VEMC_EN_SHIFT 0
414 #define MT6359_RG_LDO_VSIM1_EN_SHIFT 0
417 #define MT6359_RG_LDO_VSIM2_EN_SHIFT 0
420 #define MT6359_RG_LDO_VUSB_EN_0_MASK 0x1
421 #define MT6359_RG_LDO_VUSB_EN_0_SHIFT 0
424 #define MT6359_RG_LDO_VUSB_EN_1_MASK 0x1
427 #define MT6359_RG_LDO_VRFCK_EN_SHIFT 0
430 #define MT6359_RG_LDO_VBBCK_EN_SHIFT 0
435 #define MT6359_RG_LDO_VIBR_EN_SHIFT 0
438 #define MT6359_RG_LDO_VIO28_EN_SHIFT 0
441 #define MT6359_RG_LDO_VM18_EN_SHIFT 0
444 #define MT6359_RG_LDO_VUFS_EN_SHIFT 0
449 #define MT6359_DA_VSRAM_PROC1_VOSEL_MASK 0x7F
454 #define MT6359_DA_VSRAM_PROC2_VOSEL_MASK 0x7F
459 #define MT6359_DA_VSRAM_OTHERS_VOSEL_MASK 0x7F
463 #define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK 0x7F
468 #define MT6359_DA_VSRAM_MD_VOSEL_MASK 0x7F
471 #define MT6359_RG_VCN33_1_VOSEL_MASK 0xF
474 #define MT6359_RG_VCN33_2_VOSEL_MASK 0xF
477 #define MT6359_RG_VEMC_VOSEL_MASK 0xF
480 #define MT6359_RG_VSIM1_VOSEL_MASK 0xF
483 #define MT6359_RG_VSIM2_VOSEL_MASK 0xF
486 #define MT6359_RG_VIO28_VOSEL_MASK 0xF
489 #define MT6359_RG_VIBR_VOSEL_MASK 0xF
492 #define MT6359_RG_VRF18_VOSEL_MASK 0xF
495 #define MT6359_RG_VEFUSE_VOSEL_MASK 0xF
498 #define MT6359_RG_VCAMIO_VOSEL_MASK 0xF
501 #define MT6359_RG_VIO18_VOSEL_MASK 0xF
504 #define MT6359_RG_VM18_VOSEL_MASK 0xF
507 #define MT6359_RG_VUFS_VOSEL_MASK 0xF
510 #define MT6359_RG_VRF12_VOSEL_MASK 0xF
513 #define MT6359_RG_VCN13_VOSEL_MASK 0xF
516 #define MT6359_RG_VA09_VOSEL_MASK 0xF
519 #define MT6359_RG_VA12_VOSEL_MASK 0xF
522 #define MT6359_RG_VXO22_VOSEL_MASK 0xF
525 #define MT6359_RG_VRFCK_VOSEL_MASK 0xF
528 #define MT6359_RG_VBBCK_VOSEL_MASK 0xF