Lines Matching +full:0 +full:xf0
16 #define LP873X 0x00
19 #define LP873X_REG_DEV_REV 0X00
20 #define LP873X_REG_OTP_REV 0X01
21 #define LP873X_REG_BUCK0_CTRL_1 0X02
22 #define LP873X_REG_BUCK0_CTRL_2 0X03
23 #define LP873X_REG_BUCK1_CTRL_1 0X04
24 #define LP873X_REG_BUCK1_CTRL_2 0X05
25 #define LP873X_REG_BUCK0_VOUT 0X06
26 #define LP873X_REG_BUCK1_VOUT 0X07
27 #define LP873X_REG_LDO0_CTRL 0X08
28 #define LP873X_REG_LDO1_CTRL 0X09
29 #define LP873X_REG_LDO0_VOUT 0X0A
30 #define LP873X_REG_LDO1_VOUT 0X0B
31 #define LP873X_REG_BUCK0_DELAY 0X0C
32 #define LP873X_REG_BUCK1_DELAY 0X0D
33 #define LP873X_REG_LDO0_DELAY 0X0E
34 #define LP873X_REG_LDO1_DELAY 0X0F
35 #define LP873X_REG_GPO_DELAY 0X10
36 #define LP873X_REG_GPO2_DELAY 0X11
37 #define LP873X_REG_GPO_CTRL 0X12
38 #define LP873X_REG_CONFIG 0X13
39 #define LP873X_REG_PLL_CTRL 0X14
40 #define LP873X_REG_PGOOD_CTRL1 0X15
41 #define LP873X_REG_PGOOD_CTRL2 0X16
42 #define LP873X_REG_PG_FAULT 0X17
43 #define LP873X_REG_RESET 0X18
44 #define LP873X_REG_INT_TOP_1 0X19
45 #define LP873X_REG_INT_TOP_2 0X1A
46 #define LP873X_REG_INT_BUCK 0X1B
47 #define LP873X_REG_INT_LDO 0X1C
48 #define LP873X_REG_TOP_STAT 0X1D
49 #define LP873X_REG_BUCK_STAT 0X1E
50 #define LP873X_REG_LDO_STAT 0x1F
51 #define LP873X_REG_TOP_MASK_1 0x20
52 #define LP873X_REG_TOP_MASK_2 0x21
53 #define LP873X_REG_BUCK_MASK 0x22
54 #define LP873X_REG_LDO_MASK 0x23
55 #define LP873X_REG_SEL_I_LOAD 0x24
56 #define LP873X_REG_I_LOAD_2 0x25
57 #define LP873X_REG_I_LOAD_1 0x26
62 #define LP873X_DEV_REV_DEV_ID 0xC0
63 #define LP873X_DEV_REV_ALL_LAYER 0x30
64 #define LP873X_DEV_REV_METAL_LAYER 0x0F
66 #define LP873X_OTP_REV_OTP_ID 0xFF
71 #define LP873X_BUCK0_CTRL_1_BUCK0_EN BIT(0)
73 #define LP873X_BUCK0_CTRL_2_BUCK0_ILIM 0x38
74 #define LP873X_BUCK0_CTRL_2_BUCK0_SLEW_RATE 0x07
79 #define LP873X_BUCK1_CTRL_1_BUCK1_EN BIT(0)
81 #define LP873X_BUCK1_CTRL_2_BUCK1_ILIM 0x38
82 #define LP873X_BUCK1_CTRL_2_BUCK1_SLEW_RATE 0x07
84 #define LP873X_BUCK0_VOUT_BUCK0_VSET 0xFF
86 #define LP873X_BUCK1_VOUT_BUCK1_VSET 0xFF
90 #define LP873X_LDO0_CTRL_LDO0_EN BIT(0)
94 #define LP873X_LDO1_CTRL_LDO1_EN BIT(0)
96 #define LP873X_LDO0_VOUT_LDO0_VSET 0x1F
98 #define LP873X_LDO1_VOUT_LDO1_VSET 0x1F
100 #define LP873X_BUCK0_DELAY_BUCK0_SD_DELAY 0xF0
101 #define LP873X_BUCK0_DELAY_BUCK0_SU_DELAY 0x0F
103 #define LP873X_BUCK1_DELAY_BUCK1_SD_DELAY 0xF0
104 #define LP873X_BUCK1_DELAY_BUCK1_SU_DELAY 0x0F
106 #define LP873X_LDO0_DELAY_LDO0_SD_DELAY 0xF0
107 #define LP873X_LDO0_DELAY_LDO0_SU_DELAY 0x0F
109 #define LP873X_LDO1_DELAY_LDO1_SD_DELAY 0xF0
110 #define LP873X_LDO1_DELAY_LDO1_SU_DELAY 0x0F
112 #define LP873X_GPO_DELAY_GPO_SD_DELAY 0xF0
113 #define LP873X_GPO_DELAY_GPO_SU_DELAY 0x0F
115 #define LP873X_GPO2_DELAY_GPO2_SD_DELAY 0xF0
116 #define LP873X_GPO2_DELAY_GPO2_SU_DELAY 0x0F
123 #define LP873X_GPO_CTRL_GPO_EN BIT(0)
131 #define LP873X_EN_SPREAD_SPEC BIT(0)
134 #define LP873X_EXT_CLK_FREQ 0x1F
143 #define LP873X_PGOOD_CTRL1_PGOOD_EN_PGOOD_BUCK0 BIT(0)
147 #define LP873X_PGOOD_CTRL2_PGOOD_MODE BIT(0)
152 #define LP873X_PG_FAULT_PG_FAULT_BUCK0 BIT(0)
154 #define LP873X_RESET_SW_RESET BIT(0)
163 #define LP873X_INT_TOP_1_I_MEAS_INT BIT(0)
165 #define LP873X_INT_TOP_2_RESET_REG_INT BIT(0)
172 #define LP873X_INT_BUCK_BUCK0_ILIM_INT BIT(0)
179 #define LP873X_INT_LDO_LDO0_ILIM_INT BIT(0)
192 #define LP873X_BUCK_STAT_BUCK0_ILIM_STAT BIT(0)
199 #define LP873X_LDO_STAT_LDO0_ILIM_STAT BIT(0)
204 #define LP873X_TOP_MASK_1_I_MEAS_MASK BIT(0)
206 #define LP873X_TOP_MASK_2_RESET_REG_MASK BIT(0)
213 #define LP873X_BUCK_MASK_BUCK0_ILIM_MASK BIT(0)
220 #define LP873X_LDO_MASK_LDO0_ILIM_MASK BIT(0)
222 #define LP873X_SEL_I_LOAD_CURRENT_BUCK_SELECT BIT(0)
224 #define LP873X_I_LOAD_2_BUCK_LOAD_CURRENT BIT(0)
226 #define LP873X_I_LOAD_1_BUCK_LOAD_CURRENT 0xFF