Lines Matching +full:enable +full:- +full:ssc

1 /* SPDX-License-Identifier: GPL-2.0-only */
10 #include <linux/clk-provider.h>
14  * struct clk_omap_reg - OMAP register declaration
26  * struct dpll_data - DPLL registers and integration data
40  * @max_multiplier: maximum valid non-bypass multiplier value (actual)
42  * @min_divider: minimum valid non-bypass divider value (actual)
43  * @max_divider: maximum valid non-bypass divider value (actual)
53  * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
55  * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
58  * @ssc_deltam_reg: register containing the DPLL SSC frequency spreading
59  * @ssc_modfreq_reg: register containing the DPLL SSC modulation frequency
62  * @ssc_enable_mask: mask of the DPLL SSC enable bit in @control_reg
63  * @ssc_downspread_mask: mask of the DPLL SSC low frequency only bit in
65  * @ssc_modfreq: the DPLL SSC frequency modulation in kHz
66  * @ssc_deltam: the DPLL SSC frequency spreading in permille (10th of percent)
67  * @ssc_downspread: require the only low frequency spread of the DPLL in SSC
72  * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
79  * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
80  * @last_rounded_n) should be separated from the runtime-fixed fields
81  * and placed into a different structure, so that the runtime-fixed data
82  * can be placed into read-only space.
133  * struct clk_hw_omap_ops - OMAP clk ops
136  *		    basically converts CM_ICLKEN* <-> CM_FCLKEN*
152  * struct clk_hw_omap - OMAP struct clk
154  * @enable_reg: register to write to enable the clock (see @enable_bit)
155  * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
189  *     clock is put to no-idle mode.
191  * INVERT_ENABLE: By default, clock enable bit behavior is '1' enable, '0'
192  *     disable. This inverts the behavior making '0' enable and '1' disable.
196  *     should be used.  This is a temporary solution - a better approach
197  *     would be to associate clock type-specific data with the clock,
200 #define ENABLE_REG_32BIT	(1 << 0)	/* Use 32-bit access */
203 #define ENABLE_ON_INIT		(1 << 3)	/* Enable upon framework init */
207 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
228  * struct ti_clk_ll_ops - low-level ops for clocks
231  * @clk_rmw: pointer to register read-modify-write function
232  * @clkdm_clk_enable: pointer to clockdomain enable function
238  * Low-level ops are generally used by the basic clock types (clk-gate,
239  * clk-mux, clk-divider etc.) to provide support for various low-level
241  * by board code. Low-level ops also contain some other platform specific
330 static inline int omap3430_clk_legacy_init(void) { return -ENXIO; }  in omap3430_clk_legacy_init()
331 static inline int omap3430es1_clk_legacy_init(void) { return -ENXIO; }  in omap3430es1_clk_legacy_init()
332 static inline int omap36xx_clk_legacy_init(void) { return -ENXIO; }  in omap36xx_clk_legacy_init()
333 static inline int am35xx_clk_legacy_init(void) { return -ENXIO; }  in am35xx_clk_legacy_init()