1 /* SPDX-License-Identifier: GPL-2.0 */
3  *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4  *  Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14  * top-level framework.  custom flags for dealing with hardware specifics
19 #define CLK_SET_RATE_GATE	BIT(0) /* must be gated across rate change */
20 #define CLK_SET_PARENT_GATE	BIT(1) /* must be gated across re-parent */
21 #define CLK_SET_RATE_PARENT	BIT(2) /* propagate rate change up one level */
25 #define CLK_GET_RATE_NOCACHE	BIT(6) /* do not use the cached clk rate */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
29 #define CLK_SET_RATE_UNGATE	BIT(10) /* clock needs to run to set rate */
31 /* parents need enable during gate/ungate, set rate and re-parent */
42  * struct clk_rate_request - Structure encoding the clk constraints that
48  * @rate:		Requested clock rate. This field will be adjusted by
50  * @min_rate:		Minimum rate imposed by clk users.
51  * @max_rate:		Maximum rate imposed by clk users.
52  * @best_parent_rate:	The best parent rate a parent can provide to fulfill the
60 	unsigned long rate;  member
69 			      unsigned long rate);
77  * struct clk_duty - Struture encoding the duty cycle ratio of a clock
88  * struct clk_ops -  Callback operations for hardware clocks; these are to
132  * @recalc_rate	Recalculate the rate of this clock, by querying hardware. The
133  *		parent rate is an input parameter.  It is up to the caller to
135  *		driver cannot figure out a rate for this clock, it must return
136  *		0. Returns the calculated rate. Optional, but recommended - if
137  *		this op is not set then clock rate will be initialized to 0.
139  * @round_rate:	Given a target rate as input, returns the closest rate actually
140  *		supported by the clock. The parent rate is an input/output
143  * @determine_rate: Given a target rate as input, returns the closest rate
145  *		that should be used to provide the clock rate.
152  *		Returns 0 on success, -EERROR otherwise.
164  * @set_rate:	Change the rate of this clock. The requested rate is specified
166  *		of .round_rate call.  The third argument gives the parent rate
168  *		Returns 0 on success, -EERROR otherwise.
170  * @set_rate_and_parent: Change the rate and the parent of this clock. The
171  *		requested rate is specified by the second argument, which
173  *		third argument gives the parent rate which is likely helpful
177  *		for clocks that can tolerate switching the rate and the parent
179  *		Returns 0 on success, -EERROR otherwise.
184  *		Returns the calculated accuracy.  Optional - if	this op is not
189  *		Returned values are 0-359 degrees on success, negative
194  *		0-359. Return 0 on success, otherwise -EERROR.
203  *              and >= numerator) Return 0 on success, otherwise -EERROR.
205  * @init:	Perform platform-specific initialization magic.
211  *		such as rate or parents.
212  *		Returns 0 on success, -EERROR otherwise.
216  * @debug_init:	Set up type-specific debugfs entries for this clock.  This
220  *		prepare_lock held.  Returns 0 on success, -EERROR otherwise.
247 	long		(*round_rate)(struct clk_hw *hw, unsigned long rate,
253 	int		(*set_rate)(struct clk_hw *hw, unsigned long rate,
256 				    unsigned long rate,
272  * struct clk_parent_data - clk parent information
286  * struct clk_init_data - holds init data that's common to all clocks and is
297  * @flags: framework-level hints and quirks
311  * struct clk_hw - handle for traversing from a struct clk to its corresponding
312  * hardware-specific structure.  struct clk_hw should be declared within struct
319  * @clk: pointer to the per-user struct clk instance that can be used to call
342  * struct clk_fixed_rate - fixed-rate clock
343  * @hw:		handle between common and hardware-specific interfaces
349  * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
372  * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
377  * @flags: framework-specific flags
378  * @fixed_rate: non-adjustable clock rate
385  * devm_clk_hw_register_fixed_rate - register fixed-rate clock with the clock
390  * @flags: framework-specific flags
391  * @fixed_rate: non-adjustable clock rate
397  * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
402  * @flags: framework-specific flags
403  * @fixed_rate: non-adjustable clock rate
410  * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
415  * @flags: framework-specific flags
416  * @fixed_rate: non-adjustable clock rate
424  * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
429  * @flags: framework-specific flags
430  * @fixed_rate: non-adjustable clock rate
431  * @fixed_accuracy: non-adjustable clock accuracy
440  * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
445  * @flags: framework-specific flags
446  * @fixed_rate: non-adjustable clock rate
447  * @fixed_accuracy: non-adjustable clock accuracy
455  * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
460  * @flags: framework-specific flags
461  * @fixed_rate: non-adjustable clock rate
462  * @fixed_accuracy: non-adjustable clock accuracy
470  * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with
475  * @flags: framework-specific flags
476  * @fixed_rate: non-adjustable clock rate
490  * struct clk_gate - gating clock
492  * @hw:		handle between common and hardware-specific interfaces
495  * @flags:	hardware-specific flags
501  * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
504  * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
505  *	of this register, and mask of gate bits are in higher 16-bit of this
506  *	register.  While setting the gate bits, higher 16-bit should also be
508  * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
546  * clk_hw_register_gate - register a gate clock with the clock framework
550  * @flags: framework-specific flags for this clock
553  * @clk_gate_flags: gate-specific flags for this clock
562  * clk_hw_register_gate_parent_hw - register a gate clock with the clock
567  * @flags: framework-specific flags for this clock
570  * @clk_gate_flags: gate-specific flags for this clock
579  * clk_hw_register_gate_parent_data - register a gate clock with the clock
584  * @flags: framework-specific flags for this clock
587  * @clk_gate_flags: gate-specific flags for this clock
596  * devm_clk_hw_register_gate - register a gate clock with the clock framework
600  * @flags: framework-specific flags for this clock
603  * @clk_gate_flags: gate-specific flags for this clock
612  * devm_clk_hw_register_gate_parent_data - register a gate clock with the
617  * @flags: framework-specific flags for this clock
620  * @clk_gate_flags: gate-specific flags for this clock
640  * struct clk_divider - adjustable divider clock
642  * @hw:		handle between common and hardware-specific interfaces
653  * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
657  * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
659  * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors.  For dividers which have
664  * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
665  *	of this register, and mask of divider bits are in higher 16-bit of this
666  *	register.  While setting the divider bits, higher 16-bit should also be
668  * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
670  * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
672  * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
675  * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
689 #define clk_div_mask(width)	((1 << (width)) - 1)
708 			       unsigned long rate, unsigned long *prate,
712 				  unsigned long rate, unsigned long *prate,
721 int divider_get_val(unsigned long rate, unsigned long parent_rate,
743  * clk_register_divider - register a divider clock with the clock framework
747  * @flags: framework-specific flags
751  * @clk_divider_flags: divider-specific flags for this clock
760  * clk_hw_register_divider - register a divider clock with the clock framework
764  * @flags: framework-specific flags
768  * @clk_divider_flags: divider-specific flags for this clock
777  * clk_hw_register_divider_parent_hw - register a divider clock with the clock
782  * @flags: framework-specific flags
786  * @clk_divider_flags: divider-specific flags for this clock
796  * clk_hw_register_divider_parent_data - register a divider clock with the clock
801  * @flags: framework-specific flags
805  * @clk_divider_flags: divider-specific flags for this clock
815  * clk_hw_register_divider_table - register a table based divider clock with
820  * @flags: framework-specific flags
824  * @clk_divider_flags: divider-specific flags for this clock
835  * clk_hw_register_divider_table_parent_hw - register a table based divider
840  * @flags: framework-specific flags
844  * @clk_divider_flags: divider-specific flags for this clock
856  * clk_hw_register_divider_table_parent_data - register a table based divider
861  * @flags: framework-specific flags
865  * @clk_divider_flags: divider-specific flags for this clock
878  * devm_clk_hw_register_divider - register a divider clock with the clock framework
882  * @flags: framework-specific flags
886  * @clk_divider_flags: divider-specific flags for this clock
895  * devm_clk_hw_register_divider_parent_hw - register a divider clock with the clock framework
899  * @flags: framework-specific flags
903  * @clk_divider_flags: divider-specific flags for this clock
914  * devm_clk_hw_register_divider_table - register a table based divider clock
919  * @flags: framework-specific flags
923  * @clk_divider_flags: divider-specific flags for this clock
939  * struct clk_mux - multiplexer clock
941  * @hw:		handle between common and hardware-specific interfaces
946  * @flags:	hardware-specific flags
953  * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
954  * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
955  * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
956  *	register, and mask of mux bits are in higher 16-bit of this register.
957  *	While setting the mux bits, higher 16-bit should also be updated to
959  * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
961  * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
963  * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
1011 			       (flags), (reg), (shift), BIT((width)) - 1,     \
1031 			      (shift), BIT((width)) - 1, (clk_mux_flags),     \
1037 			      BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1043 			      BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1050 			      BIT((width)) - 1, (clk_mux_flags), table, (lock))
1055 			      (shift), BIT((width)) - 1, (clk_mux_flags),     \
1062 				   (shift), BIT((width)) - 1,		      \
1070 			      BIT((width)) - 1, (clk_mux_flags), table, (lock))
1082  * struct clk_fixed_factor - fixed multiplier and divider clock
1084  * @hw:		handle between common and hardware-specific interfaces
1088  * Clock with a fixed multiplier and divider. The output frequency is the
1089  * parent clock rate divided by div and multiplied by mult.
1125  * struct clk_fractional_divider - adjustable fractional divider clock
1127  * @hw:		handle between common and hardware-specific interfaces
1138  * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
1142  * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
1145  * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might
1150  *	caller's side the power-of-two capable prescaler exists.
1161 				unsigned long rate, unsigned long *parent_rate,
1183  * struct clk_multiplier - adjustable multiplier clock
1185  * @hw:		handle between common and hardware-specific interfaces
1195  * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
1197  *	zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
1199  *	leaving the parent rate unmodified.
1200  * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
1202  * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1224  * struct clk_composite - aggregate clock of mux, divider and gate clocks
1226  * @hw:		handle between common and hardware-specific interfaces
1227  * @mux_hw:	handle between composite and hardware-specific mux clock
1228  * @rate_hw:	handle between composite and hardware-specific rate clock
1229  * @gate_hw:	handle between composite and hardware-specific gate clock
1231  * @rate_ops:	clock ops for rate
1346 	dst->clk = src->clk;  in __clk_hw_set_clk()
1347 	dst->core = src->core;  in __clk_hw_set_clk()
1350 static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,  in divider_round_rate()  argument
1356 					 rate, prate, table, width, flags);  in divider_round_rate()
1359 static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,  in divider_ro_round_rate()  argument
1366 					    rate, prate, table, width, flags,  in divider_ro_round_rate()
1373 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
1508  * fixed factor clk declarations.
1587 	return ERR_PTR(-ENOENT);  in of_clk_src_simple_get()
1592 	return ERR_PTR(-ENOENT);  in of_clk_hw_simple_get()
1597 	return ERR_PTR(-ENOENT);  in of_clk_src_onecell_get()
1602 	return ERR_PTR(-ENOENT);  in of_clk_hw_onecell_get()