Lines Matching +full:0 +full:x1100
35 ({ if (status < 0) pr_warn(fmt, ##args); })
38 ({ if (status < 0) { pr_warn(fmt, ##args); return status; } })
41 ({ if (status < 0) { pr_warn(fmt, ##args); goto error; } })
45 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
46 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
55 #define UFX_IOCTL_RETURN_EDID (0xAD)
56 #define UFX_IOCTL_REPORT_DAMAGE (0xAA)
100 atomic_t usb_active; /* 0 = update virtual buffer, but no usb traffic */
111 .xpanstep = 0,
112 .ypanstep = 0,
113 .ywrapstep = 0,
122 {USB_DEVICE(0x0424, 0x9d00),},
123 {USB_DEVICE(0x0424, 0x9d01),},
152 ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0), in ufx_reg_read()
161 if (unlikely(ret < 0)) in ufx_reg_read()
162 pr_warn("Failed to read register index 0x%08x\n", index); in ufx_reg_read()
181 ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0), in ufx_reg_write()
188 if (unlikely(ret < 0)) in ufx_reg_write()
189 pr_warn("Failed to write register index 0x%08x with value " in ufx_reg_write()
190 "0x%08x\n", index, data); in ufx_reg_write()
201 "0x%x", index); in ufx_reg_clear_and_set_bits()
208 "0x%x", index); in ufx_reg_clear_and_set_bits()
210 return 0; in ufx_reg_clear_and_set_bits()
215 return ufx_reg_clear_and_set_bits(dev, index, 0, bits); in ufx_reg_set_bits()
220 return ufx_reg_clear_and_set_bits(dev, index, bits, 0); in ufx_reg_clear_bits()
228 status = ufx_reg_write(dev, 0x3008, 0x00000001); in ufx_lite_reset()
229 check_warn_return(status, "ufx_lite_reset error writing 0x3008"); in ufx_lite_reset()
231 status = ufx_reg_read(dev, 0x3008, &value); in ufx_lite_reset()
232 check_warn_return(status, "ufx_lite_reset error reading 0x3008"); in ufx_lite_reset()
234 return (value == 0) ? 0 : -EIO; in ufx_lite_reset()
243 int status = ufx_reg_read(dev, 0x2004, &dc_sts); in ufx_blank()
244 check_warn_return(status, "ufx_blank error reading 0x2004"); in ufx_blank()
246 status = ufx_reg_read(dev, 0x2000, &dc_ctrl); in ufx_blank()
247 check_warn_return(status, "ufx_blank error reading 0x2000"); in ufx_blank()
250 if ((dc_sts & 0x00000100) || (dc_ctrl & 0x00000100)) in ufx_blank()
251 return 0; in ufx_blank()
254 dc_ctrl |= 0x00000100; in ufx_blank()
255 status = ufx_reg_write(dev, 0x2000, dc_ctrl); in ufx_blank()
256 check_warn_return(status, "ufx_blank error writing 0x2000"); in ufx_blank()
260 return 0; in ufx_blank()
262 for (i = 0; i < 250; i++) { in ufx_blank()
263 status = ufx_reg_read(dev, 0x2004, &dc_sts); in ufx_blank()
264 check_warn_return(status, "ufx_blank error reading 0x2004"); in ufx_blank()
266 if (dc_sts & 0x00000100) in ufx_blank()
267 return 0; in ufx_blank()
280 int status = ufx_reg_read(dev, 0x2004, &dc_sts); in ufx_unblank()
281 check_warn_return(status, "ufx_unblank error reading 0x2004"); in ufx_unblank()
283 status = ufx_reg_read(dev, 0x2000, &dc_ctrl); in ufx_unblank()
284 check_warn_return(status, "ufx_unblank error reading 0x2000"); in ufx_unblank()
287 if (((dc_sts & 0x00000100) == 0) || ((dc_ctrl & 0x00000100) == 0)) in ufx_unblank()
288 return 0; in ufx_unblank()
291 dc_ctrl &= ~0x00000100; in ufx_unblank()
292 status = ufx_reg_write(dev, 0x2000, dc_ctrl); in ufx_unblank()
293 check_warn_return(status, "ufx_unblank error writing 0x2000"); in ufx_unblank()
297 return 0; in ufx_unblank()
299 for (i = 0; i < 250; i++) { in ufx_unblank()
300 status = ufx_reg_read(dev, 0x2004, &dc_sts); in ufx_unblank()
301 check_warn_return(status, "ufx_unblank error reading 0x2004"); in ufx_unblank()
303 if ((dc_sts & 0x00000100) == 0) in ufx_unblank()
304 return 0; in ufx_unblank()
317 int status = ufx_reg_read(dev, 0x2004, &dc_sts); in ufx_disable()
318 check_warn_return(status, "ufx_disable error reading 0x2004"); in ufx_disable()
320 status = ufx_reg_read(dev, 0x2000, &dc_ctrl); in ufx_disable()
321 check_warn_return(status, "ufx_disable error reading 0x2000"); in ufx_disable()
324 if (((dc_sts & 0x00000001) == 0) || ((dc_ctrl & 0x00000001) == 0)) in ufx_disable()
325 return 0; in ufx_disable()
328 dc_ctrl &= ~(0x00000001); in ufx_disable()
329 status = ufx_reg_write(dev, 0x2000, dc_ctrl); in ufx_disable()
330 check_warn_return(status, "ufx_disable error writing 0x2000"); in ufx_disable()
334 return 0; in ufx_disable()
336 for (i = 0; i < 250; i++) { in ufx_disable()
337 status = ufx_reg_read(dev, 0x2004, &dc_sts); in ufx_disable()
338 check_warn_return(status, "ufx_disable error reading 0x2004"); in ufx_disable()
340 if ((dc_sts & 0x00000001) == 0) in ufx_disable()
341 return 0; in ufx_disable()
354 int status = ufx_reg_read(dev, 0x2004, &dc_sts); in ufx_enable()
355 check_warn_return(status, "ufx_enable error reading 0x2004"); in ufx_enable()
357 status = ufx_reg_read(dev, 0x2000, &dc_ctrl); in ufx_enable()
358 check_warn_return(status, "ufx_enable error reading 0x2000"); in ufx_enable()
361 if ((dc_sts & 0x00000001) || (dc_ctrl & 0x00000001)) in ufx_enable()
362 return 0; in ufx_enable()
365 dc_ctrl |= 0x00000001; in ufx_enable()
366 status = ufx_reg_write(dev, 0x2000, dc_ctrl); in ufx_enable()
367 check_warn_return(status, "ufx_enable error writing 0x2000"); in ufx_enable()
371 return 0; in ufx_enable()
373 for (i = 0; i < 250; i++) { in ufx_enable()
374 status = ufx_reg_read(dev, 0x2004, &dc_sts); in ufx_enable()
375 check_warn_return(status, "ufx_enable error reading 0x2004"); in ufx_enable()
377 if (dc_sts & 0x00000001) in ufx_enable()
378 return 0; in ufx_enable()
387 int status = ufx_reg_write(dev, 0x700C, 0x8000000F); in ufx_config_sys_clk()
388 check_warn_return(status, "error writing 0x700C"); in ufx_config_sys_clk()
390 status = ufx_reg_write(dev, 0x7014, 0x0010024F); in ufx_config_sys_clk()
391 check_warn_return(status, "error writing 0x7014"); in ufx_config_sys_clk()
393 status = ufx_reg_write(dev, 0x7010, 0x00000000); in ufx_config_sys_clk()
394 check_warn_return(status, "error writing 0x7010"); in ufx_config_sys_clk()
396 status = ufx_reg_clear_bits(dev, 0x700C, 0x0000000A); in ufx_config_sys_clk()
397 check_warn_return(status, "error clearing PLL1 bypass in 0x700C"); in ufx_config_sys_clk()
400 status = ufx_reg_clear_bits(dev, 0x700C, 0x80000000); in ufx_config_sys_clk()
401 check_warn_return(status, "error clearing output gate in 0x700C"); in ufx_config_sys_clk()
403 return 0; in ufx_config_sys_clk()
408 int status, i = 0; in ufx_config_ddr2()
411 status = ufx_reg_write(dev, 0x0004, 0x001F0F77); in ufx_config_ddr2()
412 check_warn_return(status, "error writing 0x0004"); in ufx_config_ddr2()
414 status = ufx_reg_write(dev, 0x0008, 0xFFF00000); in ufx_config_ddr2()
415 check_warn_return(status, "error writing 0x0008"); in ufx_config_ddr2()
417 status = ufx_reg_write(dev, 0x000C, 0x0FFF2222); in ufx_config_ddr2()
418 check_warn_return(status, "error writing 0x000C"); in ufx_config_ddr2()
420 status = ufx_reg_write(dev, 0x0010, 0x00030814); in ufx_config_ddr2()
421 check_warn_return(status, "error writing 0x0010"); in ufx_config_ddr2()
423 status = ufx_reg_write(dev, 0x0014, 0x00500019); in ufx_config_ddr2()
424 check_warn_return(status, "error writing 0x0014"); in ufx_config_ddr2()
426 status = ufx_reg_write(dev, 0x0018, 0x020D0F15); in ufx_config_ddr2()
427 check_warn_return(status, "error writing 0x0018"); in ufx_config_ddr2()
429 status = ufx_reg_write(dev, 0x001C, 0x02532305); in ufx_config_ddr2()
430 check_warn_return(status, "error writing 0x001C"); in ufx_config_ddr2()
432 status = ufx_reg_write(dev, 0x0020, 0x0B030905); in ufx_config_ddr2()
433 check_warn_return(status, "error writing 0x0020"); in ufx_config_ddr2()
435 status = ufx_reg_write(dev, 0x0024, 0x00000827); in ufx_config_ddr2()
436 check_warn_return(status, "error writing 0x0024"); in ufx_config_ddr2()
438 status = ufx_reg_write(dev, 0x0028, 0x00000000); in ufx_config_ddr2()
439 check_warn_return(status, "error writing 0x0028"); in ufx_config_ddr2()
441 status = ufx_reg_write(dev, 0x002C, 0x00000042); in ufx_config_ddr2()
442 check_warn_return(status, "error writing 0x002C"); in ufx_config_ddr2()
444 status = ufx_reg_write(dev, 0x0030, 0x09520000); in ufx_config_ddr2()
445 check_warn_return(status, "error writing 0x0030"); in ufx_config_ddr2()
447 status = ufx_reg_write(dev, 0x0034, 0x02223314); in ufx_config_ddr2()
448 check_warn_return(status, "error writing 0x0034"); in ufx_config_ddr2()
450 status = ufx_reg_write(dev, 0x0038, 0x00430043); in ufx_config_ddr2()
451 check_warn_return(status, "error writing 0x0038"); in ufx_config_ddr2()
453 status = ufx_reg_write(dev, 0x003C, 0xF00F000F); in ufx_config_ddr2()
454 check_warn_return(status, "error writing 0x003C"); in ufx_config_ddr2()
456 status = ufx_reg_write(dev, 0x0040, 0xF380F00F); in ufx_config_ddr2()
457 check_warn_return(status, "error writing 0x0040"); in ufx_config_ddr2()
459 status = ufx_reg_write(dev, 0x0044, 0xF00F0496); in ufx_config_ddr2()
460 check_warn_return(status, "error writing 0x0044"); in ufx_config_ddr2()
462 status = ufx_reg_write(dev, 0x0048, 0x03080406); in ufx_config_ddr2()
463 check_warn_return(status, "error writing 0x0048"); in ufx_config_ddr2()
465 status = ufx_reg_write(dev, 0x004C, 0x00001000); in ufx_config_ddr2()
466 check_warn_return(status, "error writing 0x004C"); in ufx_config_ddr2()
468 status = ufx_reg_write(dev, 0x005C, 0x00000007); in ufx_config_ddr2()
469 check_warn_return(status, "error writing 0x005C"); in ufx_config_ddr2()
471 status = ufx_reg_write(dev, 0x0100, 0x54F00012); in ufx_config_ddr2()
472 check_warn_return(status, "error writing 0x0100"); in ufx_config_ddr2()
474 status = ufx_reg_write(dev, 0x0104, 0x00004012); in ufx_config_ddr2()
475 check_warn_return(status, "error writing 0x0104"); in ufx_config_ddr2()
477 status = ufx_reg_write(dev, 0x0118, 0x40404040); in ufx_config_ddr2()
478 check_warn_return(status, "error writing 0x0118"); in ufx_config_ddr2()
480 status = ufx_reg_write(dev, 0x0000, 0x00000001); in ufx_config_ddr2()
481 check_warn_return(status, "error writing 0x0000"); in ufx_config_ddr2()
484 status = ufx_reg_read(dev, 0x0000, &tmp); in ufx_config_ddr2()
485 check_warn_return(status, "error reading 0x0000"); in ufx_config_ddr2()
487 if (all_bits_set(tmp, 0xC0000000)) in ufx_config_ddr2()
488 return 0; in ufx_config_ddr2()
491 pr_err("DDR2 initialisation timed out, reg 0x0000=0x%08x", tmp); in ufx_config_ddr2()
553 for (div_q0 = 0; div_q0 < 7; div_q0++) { in ufx_calc_pll_values()
577 for (div_q1 = 0; div_q1 < 7; div_q1++) { in ufx_calc_pll_values()
591 * because a value of 0 = divide by 1 */ in ufx_calc_pll_values()
602 if (min_error == 0) in ufx_calc_pll_values()
616 struct pll_values asic_pll = {0}; in ufx_config_pix_clk()
630 status = ufx_reg_write(dev, 0x7000, 0x8000000F); in ufx_config_pix_clk()
631 check_warn_return(status, "error writing 0x7000"); in ufx_config_pix_clk()
635 status = ufx_reg_write(dev, 0x7008, value); in ufx_config_pix_clk()
636 check_warn_return(status, "error writing 0x7008"); in ufx_config_pix_clk()
640 status = ufx_reg_write(dev, 0x7004, value); in ufx_config_pix_clk()
641 check_warn_return(status, "error writing 0x7004"); in ufx_config_pix_clk()
643 status = ufx_reg_clear_bits(dev, 0x7000, 0x00000005); in ufx_config_pix_clk()
645 "error clearing PLL0 bypass bits in 0x7000"); in ufx_config_pix_clk()
648 status = ufx_reg_clear_bits(dev, 0x7000, 0x0000000A); in ufx_config_pix_clk()
650 "error clearing PLL1 bypass bits in 0x7000"); in ufx_config_pix_clk()
653 status = ufx_reg_clear_bits(dev, 0x7000, 0x80000000); in ufx_config_pix_clk()
654 check_warn_return(status, "error clearing gate bits in 0x7000"); in ufx_config_pix_clk()
656 return 0; in ufx_config_pix_clk()
665 int status = ufx_reg_write(dev, 0x8028, 0); in ufx_set_vid_mode()
668 status = ufx_reg_write(dev, 0x8024, 0); in ufx_set_vid_mode()
681 status = ufx_reg_write(dev, 0x2000, 0x00000104); in ufx_set_vid_mode()
682 check_warn_return(status, "ufx_set_vid_mode error writing 0x2000"); in ufx_set_vid_mode()
693 status = ufx_reg_write(dev, 0x2008, temp); in ufx_set_vid_mode()
694 check_warn_return(status, "ufx_set_vid_mode error writing 0x2008"); in ufx_set_vid_mode()
697 status = ufx_reg_write(dev, 0x200C, temp); in ufx_set_vid_mode()
698 check_warn_return(status, "ufx_set_vid_mode error writing 0x200C"); in ufx_set_vid_mode()
701 status = ufx_reg_write(dev, 0x2010, temp); in ufx_set_vid_mode()
702 check_warn_return(status, "ufx_set_vid_mode error writing 0x2010"); in ufx_set_vid_mode()
713 status = ufx_reg_write(dev, 0x2014, temp); in ufx_set_vid_mode()
714 check_warn_return(status, "ufx_set_vid_mode error writing 0x2014"); in ufx_set_vid_mode()
717 status = ufx_reg_write(dev, 0x2018, temp); in ufx_set_vid_mode()
718 check_warn_return(status, "ufx_set_vid_mode error writing 0x2018"); in ufx_set_vid_mode()
721 status = ufx_reg_write(dev, 0x201C, temp); in ufx_set_vid_mode()
722 check_warn_return(status, "ufx_set_vid_mode error writing 0x201C"); in ufx_set_vid_mode()
724 status = ufx_reg_write(dev, 0x2020, 0x00000000); in ufx_set_vid_mode()
725 check_warn_return(status, "ufx_set_vid_mode error writing 0x2020"); in ufx_set_vid_mode()
727 status = ufx_reg_write(dev, 0x2024, 0x00000000); in ufx_set_vid_mode()
728 check_warn_return(status, "ufx_set_vid_mode error writing 0x2024"); in ufx_set_vid_mode()
732 temp = (temp + 7) & (~0x7); in ufx_set_vid_mode()
733 status = ufx_reg_write(dev, 0x2028, temp); in ufx_set_vid_mode()
734 check_warn_return(status, "ufx_set_vid_mode error writing 0x2028"); in ufx_set_vid_mode()
737 status = ufx_reg_write(dev, 0x2040, 0); in ufx_set_vid_mode()
738 check_warn_return(status, "ufx_set_vid_mode error writing 0x2040"); in ufx_set_vid_mode()
740 status = ufx_reg_write(dev, 0x2044, 0); in ufx_set_vid_mode()
741 check_warn_return(status, "ufx_set_vid_mode error writing 0x2044"); in ufx_set_vid_mode()
743 status = ufx_reg_write(dev, 0x2048, 0); in ufx_set_vid_mode()
744 check_warn_return(status, "ufx_set_vid_mode error writing 0x2048"); in ufx_set_vid_mode()
747 temp = 0x00000001; in ufx_set_vid_mode()
749 temp |= 0x00000010; in ufx_set_vid_mode()
752 temp |= 0x00000008; in ufx_set_vid_mode()
754 status = ufx_reg_write(dev, 0x2040, temp); in ufx_set_vid_mode()
755 check_warn_return(status, "ufx_set_vid_mode error writing 0x2040"); in ufx_set_vid_mode()
766 status = ufx_reg_write(dev, 0x8028, 0x00000003); in ufx_set_vid_mode()
770 status = ufx_reg_write(dev, 0x8024, 0x00000007); in ufx_set_vid_mode()
773 return 0; in ufx_set_vid_mode()
786 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) in ufx_ops_mmap()
798 while (size > 0) { in ufx_ops_mmap()
808 size = 0; in ufx_ops_mmap()
811 return 0; in ufx_ops_mmap()
825 *((u32 *)&cmd[0]) = cpu_to_le32(0x01); in ufx_raw_rect()
836 *((u32 *)&cmd[8]) = cpu_to_le32(0); in ufx_raw_rect()
839 cmd[10] = cpu_to_le16(0x4000 | dev->info->var.xres); in ufx_raw_rect()
845 for (line = 0; line < height; line++) { in ufx_raw_rect()
857 int len, status, urb_lines, start_line = 0; in ufx_handle_damage()
859 if ((width <= 0) || (height <= 0) || in ufx_handle_damage()
865 return 0; in ufx_handle_damage()
871 return 0; in ufx_handle_damage()
883 memset(urb->transfer_buffer, 0, urb->transfer_buffer_length); in ufx_handle_damage()
894 return 0; in ufx_handle_damage()
910 if (result > 0) { in ufx_ops_write()
911 int start = max((int)(offset / info->fix.line_length), 0); in ufx_ops_write()
915 ufx_handle_damage(dev, 0, start, info->var.xres, lines); in ufx_ops_write()
974 const int x = 0; in ufx_dpy_deferred_io()
994 return 0; in ufx_ops_ioctl()
1001 return 0; in ufx_ops_ioctl()
1017 if (area->x < 0) in ufx_ops_ioctl()
1018 area->x = 0; in ufx_ops_ioctl()
1023 if (area->y < 0) in ufx_ops_ioctl()
1024 area->y = 0; in ufx_ops_ioctl()
1032 return 0; in ufx_ops_ioctl()
1040 int err = 0; in ufx_ops_setcolreg()
1049 ((red & 0xf800) >> 1) | in ufx_ops_setcolreg()
1050 ((green & 0xf800) >> 6) | ((blue & 0xf800) >> 11); in ufx_ops_setcolreg()
1052 /* 0:5:6:5 */ in ufx_ops_setcolreg()
1054 ((red & 0xf800)) | in ufx_ops_setcolreg()
1055 ((green & 0xfc00) >> 5) | ((blue & 0xf800) >> 11); in ufx_ops_setcolreg()
1072 if (user == 0 && !console) in ufx_ops_open()
1107 return 0; in ufx_ops_open()
1149 if (info->cmap.len != 0) in ufx_free_framebuffer()
1175 if (dev->virtualized && (dev->fb_count == 0)) in ufx_ops_release()
1178 if ((dev->fb_count == 0) && (info->fbdefio)) { in ufx_ops_release()
1191 return 0; in ufx_ops_release()
1202 return 0; in ufx_is_valid_mode()
1208 return 0; in ufx_is_valid_mode()
1218 const struct fb_bitfield red = { 11, 5, 0 }; in ufx_var_color_format()
1219 const struct fb_bitfield green = { 5, 6, 0 }; in ufx_var_color_format()
1220 const struct fb_bitfield blue = { 0, 5, 0 }; in ufx_var_color_format()
1245 return 0; in ufx_ops_check_var()
1258 if ((result == 0) && (dev->fb_count == 0)) { in ufx_ops_set_par()
1261 for (i = 0; i < info->fix.smem_len / 2; i++) in ufx_ops_set_par()
1262 pix_framebuffer[i] = 0x37e6; in ufx_ops_set_par()
1264 ufx_handle_damage(dev, 0, 0, info->var.xres, info->var.yres); in ufx_ops_set_par()
1279 return 0; in ufx_ops_blank()
1331 return 0; in ufx_realloc_framebuffer()
1341 int status = ufx_reg_write(dev, 0x106C, 0x00); in ufx_i2c_init()
1346 status = ufx_reg_write(dev, 0x1018, 12); in ufx_i2c_init()
1347 check_warn_return(status, "error writing 0x1018"); in ufx_i2c_init()
1350 status = ufx_reg_write(dev, 0x1014, 6); in ufx_i2c_init()
1351 check_warn_return(status, "error writing 0x1014"); in ufx_i2c_init()
1353 status = ufx_reg_read(dev, 0x1000, &tmp); in ufx_i2c_init()
1354 check_warn_return(status, "error reading 0x1000"); in ufx_i2c_init()
1357 tmp &= ~(0x06); in ufx_i2c_init()
1358 tmp |= 0x02; in ufx_i2c_init()
1361 tmp &= ~(0x10); in ufx_i2c_init()
1364 tmp |= 0x21; in ufx_i2c_init()
1366 status = ufx_reg_write(dev, 0x1000, tmp); in ufx_i2c_init()
1367 check_warn_return(status, "error writing 0x1000"); in ufx_i2c_init()
1369 /* Set normal tx using target address 0 */ in ufx_i2c_init()
1370 status = ufx_reg_clear_and_set_bits(dev, 0x1004, 0xC00, 0x000); in ufx_i2c_init()
1371 check_warn_return(status, "error setting TX mode bits in 0x1004"); in ufx_i2c_init()
1374 status = ufx_reg_write(dev, 0x106C, 0x01); in ufx_i2c_init()
1377 return 0; in ufx_i2c_init()
1383 int status = ufx_reg_write(dev, 0x106C, 0x00); in ufx_i2c_configure()
1386 status = ufx_reg_write(dev, 0x3010, 0x00000000); in ufx_i2c_configure()
1387 check_warn_return(status, "failed to write 0x3010"); in ufx_i2c_configure()
1390 status = ufx_reg_clear_and_set_bits(dev, 0x1004, 0x3FF, (0xA0 >> 1)); in ufx_i2c_configure()
1391 check_warn_return(status, "failed to set TAR bits in 0x1004"); in ufx_i2c_configure()
1393 status = ufx_reg_write(dev, 0x106C, 0x01); in ufx_i2c_configure()
1396 return 0; in ufx_i2c_configure()
1406 for (i = 0; i < 15; i++) { in ufx_i2c_wait_busy()
1407 status = ufx_reg_read(dev, 0x1100, &tmp); in ufx_i2c_wait_busy()
1408 check_warn_return(status, "0x1100 read failed"); in ufx_i2c_wait_busy()
1411 if ((tmp & 0x80000000) == 0) { in ufx_i2c_wait_busy()
1412 if (tmp & 0x20000000) { in ufx_i2c_wait_busy()
1413 pr_warn("I2C read failed, 0x1100=0x%08x", tmp); in ufx_i2c_wait_busy()
1417 return 0; in ufx_i2c_wait_busy()
1426 status = ufx_reg_write(dev, 0x1100, 0x40000000); in ufx_i2c_wait_busy()
1427 check_warn_return(status, "0x1100 write failed"); in ufx_i2c_wait_busy()
1441 if (status < 0) { in ufx_read_edid()
1446 memset(edid, 0xff, EDID_LENGTH); in ufx_read_edid()
1449 for (i = 0; i < 2; i++) { in ufx_read_edid()
1450 u32 temp = 0x28070000 | (63 << 20) | (((u32)(i * 64)) << 8); in ufx_read_edid()
1451 status = ufx_reg_write(dev, 0x1100, temp); in ufx_read_edid()
1452 check_warn_return(status, "Failed to write 0x1100"); in ufx_read_edid()
1454 temp |= 0x80000000; in ufx_read_edid()
1455 status = ufx_reg_write(dev, 0x1100, temp); in ufx_read_edid()
1456 check_warn_return(status, "Failed to write 0x1100"); in ufx_read_edid()
1461 for (j = 0; j < 16; j++) { in ufx_read_edid()
1462 u32 data_reg_addr = 0x1110 + (j * 4); in ufx_read_edid()
1469 for (i = 0; i < 16; i++) { in ufx_read_edid()
1470 if (edid[i] != 0xFF) { in ufx_read_edid()
1476 pr_warn("edid data contains all 0xff"); in ufx_read_edid()
1491 * Returns 0 if successful */
1497 int i, result = 0, tries = 3; in ufx_setup_modes()
1509 memset(&info->monspecs, 0, sizeof(info->monspecs)); in ufx_setup_modes()
1520 if (info->monspecs.modedb_len > 0) { in ufx_setup_modes()
1528 if (info->monspecs.modedb_len == 0) { in ufx_setup_modes()
1533 if (info->monspecs.modedb_len > 0) in ufx_setup_modes()
1539 if (info->monspecs.modedb_len == 0) { in ufx_setup_modes()
1542 if (info->monspecs.modedb_len > 0) { in ufx_setup_modes()
1552 if (info->monspecs.modedb_len > 0) { in ufx_setup_modes()
1554 for (i = 0; i < info->monspecs.modedb_len; i++) { in ufx_setup_modes()
1569 struct fb_videomode fb_vmode = {0}; in ufx_setup_modes()
1576 for (i = 0; i < VESA_MODEDB_SIZE; i++) { in ufx_setup_modes()
1594 if ((default_vmode != NULL) && (dev->fb_count == 0)) { in ufx_setup_modes()
1663 info = framebuffer_alloc(0, &usbdev->dev); in ufx_usb_probe()
1675 retval = fb_alloc_cmap(&info->cmap, 256, 0); in ufx_usb_probe()
1676 if (retval < 0) { in ufx_usb_probe()
1681 retval = ufx_reg_read(dev, 0x3000, &id_rev); in ufx_usb_probe()
1682 check_warn_goto_error(retval, "error %d reading 0x3000 register from device", retval); in ufx_usb_probe()
1683 dev_dbg(dev->gdev, "ID_REV register value 0x%08x", id_rev); in ufx_usb_probe()
1685 retval = ufx_reg_read(dev, 0x3004, &fpga_rev); in ufx_usb_probe()
1686 check_warn_goto_error(retval, "error %d reading 0x3004 register from device", retval); in ufx_usb_probe()
1687 dev_dbg(dev->gdev, "FPGA_REV register value 0x%08x", fpga_rev); in ufx_usb_probe()
1706 retval = ufx_setup_modes(dev, info, NULL, 0); in ufx_usb_probe()
1709 retval = ufx_reg_set_bits(dev, 0x4000, 0x00000001); in ufx_usb_probe()
1710 if (retval < 0) { in ufx_usb_probe()
1720 if (retval < 0) { in ufx_usb_probe()
1727 if (retval < 0) { in ufx_usb_probe()
1734 if (retval < 0) { in ufx_usb_probe()
1743 return 0; in ufx_usb_probe()
1746 atomic_set(&dev->usb_active, 0); in ufx_usb_probe()
1756 if (dev->urbs.count > 0) in ufx_usb_probe()
1780 atomic_set(&dev->usb_active, 0); in ufx_usb_disconnect()
1785 if (dev->fb_count == 0) in ufx_usb_disconnect()
1789 if (dev->urbs.count > 0) in ufx_usb_disconnect()
1835 schedule_delayed_work(&unode->release_urb_work, 0); in ufx_urb_completion()
1878 int i = 0; in ufx_alloc_urb_list()
1897 urb = usb_alloc_urb(0, GFP_KERNEL); in ufx_alloc_urb_list()
1933 int ret = 0; in ufx_get_urb()