71 #define write_cr(num, val)	mm_write_cr(p, num, val)  macro
191 	write_cr(0x11, (ve - 1) & 0x0f);  in asiliant_set_timing()
192 	write_cr(0x00, (ht - 5) & 0xff);  in asiliant_set_timing()
193 	write_cr(0x01, hd - 1);  in asiliant_set_timing()
194 	write_cr(0x02, hd);  in asiliant_set_timing()
195 	write_cr(0x03, ((ht - 1) & 0x1f) | 0x80);  in asiliant_set_timing()
196 	write_cr(0x04, hs);  in asiliant_set_timing()
197 	write_cr(0x05, (((ht - 1) & 0x20) <<2) | (he & 0x1f));  in asiliant_set_timing()
198 	write_cr(0x3c, (ht - 1) & 0xc0);  in asiliant_set_timing()
199 	write_cr(0x06, (vt - 2) & 0xff);  in asiliant_set_timing()
200 	write_cr(0x30, (vt - 2) >> 8);  in asiliant_set_timing()
201 	write_cr(0x07, 0x00);  in asiliant_set_timing()
202 	write_cr(0x08, 0x00);  in asiliant_set_timing()
203 	write_cr(0x09, 0x00);  in asiliant_set_timing()
204 	write_cr(0x10, (vs - 1) & 0xff);  in asiliant_set_timing()
205 	write_cr(0x32, ((vs - 1) >> 8) & 0xf);  in asiliant_set_timing()
206 	write_cr(0x11, ((ve - 1) & 0x0f) | 0x80);  in asiliant_set_timing()
207 	write_cr(0x12, (vd - 1) & 0xff);  in asiliant_set_timing()
208 	write_cr(0x31, ((vd - 1) & 0xf00) >> 8);  in asiliant_set_timing()
209 	write_cr(0x13, wd & 0xff);  in asiliant_set_timing()
210 	write_cr(0x41, (wd & 0xf00) >> 8);  in asiliant_set_timing()
211 	write_cr(0x15, (vs - 1) & 0xff);  in asiliant_set_timing()
212 	write_cr(0x33, ((vs - 1) >> 8) & 0xf);  in asiliant_set_timing()
213 	write_cr(0x38, ((ht - 5) & 0x100) >> 8);  in asiliant_set_timing()
214 	write_cr(0x16, (vt - 1) & 0xff);  in asiliant_set_timing()
215 	write_cr(0x18, 0x00);  in asiliant_set_timing()
474 		write_cr(chips_init_cr[i].addr, chips_init_cr[i].data);  in chips_hw_init()