34 #define UDC_DEVCTL_ADDR		0x404	/* Device control */  macro
506 	pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);  in pch_udc_rmt_wakeup()
508 	pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);  in pch_udc_rmt_wakeup()
546 	pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);  in pch_udc_set_disconnect()
556 	pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);  in pch_udc_clear_disconnect()
557 	pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);  in pch_udc_clear_disconnect()
560 	pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);  in pch_udc_clear_disconnect()
580 	pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);  in pch_udc_reconnect()
581 	pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);  in pch_udc_reconnect()
584 	pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);  in pch_udc_reconnect()
744 		pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);  in pch_udc_set_dma()
746 		pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);  in pch_udc_set_dma()
760 		pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);  in pch_udc_clear_dma()
762 		pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);  in pch_udc_clear_dma()
772 	pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_CSR_DONE);  in pch_udc_set_csr_done()
1072 	pch_udc_bit_set(dev, UDC_DEVCTL_ADDR,  in pch_udc_init()