Lines Matching +full:srp +full:- +full:capable
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) 2004-2016 Synopsys, Inc.
20 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_bcm_params()
22 p->host_rx_fifo_size = 774; in dwc2_set_bcm_params()
23 p->max_transfer_size = 65535; in dwc2_set_bcm_params()
24 p->max_packet_count = 511; in dwc2_set_bcm_params()
25 p->ahbcfg = 0x10; in dwc2_set_bcm_params()
30 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_his_params()
32 p->otg_caps.hnp_support = false; in dwc2_set_his_params()
33 p->otg_caps.srp_support = false; in dwc2_set_his_params()
34 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_his_params()
35 p->host_rx_fifo_size = 512; in dwc2_set_his_params()
36 p->host_nperio_tx_fifo_size = 512; in dwc2_set_his_params()
37 p->host_perio_tx_fifo_size = 512; in dwc2_set_his_params()
38 p->max_transfer_size = 65535; in dwc2_set_his_params()
39 p->max_packet_count = 511; in dwc2_set_his_params()
40 p->host_channels = 16; in dwc2_set_his_params()
41 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_his_params()
42 p->phy_utmi_width = 8; in dwc2_set_his_params()
43 p->i2c_enable = false; in dwc2_set_his_params()
44 p->reload_ctl = false; in dwc2_set_his_params()
45 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << in dwc2_set_his_params()
47 p->change_speed_quirk = true; in dwc2_set_his_params()
48 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_his_params()
53 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_jz4775_params()
55 p->otg_caps.hnp_support = false; in dwc2_set_jz4775_params()
56 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_jz4775_params()
57 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_jz4775_params()
58 p->phy_utmi_width = 16; in dwc2_set_jz4775_params()
59 p->activate_ingenic_overcurrent_detection = in dwc2_set_jz4775_params()
60 !device_property_read_bool(hsotg->dev, "disable-over-current"); in dwc2_set_jz4775_params()
65 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_loongson_params()
67 p->phy_utmi_width = 8; in dwc2_set_loongson_params()
68 p->power_down = DWC2_POWER_DOWN_PARAM_PARTIAL; in dwc2_set_loongson_params()
73 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_x1600_params()
75 p->otg_caps.hnp_support = false; in dwc2_set_x1600_params()
76 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_x1600_params()
77 p->host_channels = 16; in dwc2_set_x1600_params()
78 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_x1600_params()
79 p->phy_utmi_width = 16; in dwc2_set_x1600_params()
80 p->activate_ingenic_overcurrent_detection = in dwc2_set_x1600_params()
81 !device_property_read_bool(hsotg->dev, "disable-over-current"); in dwc2_set_x1600_params()
86 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_x2000_params()
88 p->otg_caps.hnp_support = false; in dwc2_set_x2000_params()
89 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_x2000_params()
90 p->host_rx_fifo_size = 1024; in dwc2_set_x2000_params()
91 p->host_nperio_tx_fifo_size = 1024; in dwc2_set_x2000_params()
92 p->host_perio_tx_fifo_size = 1024; in dwc2_set_x2000_params()
93 p->host_channels = 16; in dwc2_set_x2000_params()
94 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_x2000_params()
95 p->phy_utmi_width = 16; in dwc2_set_x2000_params()
96 p->activate_ingenic_overcurrent_detection = in dwc2_set_x2000_params()
97 !device_property_read_bool(hsotg->dev, "disable-over-current"); in dwc2_set_x2000_params()
102 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_s3c6400_params()
104 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_s3c6400_params()
105 p->no_clock_gating = true; in dwc2_set_s3c6400_params()
106 p->phy_utmi_width = 8; in dwc2_set_s3c6400_params()
111 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_socfpga_agilex_params()
113 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_socfpga_agilex_params()
114 p->no_clock_gating = true; in dwc2_set_socfpga_agilex_params()
119 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_rk_params()
121 p->otg_caps.hnp_support = false; in dwc2_set_rk_params()
122 p->otg_caps.srp_support = false; in dwc2_set_rk_params()
123 p->host_rx_fifo_size = 525; in dwc2_set_rk_params()
124 p->host_nperio_tx_fifo_size = 128; in dwc2_set_rk_params()
125 p->host_perio_tx_fifo_size = 256; in dwc2_set_rk_params()
126 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << in dwc2_set_rk_params()
128 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_rk_params()
129 p->lpm = false; in dwc2_set_rk_params()
130 p->lpm_clock_gating = false; in dwc2_set_rk_params()
131 p->besl = false; in dwc2_set_rk_params()
132 p->hird_threshold_en = false; in dwc2_set_rk_params()
137 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_ltq_params()
139 p->otg_caps.hnp_support = false; in dwc2_set_ltq_params()
140 p->otg_caps.srp_support = false; in dwc2_set_ltq_params()
141 p->host_rx_fifo_size = 288; in dwc2_set_ltq_params()
142 p->host_nperio_tx_fifo_size = 128; in dwc2_set_ltq_params()
143 p->host_perio_tx_fifo_size = 96; in dwc2_set_ltq_params()
144 p->max_transfer_size = 65535; in dwc2_set_ltq_params()
145 p->max_packet_count = 511; in dwc2_set_ltq_params()
146 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << in dwc2_set_ltq_params()
152 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_amlogic_params()
154 p->otg_caps.hnp_support = false; in dwc2_set_amlogic_params()
155 p->otg_caps.srp_support = false; in dwc2_set_amlogic_params()
156 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_amlogic_params()
157 p->host_rx_fifo_size = 512; in dwc2_set_amlogic_params()
158 p->host_nperio_tx_fifo_size = 500; in dwc2_set_amlogic_params()
159 p->host_perio_tx_fifo_size = 500; in dwc2_set_amlogic_params()
160 p->host_channels = 16; in dwc2_set_amlogic_params()
161 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_amlogic_params()
162 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << in dwc2_set_amlogic_params()
164 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_amlogic_params()
169 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_amlogic_g12a_params()
171 p->lpm = false; in dwc2_set_amlogic_g12a_params()
172 p->lpm_clock_gating = false; in dwc2_set_amlogic_g12a_params()
173 p->besl = false; in dwc2_set_amlogic_g12a_params()
174 p->hird_threshold_en = false; in dwc2_set_amlogic_g12a_params()
179 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_amlogic_a1_params()
181 p->otg_caps.hnp_support = false; in dwc2_set_amlogic_a1_params()
182 p->otg_caps.srp_support = false; in dwc2_set_amlogic_a1_params()
183 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_amlogic_a1_params()
184 p->host_rx_fifo_size = 192; in dwc2_set_amlogic_a1_params()
185 p->host_nperio_tx_fifo_size = 128; in dwc2_set_amlogic_a1_params()
186 p->host_perio_tx_fifo_size = 128; in dwc2_set_amlogic_a1_params()
187 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_amlogic_a1_params()
188 p->phy_utmi_width = 8; in dwc2_set_amlogic_a1_params()
189 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << GAHBCFG_HBSTLEN_SHIFT; in dwc2_set_amlogic_a1_params()
190 p->lpm = false; in dwc2_set_amlogic_a1_params()
191 p->lpm_clock_gating = false; in dwc2_set_amlogic_a1_params()
192 p->besl = false; in dwc2_set_amlogic_a1_params()
193 p->hird_threshold_en = false; in dwc2_set_amlogic_a1_params()
198 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_amcc_params()
200 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; in dwc2_set_amcc_params()
205 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_stm32f4x9_fsotg_params()
207 p->otg_caps.hnp_support = false; in dwc2_set_stm32f4x9_fsotg_params()
208 p->otg_caps.srp_support = false; in dwc2_set_stm32f4x9_fsotg_params()
209 p->speed = DWC2_SPEED_PARAM_FULL; in dwc2_set_stm32f4x9_fsotg_params()
210 p->host_rx_fifo_size = 128; in dwc2_set_stm32f4x9_fsotg_params()
211 p->host_nperio_tx_fifo_size = 96; in dwc2_set_stm32f4x9_fsotg_params()
212 p->host_perio_tx_fifo_size = 96; in dwc2_set_stm32f4x9_fsotg_params()
213 p->max_packet_count = 256; in dwc2_set_stm32f4x9_fsotg_params()
214 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; in dwc2_set_stm32f4x9_fsotg_params()
215 p->i2c_enable = false; in dwc2_set_stm32f4x9_fsotg_params()
216 p->activate_stm_fs_transceiver = true; in dwc2_set_stm32f4x9_fsotg_params()
221 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_stm32f7_hsotg_params()
223 p->host_rx_fifo_size = 622; in dwc2_set_stm32f7_hsotg_params()
224 p->host_nperio_tx_fifo_size = 128; in dwc2_set_stm32f7_hsotg_params()
225 p->host_perio_tx_fifo_size = 256; in dwc2_set_stm32f7_hsotg_params()
230 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_stm32mp15_fsotg_params()
232 p->otg_caps.hnp_support = false; in dwc2_set_stm32mp15_fsotg_params()
233 p->otg_caps.srp_support = false; in dwc2_set_stm32mp15_fsotg_params()
234 p->otg_caps.otg_rev = 0x200; in dwc2_set_stm32mp15_fsotg_params()
235 p->speed = DWC2_SPEED_PARAM_FULL; in dwc2_set_stm32mp15_fsotg_params()
236 p->host_rx_fifo_size = 128; in dwc2_set_stm32mp15_fsotg_params()
237 p->host_nperio_tx_fifo_size = 96; in dwc2_set_stm32mp15_fsotg_params()
238 p->host_perio_tx_fifo_size = 96; in dwc2_set_stm32mp15_fsotg_params()
239 p->max_packet_count = 256; in dwc2_set_stm32mp15_fsotg_params()
240 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; in dwc2_set_stm32mp15_fsotg_params()
241 p->i2c_enable = false; in dwc2_set_stm32mp15_fsotg_params()
242 p->activate_stm_fs_transceiver = true; in dwc2_set_stm32mp15_fsotg_params()
243 p->activate_stm_id_vb_detection = true; in dwc2_set_stm32mp15_fsotg_params()
244 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; in dwc2_set_stm32mp15_fsotg_params()
245 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_stm32mp15_fsotg_params()
246 p->host_support_fs_ls_low_power = true; in dwc2_set_stm32mp15_fsotg_params()
247 p->host_ls_low_power_phy_clk = true; in dwc2_set_stm32mp15_fsotg_params()
252 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_stm32mp15_hsotg_params()
254 p->otg_caps.hnp_support = false; in dwc2_set_stm32mp15_hsotg_params()
255 p->otg_caps.srp_support = false; in dwc2_set_stm32mp15_hsotg_params()
256 p->otg_caps.otg_rev = 0x200; in dwc2_set_stm32mp15_hsotg_params()
257 p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch"); in dwc2_set_stm32mp15_hsotg_params()
258 p->host_rx_fifo_size = 440; in dwc2_set_stm32mp15_hsotg_params()
259 p->host_nperio_tx_fifo_size = 256; in dwc2_set_stm32mp15_hsotg_params()
260 p->host_perio_tx_fifo_size = 256; in dwc2_set_stm32mp15_hsotg_params()
261 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; in dwc2_set_stm32mp15_hsotg_params()
262 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_stm32mp15_hsotg_params()
263 p->lpm = false; in dwc2_set_stm32mp15_hsotg_params()
264 p->lpm_clock_gating = false; in dwc2_set_stm32mp15_hsotg_params()
265 p->besl = false; in dwc2_set_stm32mp15_hsotg_params()
266 p->hird_threshold_en = false; in dwc2_set_stm32mp15_hsotg_params()
270 { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
271 { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params },
272 { .compatible = "ingenic,jz4775-otg", .data = dwc2_set_jz4775_params },
273 { .compatible = "ingenic,jz4780-otg", .data = dwc2_set_jz4775_params },
274 { .compatible = "ingenic,x1000-otg", .data = dwc2_set_jz4775_params },
275 { .compatible = "ingenic,x1600-otg", .data = dwc2_set_x1600_params },
276 { .compatible = "ingenic,x1700-otg", .data = dwc2_set_x1600_params },
277 { .compatible = "ingenic,x1830-otg", .data = dwc2_set_x1600_params },
278 { .compatible = "ingenic,x2000-otg", .data = dwc2_set_x2000_params },
279 { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
280 { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
281 { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
283 { .compatible = "samsung,s3c6400-hsotg",
285 { .compatible = "amlogic,meson8-usb",
287 { .compatible = "amlogic,meson8b-usb",
289 { .compatible = "amlogic,meson-gxbb-usb",
291 { .compatible = "amlogic,meson-g12a-usb",
293 { .compatible = "amlogic,meson-a1-usb",
295 { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
296 { .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params },
297 { .compatible = "st,stm32f4x9-fsotg",
299 { .compatible = "st,stm32f4x9-hsotg" },
300 { .compatible = "st,stm32f7-hsotg",
302 { .compatible = "st,stm32mp15-fsotg",
304 { .compatible = "st,stm32mp15-hsotg",
306 { .compatible = "intel,socfpga-agilex-hsotg",
337 switch (hsotg->hw_params.op_mode) { in dwc2_set_param_otg_cap()
339 hsotg->params.otg_caps.hnp_support = true; in dwc2_set_param_otg_cap()
340 hsotg->params.otg_caps.srp_support = true; in dwc2_set_param_otg_cap()
345 hsotg->params.otg_caps.hnp_support = false; in dwc2_set_param_otg_cap()
346 hsotg->params.otg_caps.srp_support = true; in dwc2_set_param_otg_cap()
349 hsotg->params.otg_caps.hnp_support = false; in dwc2_set_param_otg_cap()
350 hsotg->params.otg_caps.srp_support = false; in dwc2_set_param_otg_cap()
358 u32 hs_phy_type = hsotg->hw_params.hs_phy_type; in dwc2_set_param_phy_type()
370 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS; in dwc2_set_param_phy_type()
372 hsotg->params.phy_type = val; in dwc2_set_param_phy_type()
379 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ? in dwc2_set_param_speed()
388 hsotg->params.speed = val; in dwc2_set_param_speed()
395 val = (hsotg->hw_params.utmi_phy_data_width == in dwc2_set_param_phy_utmi_width()
398 if (hsotg->phy) { in dwc2_set_param_phy_utmi_width()
401 * width is 8-bit and set the phyif appropriately. in dwc2_set_param_phy_utmi_width()
403 if (phy_get_bus_width(hsotg->phy) == 8) in dwc2_set_param_phy_utmi_width()
407 hsotg->params.phy_utmi_width = val; in dwc2_set_param_phy_utmi_width()
412 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_param_tx_fifo_sizes()
419 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); in dwc2_set_param_tx_fifo_sizes()
422 p->g_tx_fifo_size[i] = depth_average; in dwc2_set_param_tx_fifo_sizes()
429 if (hsotg->hw_params.hibernation) in dwc2_set_param_power_down()
431 else if (hsotg->hw_params.power_optimized) in dwc2_set_param_power_down()
436 hsotg->params.power_down = val; in dwc2_set_param_power_down()
441 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_param_lpm()
443 p->lpm = hsotg->hw_params.lpm_mode; in dwc2_set_param_lpm()
444 if (p->lpm) { in dwc2_set_param_lpm()
445 p->lpm_clock_gating = true; in dwc2_set_param_lpm()
446 p->besl = true; in dwc2_set_param_lpm()
447 p->hird_threshold_en = true; in dwc2_set_param_lpm()
448 p->hird_threshold = 4; in dwc2_set_param_lpm()
450 p->lpm_clock_gating = false; in dwc2_set_param_lpm()
451 p->besl = false; in dwc2_set_param_lpm()
452 p->hird_threshold_en = false; in dwc2_set_param_lpm()
457 * dwc2_set_default_params() - Set all core parameters to their
458 * auto-detected default values.
465 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_set_default_params()
466 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_default_params()
467 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); in dwc2_set_default_params()
475 p->phy_ulpi_ddr = false; in dwc2_set_default_params()
476 p->phy_ulpi_ext_vbus = false; in dwc2_set_default_params()
478 p->enable_dynamic_fifo = hw->enable_dynamic_fifo; in dwc2_set_default_params()
479 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo; in dwc2_set_default_params()
480 p->i2c_enable = hw->i2c_enable; in dwc2_set_default_params()
481 p->acg_enable = hw->acg_enable; in dwc2_set_default_params()
482 p->ulpi_fs_ls = false; in dwc2_set_default_params()
483 p->ts_dline = false; in dwc2_set_default_params()
484 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a); in dwc2_set_default_params()
485 p->uframe_sched = true; in dwc2_set_default_params()
486 p->external_id_pin_ctl = false; in dwc2_set_default_params()
487 p->ipg_isoc_en = false; in dwc2_set_default_params()
488 p->service_interval = false; in dwc2_set_default_params()
489 p->max_packet_count = hw->max_packet_count; in dwc2_set_default_params()
490 p->max_transfer_size = hw->max_transfer_size; in dwc2_set_default_params()
491 p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT; in dwc2_set_default_params()
492 p->ref_clk_per = 33333; in dwc2_set_default_params()
493 p->sof_cnt_wkup_alert = 100; in dwc2_set_default_params()
495 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || in dwc2_set_default_params()
496 (hsotg->dr_mode == USB_DR_MODE_OTG)) { in dwc2_set_default_params()
497 p->host_dma = dma_capable; in dwc2_set_default_params()
498 p->dma_desc_enable = false; in dwc2_set_default_params()
499 p->dma_desc_fs_enable = false; in dwc2_set_default_params()
500 p->host_support_fs_ls_low_power = false; in dwc2_set_default_params()
501 p->host_ls_low_power_phy_clk = false; in dwc2_set_default_params()
502 p->host_channels = hw->host_channels; in dwc2_set_default_params()
503 p->host_rx_fifo_size = hw->rx_fifo_size; in dwc2_set_default_params()
504 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size; in dwc2_set_default_params()
505 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size; in dwc2_set_default_params()
508 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || in dwc2_set_default_params()
509 (hsotg->dr_mode == USB_DR_MODE_OTG)) { in dwc2_set_default_params()
510 p->g_dma = dma_capable; in dwc2_set_default_params()
511 p->g_dma_desc = hw->dma_desc_enable; in dwc2_set_default_params()
516 * gadget driver. These defaults have been hard-coded in dwc2_set_default_params()
519 * auto-detect if the hardware does not support the in dwc2_set_default_params()
522 p->g_rx_fifo_size = 2048; in dwc2_set_default_params()
523 p->g_np_tx_fifo_size = 1024; in dwc2_set_default_params()
529 * dwc2_get_device_properties() - Read in device properties.
537 struct dwc2_core_params *p = &hsotg->params; in dwc2_get_device_properties()
540 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || in dwc2_get_device_properties()
541 (hsotg->dr_mode == USB_DR_MODE_OTG)) { in dwc2_get_device_properties()
542 device_property_read_u32(hsotg->dev, "g-rx-fifo-size", in dwc2_get_device_properties()
543 &p->g_rx_fifo_size); in dwc2_get_device_properties()
545 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size", in dwc2_get_device_properties()
546 &p->g_np_tx_fifo_size); in dwc2_get_device_properties()
548 num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size"); in dwc2_get_device_properties()
551 memset(p->g_tx_fifo_size, 0, in dwc2_get_device_properties()
552 sizeof(p->g_tx_fifo_size)); in dwc2_get_device_properties()
553 device_property_read_u32_array(hsotg->dev, in dwc2_get_device_properties()
554 "g-tx-fifo-size", in dwc2_get_device_properties()
555 &p->g_tx_fifo_size[1], in dwc2_get_device_properties()
559 of_usb_update_otg_caps(hsotg->dev->of_node, &p->otg_caps); in dwc2_get_device_properties()
562 p->oc_disable = of_property_read_bool(hsotg->dev->of_node, "disable-over-current"); in dwc2_get_device_properties()
569 if (hsotg->params.otg_caps.hnp_support && hsotg->params.otg_caps.srp_support) { in dwc2_check_param_otg_cap()
570 /* check HNP && SRP capable */ in dwc2_check_param_otg_cap()
571 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) in dwc2_check_param_otg_cap()
573 } else if (!hsotg->params.otg_caps.hnp_support) { in dwc2_check_param_otg_cap()
574 /* check SRP only capable */ in dwc2_check_param_otg_cap()
575 if (hsotg->params.otg_caps.srp_support) { in dwc2_check_param_otg_cap()
576 switch (hsotg->hw_params.op_mode) { in dwc2_check_param_otg_cap()
587 /* else: NO HNP && NO SRP capable: always valid */ in dwc2_check_param_otg_cap()
602 hs_phy_type = hsotg->hw_params.hs_phy_type; in dwc2_check_param_phy_type()
603 fs_phy_type = hsotg->hw_params.fs_phy_type; in dwc2_check_param_phy_type()
605 switch (hsotg->params.phy_type) { in dwc2_check_param_phy_type()
631 int phy_type = hsotg->params.phy_type; in dwc2_check_param_speed()
632 int speed = hsotg->params.speed; in dwc2_check_param_speed()
636 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) && in dwc2_check_param_speed()
655 int param = hsotg->params.phy_utmi_width; in dwc2_check_param_phy_utmi_width()
656 int width = hsotg->hw_params.utmi_phy_data_width; in dwc2_check_param_phy_utmi_width()
676 int param = hsotg->params.power_down; in dwc2_check_param_power_down()
682 if (hsotg->hw_params.power_optimized) in dwc2_check_param_power_down()
684 dev_dbg(hsotg->dev, in dwc2_check_param_power_down()
689 if (hsotg->hw_params.hibernation) in dwc2_check_param_power_down()
691 dev_dbg(hsotg->dev, in dwc2_check_param_power_down()
696 dev_err(hsotg->dev, in dwc2_check_param_power_down()
703 hsotg->params.power_down = param; in dwc2_check_param_power_down()
715 min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4; in dwc2_check_param_tx_fifo_sizes()
718 total += hsotg->params.g_tx_fifo_size[fifo]; in dwc2_check_param_tx_fifo_sizes()
721 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n", in dwc2_check_param_tx_fifo_sizes()
727 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo]; in dwc2_check_param_tx_fifo_sizes()
729 if (hsotg->params.g_tx_fifo_size[fifo] < min || in dwc2_check_param_tx_fifo_sizes()
730 hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) { in dwc2_check_param_tx_fifo_sizes()
731 dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n", in dwc2_check_param_tx_fifo_sizes()
733 hsotg->params.g_tx_fifo_size[fifo]); in dwc2_check_param_tx_fifo_sizes()
734 hsotg->params.g_tx_fifo_size[fifo] = dptxfszn; in dwc2_check_param_tx_fifo_sizes()
740 if ((int)(hsotg->params._param) < (_min) || \
741 (hsotg->params._param) > (_max)) { \
742 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
743 __func__, #_param, hsotg->params._param); \
744 hsotg->params._param = (_def); \
749 if (hsotg->params._param && !(_check)) { \
750 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
751 __func__, #_param, hsotg->params._param); \
752 hsotg->params._param = false; \
758 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_check_params()
759 struct dwc2_core_params *p = &hsotg->params; in dwc2_check_params()
760 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); in dwc2_check_params()
767 CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo); in dwc2_check_params()
768 CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo); in dwc2_check_params()
769 CHECK_BOOL(i2c_enable, hw->i2c_enable); in dwc2_check_params()
770 CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en); in dwc2_check_params()
771 CHECK_BOOL(acg_enable, hw->acg_enable); in dwc2_check_params()
772 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a)); in dwc2_check_params()
773 CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a)); in dwc2_check_params()
774 CHECK_BOOL(lpm, hw->lpm_mode); in dwc2_check_params()
775 CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm); in dwc2_check_params()
776 CHECK_BOOL(besl, hsotg->params.lpm); in dwc2_check_params()
777 CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)); in dwc2_check_params()
778 CHECK_BOOL(hird_threshold_en, hsotg->params.lpm); in dwc2_check_params()
779 CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0); in dwc2_check_params()
780 CHECK_BOOL(service_interval, hw->service_interval_mode); in dwc2_check_params()
782 15, hw->max_packet_count, in dwc2_check_params()
783 hw->max_packet_count); in dwc2_check_params()
785 2047, hw->max_transfer_size, in dwc2_check_params()
786 hw->max_transfer_size); in dwc2_check_params()
788 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || in dwc2_check_params()
789 (hsotg->dr_mode == USB_DR_MODE_OTG)) { in dwc2_check_params()
791 CHECK_BOOL(dma_desc_enable, p->host_dma); in dwc2_check_params()
792 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable); in dwc2_check_params()
794 p->phy_type == DWC2_PHY_TYPE_PARAM_FS); in dwc2_check_params()
796 1, hw->host_channels, in dwc2_check_params()
797 hw->host_channels); in dwc2_check_params()
799 16, hw->rx_fifo_size, in dwc2_check_params()
800 hw->rx_fifo_size); in dwc2_check_params()
802 16, hw->host_nperio_tx_fifo_size, in dwc2_check_params()
803 hw->host_nperio_tx_fifo_size); in dwc2_check_params()
805 16, hw->host_perio_tx_fifo_size, in dwc2_check_params()
806 hw->host_perio_tx_fifo_size); in dwc2_check_params()
809 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || in dwc2_check_params()
810 (hsotg->dr_mode == USB_DR_MODE_OTG)) { in dwc2_check_params()
812 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable)); in dwc2_check_params()
814 16, hw->rx_fifo_size, in dwc2_check_params()
815 hw->rx_fifo_size); in dwc2_check_params()
817 16, hw->dev_nperio_tx_fifo_size, in dwc2_check_params()
818 hw->dev_nperio_tx_fifo_size); in dwc2_check_params()
830 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_get_host_hwparams()
834 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) in dwc2_get_host_hwparams()
842 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> in dwc2_get_host_hwparams()
844 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> in dwc2_get_host_hwparams()
855 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_get_dev_hwparams()
859 if (hsotg->dr_mode == USB_DR_MODE_HOST) in dwc2_get_dev_hwparams()
869 hw->g_tx_fifo_size[fifo] = in dwc2_get_dev_hwparams()
874 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> in dwc2_get_dev_hwparams()
879 * dwc2_get_hwparams() - During device initialization, read various hardware
887 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_get_hwparams()
899 hw->dev_ep_dirs = hwcfg1; in dwc2_get_hwparams()
902 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> in dwc2_get_hwparams()
904 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> in dwc2_get_hwparams()
906 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); in dwc2_get_hwparams()
907 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> in dwc2_get_hwparams()
909 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> in dwc2_get_hwparams()
911 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> in dwc2_get_hwparams()
913 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> in dwc2_get_hwparams()
915 hw->nperio_tx_q_depth = in dwc2_get_hwparams()
918 hw->host_perio_tx_q_depth = in dwc2_get_hwparams()
921 hw->dev_token_q_depth = in dwc2_get_hwparams()
928 hw->max_transfer_size = (1 << (width + 11)) - 1; in dwc2_get_hwparams()
931 hw->max_packet_count = (1 << (width + 4)) - 1; in dwc2_get_hwparams()
932 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); in dwc2_get_hwparams()
933 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> in dwc2_get_hwparams()
935 hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN); in dwc2_get_hwparams()
938 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); in dwc2_get_hwparams()
939 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> in dwc2_get_hwparams()
941 hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >> in dwc2_get_hwparams()
943 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); in dwc2_get_hwparams()
944 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); in dwc2_get_hwparams()
945 hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER); in dwc2_get_hwparams()
946 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> in dwc2_get_hwparams()
948 hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED); in dwc2_get_hwparams()
949 hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED); in dwc2_get_hwparams()
950 hw->service_interval_mode = !!(hwcfg4 & in dwc2_get_hwparams()
954 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> in dwc2_get_hwparams()
977 match = of_match_device(dwc2_of_match_table, hsotg->dev); in dwc2_init_params()
978 if (match && match->data) { in dwc2_init_params()
979 set_params = match->data; in dwc2_init_params()
985 amatch = acpi_match_device(dwc2_acpi_match, hsotg->dev); in dwc2_init_params()
986 if (amatch && amatch->driver_data) { in dwc2_init_params()
987 set_params = (set_params_cb)amatch->driver_data; in dwc2_init_params()
990 pmatch = pci_match_id(dwc2_pci_ids, to_pci_dev(hsotg->dev->parent)); in dwc2_init_params()
992 if (pmatch && pmatch->driver_data) { in dwc2_init_params()
993 set_params = (set_params_cb)pmatch->driver_data; in dwc2_init_params()