Lines Matching +full:full +full:- +full:speed
1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * hcd.h - DesignWare HS OTG Controller host-mode declarations
5 * Copyright (C) 2004-2013 Synopsys, Inc.
24 * struct dwc2_host_chan - Software host channel descriptor
30 * @speed: Device speed. One of the following values:
31 * - USB_SPEED_LOW
32 * - USB_SPEED_FULL
33 * - USB_SPEED_HIGH
35 * - USB_ENDPOINT_XFER_CONTROL: 0
36 * - USB_ENDPOINT_XFER_ISOC: 1
37 * - USB_ENDPOINT_XFER_BULK: 2
38 * - USB_ENDPOINT_XFER_INTR: 3
44 * 3: MDATA (non-Control EP),
57 * @error_state: True if the error count for this transaction is non-zero
66 * @hub_addr: Address of high speed hub for the split
67 * @hub_port: Port of the low/full speed device for the split
69 * - DWC2_HCSPLT_XACTPOS_MID
70 * - DWC2_HCSPLT_XACTPOS_BEGIN
71 * - DWC2_HCSPLT_XACTPOS_END
72 * - DWC2_HCSPLT_XACTPOS_ALL
75 * @schinfo: Scheduling micro-frame bitmap
95 unsigned speed:4; member
196 * struct dwc2_tt - dwc2 data associated with a usb_tt
213 * struct dwc2_hs_transfer_time - Info about a transfer on the high speed bus.
229 * struct dwc2_qh - Software queue head structure
233 * - USB_ENDPOINT_XFER_CONTROL
234 * - USB_ENDPOINT_XFER_BULK
235 * - USB_ENDPOINT_XFER_INT
236 * - USB_ENDPOINT_XFER_ISOC
240 * @dev_speed: Device speed. One of the following values:
241 * - USB_SPEED_LOW
242 * - USB_SPEED_FULL
243 * - USB_SPEED_HIGH
245 * non-controltransfers. Ignored for control transfers.
247 * - DWC2_HC_PID_DATA0
248 * - DWC2_HC_PID_DATA1
250 * @do_split: Full/low speed endpoint on high-speed hub requires split
256 * the host is high speed and the device is low speed this
262 * host is in high speed mode this will be a uframe. If
263 * the host is in low speed mode this will be a full frame.
269 * Always >= 1 unless the host is in low/full speed mode.
270 * @hs_transfers: Transfers that are scheduled as seen by the high speed
271 * bus. Not used if host is in low or full speed mode (but
272 * note that it IS USED if the device is low or full speed
273 * as long as the HOST is in high speed mode).
274 * @ls_start_schedule_slice: Start time (in slices) on the low speed bus
278 * speed. Note that this is in "schedule slice" which
282 * is not dword-aligned
286 * @qh_list_entry: Entry for QH in either the periodic or non-periodic
295 * @wait_timer: Timer used to wait before re-queuing.
300 * @schedule_low_speed: True if we have a low/full speed component (either the
301 * host is in low/full speed mode or do_split).
302 * @want_wait: We should wait before re-queuing; only matters for non-
309 * be entered in either the non-periodic or periodic schedule.
354 * struct dwc2_qtd - Software queue transfer descriptor (QTD)
362 * - DWC2_HC_PID_DATA0
363 * - DWC2_HC_PID_DATA1
366 * @isoc_split_pos: Position of the ISOC split in full/low speed
396 * non-periodic or periodic schedule for execution. When a QTD is chosen for
434 return (struct usb_hcd *)hsotg->priv; in dwc2_hsotg_to_hcd()
441 * channel is re-assigned. In fact, subsequent handling may cause crashes
472 return pipe->ep_num; in dwc2_hcd_get_ep_num()
477 return pipe->pipe_type; in dwc2_hcd_get_pipe_type()
482 return pipe->maxp; in dwc2_hcd_get_maxp()
487 return pipe->maxp_mult; in dwc2_hcd_get_maxp_mult()
492 return pipe->dev_addr; in dwc2_hcd_get_dev_addr()
497 return pipe->pipe_type == USB_ENDPOINT_XFER_ISOC; in dwc2_hcd_is_pipe_isoc()
502 return pipe->pipe_type == USB_ENDPOINT_XFER_INT; in dwc2_hcd_is_pipe_int()
507 return pipe->pipe_type == USB_ENDPOINT_XFER_BULK; in dwc2_hcd_is_pipe_bulk()
512 return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL; in dwc2_hcd_is_pipe_control()
517 return pipe->pipe_dir == USB_DIR_IN; in dwc2_hcd_is_pipe_in()
554 list_del(&qtd->qtd_list_entry); in dwc2_hcd_qtd_unlink_and_free()
569 /* Check if QH is non-periodic */
571 ((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \
572 (_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL)
582 return hc->ep_type == USB_ENDPOINT_XFER_BULK || in dbg_hc()
583 hc->ep_type == USB_ENDPOINT_XFER_CONTROL; in dbg_hc()
588 return qh->ep_type == USB_ENDPOINT_XFER_BULK || in dbg_qh()
589 qh->ep_type == USB_ENDPOINT_XFER_CONTROL; in dbg_qh()
594 return usb_pipetype(urb->pipe) == PIPE_BULK || in dbg_urb()
595 usb_pipetype(urb->pipe) == PIPE_CONTROL; in dbg_urb()
608 u16 diff = fr_idx1 - fr_idx2; in dwc2_frame_idx_num_gt()
621 return ((frame2 - frame1) & HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM >> 1); in dwc2_frame_num_le()
632 ((frame1 - frame2) & HFNUM_MAX_FRNUM) < (HFNUM_MAX_FRNUM >> 1); in dwc2_frame_num_gt()
646 return (frame + HFNUM_MAX_FRNUM + 1 - dec) & HFNUM_MAX_FRNUM; in dwc2_frame_num_dec()
671 return dwc2_urb->status; in dwc2_hcd_urb_get_status()
677 return dwc2_urb->actual_length; in dwc2_hcd_urb_get_actual_length()
682 return dwc2_urb->error_count; in dwc2_hcd_urb_get_error_count()
689 dwc2_urb->iso_descs[desc_num].offset = offset; in dwc2_hcd_urb_set_iso_desc_params()
690 dwc2_urb->iso_descs[desc_num].length = length; in dwc2_hcd_urb_set_iso_desc_params()
696 return dwc2_urb->iso_descs[desc_num].status; in dwc2_hcd_urb_get_iso_desc_status()
702 return dwc2_urb->iso_descs[desc_num].actual_length; in dwc2_hcd_urb_get_iso_desc_actual_length()
708 struct dwc2_qh *qh = ep->hcpriv; in dwc2_hcd_is_bandwidth_allocated()
710 if (qh && !list_empty(&qh->qh_list_entry)) in dwc2_hcd_is_bandwidth_allocated()
719 struct dwc2_qh *qh = ep->hcpriv; in dwc2_hcd_get_ep_bandwidth()
726 return qh->host_us; in dwc2_hcd_get_ep_bandwidth()
736 * dwc2_handle_hcd_intr() - Called on every hardware interrupt
746 * dwc2_hcd_stop() - Halts the DWC_otg host mode operation
753 * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host,
761 * dwc2_hcd_dump_state() - Dumps hsotg state