Lines Matching +full:0 +full:x1700
14 #define MAX_U32 (~(u32)0)
15 #define MPHY_TX_FSM_STATE 0x41
16 #define TX_FSM_HIBERN8 0x1
24 #define UFS_HW_VER_STEP_MASK GENMASK(15, 0)
34 REG_UFS_SYS1CLK_1US = 0xC0,
35 REG_UFS_TX_SYMBOL_CLK_NS_US = 0xC4,
36 REG_UFS_LOCAL_PORT_ID_REG = 0xC8,
37 REG_UFS_PA_ERR_CODE = 0xCC,
39 REG_UFS_PARAM0 = 0xD0,
41 REG_UFS_CFG0 = 0xD8,
42 REG_UFS_CFG1 = 0xDC,
43 REG_UFS_CFG2 = 0xE0,
44 REG_UFS_HW_VERSION = 0xE4,
46 UFS_TEST_BUS = 0xE8,
47 UFS_TEST_BUS_CTRL_0 = 0xEC,
48 UFS_TEST_BUS_CTRL_1 = 0xF0,
49 UFS_TEST_BUS_CTRL_2 = 0xF4,
50 UFS_UNIPRO_CFG = 0xF8,
54 * added in HW Version 3.0.0
56 UFS_AH8_CFG = 0xFC,
58 REG_UFS_CFG3 = 0x271C,
63 UFS_DBG_RD_REG_UAWM = 0x100,
64 UFS_DBG_RD_REG_UARM = 0x200,
65 UFS_DBG_RD_REG_TXUC = 0x300,
66 UFS_DBG_RD_REG_RXUC = 0x400,
67 UFS_DBG_RD_REG_DFC = 0x500,
68 UFS_DBG_RD_REG_TRLUT = 0x600,
69 UFS_DBG_RD_REG_TMRLUT = 0x700,
70 UFS_UFS_DBG_RD_REG_OCSC = 0x800,
72 UFS_UFS_DBG_RD_DESC_RAM = 0x1500,
73 UFS_UFS_DBG_RD_PRDT_RAM = 0x1700,
74 UFS_UFS_DBG_RD_RESP_RAM = 0x1800,
75 UFS_UFS_DBG_RD_EDTL_RAM = 0x1900,
79 UFS_MEM_CQIS_VS = 0x8,
82 #define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x) (0x000 + x)
83 #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x)
89 #define QUNIPRO_SEL BIT(0)
97 #define UFS_PHY_RESET_DISABLE 0
100 #define UAWM_HW_CGC_EN BIT(0)
114 #define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 bits wide */
122 #define OFFSET_CLK_NS_REG 0xa
125 #define MASK_TX_SYMBOL_CLK_1US_REG GENMASK(9, 0)
129 #define PA_VS_CONFIG_REG1 0x9000
130 #define DME_VS_CORE_CLK_CTRL 0xD002
133 #define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK 0xFF
191 #define UFS_QCOM_CAP_QUNIPRO 0x1
197 #define UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE 0x2
238 if (host->hw_ver.major <= 0x02) in ufs_qcom_get_debug_reg_offset()