Lines Matching refs:TCR
363 #define TCR 0x82 /* tx control */ macro
1321 value = rd_reg16(info, TCR); in set_break()
1326 wr_reg16(info, TCR, value); in set_break()
2202 unsigned short val = rd_reg16(info, TCR); in isr_txeom()
2203 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ in isr_txeom()
2204 wr_reg16(info, TCR, val); /* clear reset bit */ in isr_txeom()
2780 val = rd_reg16(info, TCR); in set_interface()
2785 wr_reg16(info, TCR, val); in set_interface()
3918 wr_reg16(info, TCR, in tx_start()
3919 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2)); in tx_start()
3962 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */ in tx_stop()
3963 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ in tx_stop()
4049 wr_reg16(info, TCR, val); in async_mode()
4211 wr_reg16(info, TCR, val); in sync_mode()
4373 tcr = rd_reg16(info, TCR); in tx_set_idle()
4383 wr_reg16(info, TCR, tcr); in tx_set_idle()
4873 wr_reg16(info, TCR, in irq_test()
4874 (unsigned short)(rd_reg16(info, TCR) | BIT1)); in irq_test()