Lines Matching +full:rs485 +full:- +full:rx +full:- +full:during +full:- +full:tx +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0
9 * Inspired by st-asc.c from STMicroelectronics (c)
15 #include <linux/dma-direction.h>
17 #include <linux/dma-mapping.h>
36 #include "stm32-usart.h"
120 val = readl_relaxed(port->membase + reg); in stm32_usart_set_bits()
122 writel_relaxed(val, port->membase + reg); in stm32_usart_set_bits()
129 val = readl_relaxed(port->membase + reg); in stm32_usart_clr_bits()
131 writel_relaxed(val, port->membase + reg); in stm32_usart_clr_bits()
137 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tx_empty()
139 if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC) in stm32_usart_tx_empty()
148 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_rs485_rts_enable()
150 if (stm32_port->hw_flow_control || in stm32_usart_rs485_rts_enable()
151 !(rs485conf->flags & SER_RS485_ENABLED)) in stm32_usart_rs485_rts_enable()
154 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_usart_rs485_rts_enable()
155 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_rs485_rts_enable()
156 stm32_port->port.mctrl | TIOCM_RTS); in stm32_usart_rs485_rts_enable()
158 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_rs485_rts_enable()
159 stm32_port->port.mctrl & ~TIOCM_RTS); in stm32_usart_rs485_rts_enable()
166 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_rs485_rts_disable()
168 if (stm32_port->hw_flow_control || in stm32_usart_rs485_rts_disable()
169 !(rs485conf->flags & SER_RS485_ENABLED)) in stm32_usart_rs485_rts_disable()
172 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_usart_rs485_rts_disable()
173 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_rs485_rts_disable()
174 stm32_port->port.mctrl & ~TIOCM_RTS); in stm32_usart_rs485_rts_disable()
176 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_rs485_rts_disable()
177 stm32_port->port.mctrl | TIOCM_RTS); in stm32_usart_rs485_rts_disable()
222 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_config_rs485()
223 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_config_rs485()
227 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_config_rs485()
229 if (port->rs485_rx_during_tx_gpio) in stm32_usart_config_rs485()
230 gpiod_set_value_cansleep(port->rs485_rx_during_tx_gpio, in stm32_usart_config_rs485()
231 !!(rs485conf->flags & SER_RS485_RX_DURING_TX)); in stm32_usart_config_rs485()
233 rs485conf->flags |= SER_RS485_RX_DURING_TX; in stm32_usart_config_rs485()
235 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_usart_config_rs485()
236 cr1 = readl_relaxed(port->membase + ofs->cr1); in stm32_usart_config_rs485()
237 cr3 = readl_relaxed(port->membase + ofs->cr3); in stm32_usart_config_rs485()
238 usartdiv = readl_relaxed(port->membase + ofs->brr); in stm32_usart_config_rs485()
246 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); in stm32_usart_config_rs485()
248 rs485conf->delay_rts_before_send, in stm32_usart_config_rs485()
249 rs485conf->delay_rts_after_send, in stm32_usart_config_rs485()
252 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) in stm32_usart_config_rs485()
257 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_usart_config_rs485()
258 writel_relaxed(cr1, port->membase + ofs->cr1); in stm32_usart_config_rs485()
260 stm32_usart_clr_bits(port, ofs->cr3, in stm32_usart_config_rs485()
262 stm32_usart_clr_bits(port, ofs->cr1, in stm32_usart_config_rs485()
266 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_config_rs485()
280 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_init_rs485()
282 rs485conf->flags = 0; in stm32_usart_init_rs485()
283 rs485conf->delay_rts_before_send = 0; in stm32_usart_init_rs485()
284 rs485conf->delay_rts_after_send = 0; in stm32_usart_init_rs485()
286 if (!pdev->dev.of_node) in stm32_usart_init_rs485()
287 return -ENODEV; in stm32_usart_init_rs485()
294 return stm32_port->rx_ch ? stm32_port->rx_dma_busy : false; in stm32_usart_rx_dma_started()
299 dmaengine_terminate_async(stm32_port->rx_ch); in stm32_usart_rx_dma_terminate()
300 stm32_port->rx_dma_busy = false; in stm32_usart_rx_dma_terminate()
310 struct uart_port *port = &stm32_port->port; in stm32_usart_dma_pause_resume()
315 return -EPERM; in stm32_usart_dma_pause_resume()
317 dma_status = dmaengine_tx_status(chan, chan->cookie, NULL); in stm32_usart_dma_pause_resume()
319 return -EAGAIN; in stm32_usart_dma_pause_resume()
323 dev_err(port->dev, "DMA failed with error code: %d\n", ret); in stm32_usart_dma_pause_resume()
331 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->rx_ch, in stm32_usart_rx_dma_pause()
339 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->rx_ch, in stm32_usart_rx_dma_resume()
349 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_pending_rx_pio()
351 *sr = readl_relaxed(port->membase + ofs->isr); in stm32_usart_pending_rx_pio()
358 /* Handle only RX data errors when using DMA */ in stm32_usart_pending_rx_pio()
369 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_get_char_pio()
372 c = readl_relaxed(port->membase + ofs->rdr); in stm32_usart_get_char_pio()
374 c &= stm32_port->rdr_mask; in stm32_usart_get_char_pio()
382 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_receive_chars_pio()
396 * and clear status bits of the next rx data. in stm32_usart_receive_chars_pio()
400 * cleared by the sequence [read SR - read DR]. in stm32_usart_receive_chars_pio()
402 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) in stm32_usart_receive_chars_pio()
404 port->membase + ofs->icr); in stm32_usart_receive_chars_pio()
407 port->icount.rx++; in stm32_usart_receive_chars_pio()
411 port->icount.overrun++; in stm32_usart_receive_chars_pio()
413 port->icount.parity++; in stm32_usart_receive_chars_pio()
417 port->icount.brk++; in stm32_usart_receive_chars_pio()
421 port->icount.frame++; in stm32_usart_receive_chars_pio()
425 sr &= port->read_status_mask; in stm32_usart_receive_chars_pio()
448 struct tty_port *ttyport = &stm32_port->port.state->port; in stm32_usart_push_buffer_dma()
452 dma_start = stm32_port->rx_buf + (RX_BUF_L - stm32_port->last_res); in stm32_usart_push_buffer_dma()
459 if (!(stm32_port->rdr_mask == (BIT(8) - 1))) in stm32_usart_push_buffer_dma()
461 *(dma_start + i) &= stm32_port->rdr_mask; in stm32_usart_push_buffer_dma()
464 port->icount.rx += dma_count; in stm32_usart_push_buffer_dma()
466 port->icount.buf_overrun++; in stm32_usart_push_buffer_dma()
467 stm32_port->last_res -= dma_count; in stm32_usart_push_buffer_dma()
468 if (stm32_port->last_res == 0) in stm32_usart_push_buffer_dma()
469 stm32_port->last_res = RX_BUF_L; in stm32_usart_push_buffer_dma()
478 if (stm32_port->rx_dma_state.residue > stm32_port->last_res) { in stm32_usart_receive_chars_dma()
480 dma_size = stm32_port->last_res; in stm32_usart_receive_chars_dma()
485 dma_size = stm32_port->last_res - stm32_port->rx_dma_state.residue; in stm32_usart_receive_chars_dma()
495 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_receive_chars()
501 rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch, in stm32_usart_receive_chars()
502 stm32_port->rx_ch->cookie, in stm32_usart_receive_chars()
503 &stm32_port->rx_dma_state); in stm32_usart_receive_chars()
508 sr = readl_relaxed(port->membase + ofs->isr); in stm32_usart_receive_chars()
511 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_usart_receive_chars()
517 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_usart_receive_chars()
520 /* Disable RX DMA */ in stm32_usart_receive_chars()
523 dev_dbg(port->dev, "DMA error, fallback to irq mode\n"); in stm32_usart_receive_chars()
536 struct tty_port *tport = &port->state->port; in stm32_usart_rx_dma_complete()
540 spin_lock_irqsave(&port->lock, flags); in stm32_usart_rx_dma_complete()
554 if (stm32_port->throttled) in stm32_usart_rx_dma_start_or_resume()
557 if (stm32_port->rx_dma_busy) { in stm32_usart_rx_dma_start_or_resume()
558 rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch, in stm32_usart_rx_dma_start_or_resume()
559 stm32_port->rx_ch->cookie, in stm32_usart_rx_dma_start_or_resume()
567 dev_err(port->dev, "DMA failed : status error.\n"); in stm32_usart_rx_dma_start_or_resume()
571 stm32_port->rx_dma_busy = true; in stm32_usart_rx_dma_start_or_resume()
573 stm32_port->last_res = RX_BUF_L; in stm32_usart_rx_dma_start_or_resume()
575 desc = dmaengine_prep_dma_cyclic(stm32_port->rx_ch, in stm32_usart_rx_dma_start_or_resume()
576 stm32_port->rx_dma_buf, in stm32_usart_rx_dma_start_or_resume()
581 dev_err(port->dev, "rx dma prep cyclic failed\n"); in stm32_usart_rx_dma_start_or_resume()
582 stm32_port->rx_dma_busy = false; in stm32_usart_rx_dma_start_or_resume()
583 return -ENODEV; in stm32_usart_rx_dma_start_or_resume()
586 desc->callback = stm32_usart_rx_dma_complete; in stm32_usart_rx_dma_start_or_resume()
587 desc->callback_param = port; in stm32_usart_rx_dma_start_or_resume()
592 dmaengine_terminate_sync(stm32_port->rx_ch); in stm32_usart_rx_dma_start_or_resume()
593 stm32_port->rx_dma_busy = false; in stm32_usart_rx_dma_start_or_resume()
598 dma_async_issue_pending(stm32_port->rx_ch); in stm32_usart_rx_dma_start_or_resume()
605 dmaengine_terminate_async(stm32_port->tx_ch); in stm32_usart_tx_dma_terminate()
606 stm32_port->tx_dma_busy = false; in stm32_usart_tx_dma_terminate()
618 return stm32_port->tx_dma_busy; in stm32_usart_tx_dma_started()
623 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->tx_ch, in stm32_usart_tx_dma_pause()
631 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->tx_ch, in stm32_usart_tx_dma_resume()
646 spin_lock_irqsave(&port->lock, flags); in stm32_usart_tx_dma_complete()
648 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_tx_dma_complete()
654 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tx_interrupt_enable()
657 * Enables TX FIFO threashold irq when FIFO is enabled, in stm32_usart_tx_interrupt_enable()
658 * or TX empty irq when FIFO is disabled in stm32_usart_tx_interrupt_enable()
660 if (stm32_port->fifoen && stm32_port->txftcfg >= 0) in stm32_usart_tx_interrupt_enable()
661 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); in stm32_usart_tx_interrupt_enable()
663 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE); in stm32_usart_tx_interrupt_enable()
669 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tc_interrupt_enable()
671 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TCIE); in stm32_usart_tc_interrupt_enable()
677 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tx_interrupt_disable()
679 if (stm32_port->fifoen && stm32_port->txftcfg >= 0) in stm32_usart_tx_interrupt_disable()
680 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); in stm32_usart_tx_interrupt_disable()
682 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); in stm32_usart_tx_interrupt_disable()
688 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tc_interrupt_disable()
690 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TCIE); in stm32_usart_tc_interrupt_disable()
696 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_transmit_chars_pio()
697 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_transmit_chars_pio()
701 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) in stm32_usart_transmit_chars_pio()
703 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); in stm32_usart_transmit_chars_pio()
717 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_transmit_chars_dma()
724 if (ret < 0 && ret != -EAGAIN) in stm32_usart_transmit_chars_dma()
734 if (xmit->tail < xmit->head) { in stm32_usart_transmit_chars_dma()
735 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); in stm32_usart_transmit_chars_dma()
737 size_t one = UART_XMIT_SIZE - xmit->tail; in stm32_usart_transmit_chars_dma()
742 two = count - one; in stm32_usart_transmit_chars_dma()
744 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); in stm32_usart_transmit_chars_dma()
746 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); in stm32_usart_transmit_chars_dma()
749 desc = dmaengine_prep_slave_single(stm32port->tx_ch, in stm32_usart_transmit_chars_dma()
750 stm32port->tx_dma_buf, in stm32_usart_transmit_chars_dma()
764 stm32port->tx_dma_busy = true; in stm32_usart_transmit_chars_dma()
766 desc->callback = stm32_usart_tx_dma_complete; in stm32_usart_transmit_chars_dma()
767 desc->callback_param = port; in stm32_usart_transmit_chars_dma()
769 /* Push current DMA TX transaction in the pending queue */ in stm32_usart_transmit_chars_dma()
773 dev_err(port->dev, "DMA failed with error code: %d\n", ret); in stm32_usart_transmit_chars_dma()
778 /* Issue pending DMA TX requests */ in stm32_usart_transmit_chars_dma()
779 dma_async_issue_pending(stm32port->tx_ch); in stm32_usart_transmit_chars_dma()
792 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_transmit_chars()
793 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_transmit_chars()
797 if (!stm32_port->hw_flow_control && in stm32_usart_transmit_chars()
798 port->rs485.flags & SER_RS485_ENABLED && in stm32_usart_transmit_chars()
799 (port->x_char || in stm32_usart_transmit_chars()
805 if (port->x_char) { in stm32_usart_transmit_chars()
811 readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, in stm32_usart_transmit_chars()
816 dev_warn(port->dev, "1 character may be erased\n"); in stm32_usart_transmit_chars()
818 writel_relaxed(port->x_char, port->membase + ofs->tdr); in stm32_usart_transmit_chars()
819 port->x_char = 0; in stm32_usart_transmit_chars()
820 port->icount.tx++; in stm32_usart_transmit_chars()
832 if (ofs->icr == UNDEF_REG) in stm32_usart_transmit_chars()
833 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC); in stm32_usart_transmit_chars()
835 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); in stm32_usart_transmit_chars()
837 if (stm32_port->tx_ch) in stm32_usart_transmit_chars()
847 if (!stm32_port->hw_flow_control && in stm32_usart_transmit_chars()
848 port->rs485.flags & SER_RS485_ENABLED) { in stm32_usart_transmit_chars()
857 struct tty_port *tport = &port->state->port; in stm32_usart_interrupt()
859 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_interrupt()
863 sr = readl_relaxed(port->membase + ofs->isr); in stm32_usart_interrupt()
865 if (!stm32_port->hw_flow_control && in stm32_usart_interrupt()
866 port->rs485.flags & SER_RS485_ENABLED && in stm32_usart_interrupt()
872 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) in stm32_usart_interrupt()
874 port->membase + ofs->icr); in stm32_usart_interrupt()
876 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) { in stm32_usart_interrupt()
879 port->membase + ofs->icr); in stm32_usart_interrupt()
880 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); in stm32_usart_interrupt()
881 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) in stm32_usart_interrupt()
882 pm_wakeup_event(tport->tty->dev, 0); in stm32_usart_interrupt()
886 * rx errors in dma mode has to be handled ASAP to avoid overrun as the DMA request in stm32_usart_interrupt()
887 * line has been masked by HW and rx data are stacking in FIFO. in stm32_usart_interrupt()
889 if (!stm32_port->throttled) { in stm32_usart_interrupt()
892 spin_lock(&port->lock); in stm32_usart_interrupt()
900 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) { in stm32_usart_interrupt()
901 spin_lock(&port->lock); in stm32_usart_interrupt()
903 spin_unlock(&port->lock); in stm32_usart_interrupt()
906 /* Receiver timeout irq for DMA RX */ in stm32_usart_interrupt()
907 if (stm32_usart_rx_dma_started(stm32_port) && !stm32_port->throttled) { in stm32_usart_interrupt()
908 spin_lock(&port->lock); in stm32_usart_interrupt()
921 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_set_mctrl()
923 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) in stm32_usart_set_mctrl()
924 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE); in stm32_usart_set_mctrl()
926 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE); in stm32_usart_set_mctrl()
928 mctrl_gpio_set(stm32_port->gpios, mctrl); in stm32_usart_set_mctrl()
939 return mctrl_gpio_get(stm32_port->gpios, &ret); in stm32_usart_get_mctrl()
944 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios); in stm32_usart_enable_ms()
949 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios); in stm32_usart_disable_ms()
968 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_start_tx()
970 if (uart_circ_empty(xmit) && !port->x_char) { in stm32_usart_start_tx()
985 if (stm32_port->tx_ch) in stm32_usart_flush_buffer()
993 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_throttle()
996 spin_lock_irqsave(&port->lock, flags); in stm32_usart_throttle()
999 * Pause DMA transfer, so the RX data gets queued into the FIFO. in stm32_usart_throttle()
1000 * Hardware flow control is triggered when RX FIFO is full. in stm32_usart_throttle()
1004 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); in stm32_usart_throttle()
1005 if (stm32_port->cr3_irq) in stm32_usart_throttle()
1006 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_usart_throttle()
1008 stm32_port->throttled = true; in stm32_usart_throttle()
1009 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_throttle()
1016 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_unthrottle()
1019 spin_lock_irqsave(&port->lock, flags); in stm32_usart_unthrottle()
1020 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq); in stm32_usart_unthrottle()
1021 if (stm32_port->cr3_irq) in stm32_usart_unthrottle()
1022 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_usart_unthrottle()
1024 stm32_port->throttled = false; in stm32_usart_unthrottle()
1030 if (stm32_port->rx_ch) in stm32_usart_unthrottle()
1033 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_unthrottle()
1040 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_stop_rx()
1045 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); in stm32_usart_stop_rx()
1046 if (stm32_port->cr3_irq) in stm32_usart_stop_rx()
1047 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_usart_stop_rx()
1050 /* Handle breaks - ignored by us */
1058 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_startup()
1059 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_startup()
1060 const char *name = to_platform_device(port->dev)->name; in stm32_usart_startup()
1064 ret = request_irq(port->irq, stm32_usart_interrupt, in stm32_usart_startup()
1069 if (stm32_port->swap) { in stm32_usart_startup()
1070 val = readl_relaxed(port->membase + ofs->cr2); in stm32_usart_startup()
1072 writel_relaxed(val, port->membase + ofs->cr2); in stm32_usart_startup()
1075 /* RX FIFO Flush */ in stm32_usart_startup()
1076 if (ofs->rqr != UNDEF_REG) in stm32_usart_startup()
1077 writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr); in stm32_usart_startup()
1079 if (stm32_port->rx_ch) { in stm32_usart_startup()
1082 free_irq(port->irq, port); in stm32_usart_startup()
1087 /* RX enabling */ in stm32_usart_startup()
1088 val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit); in stm32_usart_startup()
1089 stm32_usart_set_bits(port, ofs->cr1, val); in stm32_usart_startup()
1097 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_shutdown()
1098 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_shutdown()
1105 if (stm32_port->tx_ch) in stm32_usart_shutdown()
1106 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_shutdown()
1112 val |= stm32_port->cr1_irq | USART_CR1_RE; in stm32_usart_shutdown()
1113 val |= BIT(cfg->uart_enable_bit); in stm32_usart_shutdown()
1114 if (stm32_port->fifoen) in stm32_usart_shutdown()
1117 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, in stm32_usart_shutdown()
1123 dev_err(port->dev, "Transmission is not complete\n"); in stm32_usart_shutdown()
1125 /* Disable RX DMA. */ in stm32_usart_shutdown()
1126 if (stm32_port->rx_ch) { in stm32_usart_shutdown()
1128 dmaengine_synchronize(stm32_port->rx_ch); in stm32_usart_shutdown()
1131 /* flush RX & TX FIFO */ in stm32_usart_shutdown()
1132 if (ofs->rqr != UNDEF_REG) in stm32_usart_shutdown()
1134 port->membase + ofs->rqr); in stm32_usart_shutdown()
1136 stm32_usart_clr_bits(port, ofs->cr1, val); in stm32_usart_shutdown()
1138 free_irq(port->irq, port); in stm32_usart_shutdown()
1146 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_set_termios()
1147 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_set_termios()
1148 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_set_termios()
1151 tcflag_t cflag = termios->c_cflag; in stm32_usart_set_termios()
1156 if (!stm32_port->hw_flow_control) in stm32_usart_set_termios()
1159 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); in stm32_usart_set_termios()
1161 spin_lock_irqsave(&port->lock, flags); in stm32_usart_set_termios()
1163 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, in stm32_usart_set_termios()
1170 dev_err(port->dev, "Transmission is not complete\n"); in stm32_usart_set_termios()
1173 writel_relaxed(0, port->membase + ofs->cr1); in stm32_usart_set_termios()
1175 /* flush RX & TX FIFO */ in stm32_usart_set_termios()
1176 if (ofs->rqr != UNDEF_REG) in stm32_usart_set_termios()
1178 port->membase + ofs->rqr); in stm32_usart_set_termios()
1181 if (stm32_port->fifoen) in stm32_usart_set_termios()
1183 cr2 = stm32_port->swap ? USART_CR2_SWAP : 0; in stm32_usart_set_termios()
1185 /* Tx and RX FIFO configuration */ in stm32_usart_set_termios()
1186 cr3 = readl_relaxed(port->membase + ofs->cr3); in stm32_usart_set_termios()
1188 if (stm32_port->fifoen) { in stm32_usart_set_termios()
1189 if (stm32_port->txftcfg >= 0) in stm32_usart_set_termios()
1190 cr3 |= stm32_port->txftcfg << USART_CR3_TXFTCFG_SHIFT; in stm32_usart_set_termios()
1191 if (stm32_port->rxftcfg >= 0) in stm32_usart_set_termios()
1192 cr3 |= stm32_port->rxftcfg << USART_CR3_RXFTCFG_SHIFT; in stm32_usart_set_termios()
1199 stm32_port->rdr_mask = (BIT(bits) - 1); in stm32_usart_set_termios()
1215 } else if ((bits == 7) && cfg->has_7bits_data) { in stm32_usart_set_termios()
1218 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" in stm32_usart_set_termios()
1222 termios->c_cflag = cflag; in stm32_usart_set_termios()
1230 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || in stm32_usart_set_termios()
1231 (stm32_port->fifoen && in stm32_usart_set_termios()
1232 stm32_port->rxftcfg >= 0))) { in stm32_usart_set_termios()
1238 /* RX timeout irq to occur after last stop bit + bits */ in stm32_usart_set_termios()
1239 stm32_port->cr1_irq = USART_CR1_RTOIE; in stm32_usart_set_termios()
1240 writel_relaxed(bits, port->membase + ofs->rtor); in stm32_usart_set_termios()
1244 * wake up over usart, from low power until the DMA gets re-enabled by resume. in stm32_usart_set_termios()
1246 stm32_port->cr3_irq = USART_CR3_RXFTIE; in stm32_usart_set_termios()
1249 cr1 |= stm32_port->cr1_irq; in stm32_usart_set_termios()
1250 cr3 |= stm32_port->cr3_irq; in stm32_usart_set_termios()
1255 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); in stm32_usart_set_termios()
1257 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; in stm32_usart_set_termios()
1261 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); in stm32_usart_set_termios()
1272 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8); in stm32_usart_set_termios()
1276 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8); in stm32_usart_set_termios()
1281 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); in stm32_usart_set_termios()
1285 port->read_status_mask = USART_SR_ORE; in stm32_usart_set_termios()
1286 if (termios->c_iflag & INPCK) in stm32_usart_set_termios()
1287 port->read_status_mask |= USART_SR_PE | USART_SR_FE; in stm32_usart_set_termios()
1288 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in stm32_usart_set_termios()
1289 port->read_status_mask |= USART_SR_FE; in stm32_usart_set_termios()
1292 port->ignore_status_mask = 0; in stm32_usart_set_termios()
1293 if (termios->c_iflag & IGNPAR) in stm32_usart_set_termios()
1294 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; in stm32_usart_set_termios()
1295 if (termios->c_iflag & IGNBRK) { in stm32_usart_set_termios()
1296 port->ignore_status_mask |= USART_SR_FE; in stm32_usart_set_termios()
1301 if (termios->c_iflag & IGNPAR) in stm32_usart_set_termios()
1302 port->ignore_status_mask |= USART_SR_ORE; in stm32_usart_set_termios()
1306 if ((termios->c_cflag & CREAD) == 0) in stm32_usart_set_termios()
1307 port->ignore_status_mask |= USART_SR_DUMMY_RX; in stm32_usart_set_termios()
1309 if (stm32_port->rx_ch) { in stm32_usart_set_termios()
1320 if (stm32_port->tx_ch) in stm32_usart_set_termios()
1323 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_usart_set_termios()
1325 rs485conf->delay_rts_before_send, in stm32_usart_set_termios()
1326 rs485conf->delay_rts_after_send, in stm32_usart_set_termios()
1328 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_usart_set_termios()
1330 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; in stm32_usart_set_termios()
1333 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; in stm32_usart_set_termios()
1342 if (stm32_port->wakeup_src) { in stm32_usart_set_termios()
1347 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_usart_set_termios()
1348 writel_relaxed(cr2, port->membase + ofs->cr2); in stm32_usart_set_termios()
1349 writel_relaxed(cr1, port->membase + ofs->cr1); in stm32_usart_set_termios()
1351 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_set_termios()
1352 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_set_termios()
1355 if (UART_ENABLE_MS(port, termios->c_cflag)) in stm32_usart_set_termios()
1363 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; in stm32_usart_type()
1378 port->type = PORT_STM32; in stm32_usart_config_port()
1385 return -EINVAL; in stm32_usart_verify_port()
1393 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_pm()
1394 const struct stm32_usart_config *cfg = &stm32port->info->cfg; in stm32_usart_pm()
1399 pm_runtime_get_sync(port->dev); in stm32_usart_pm()
1402 spin_lock_irqsave(&port->lock, flags); in stm32_usart_pm()
1403 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_pm()
1404 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_pm()
1405 pm_runtime_put_sync(port->dev); in stm32_usart_pm()
1417 return clk_prepare_enable(stm32_port->clk); in stm32_usart_poll_init()
1423 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_poll_get_char()
1425 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_RXNE)) in stm32_usart_poll_get_char()
1428 return readl_relaxed(port->membase + ofs->rdr) & stm32_port->rdr_mask; in stm32_usart_poll_get_char()
1466 * STM32H7 RX & TX FIFO threshold configuration (CR3 RXFTCFG / TXFTCFG)
1478 /* DT option to get RX & TX FIFO threshold (default to 8 bytes) */ in stm32_usart_get_ftcfg()
1479 if (of_property_read_u32(pdev->dev.of_node, p, &bytes)) in stm32_usart_get_ftcfg()
1486 i = ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg) - 1; in stm32_usart_get_ftcfg()
1488 dev_dbg(&pdev->dev, "%s set to %d bytes\n", p, in stm32_usart_get_ftcfg()
1493 *ftcfg = i - 1; in stm32_usart_get_ftcfg()
1495 *ftcfg = -EINVAL; in stm32_usart_get_ftcfg()
1500 clk_disable_unprepare(stm32port->clk); in stm32_usart_deinit_port()
1513 struct uart_port *port = &stm32port->port; in stm32_usart_init_port()
1521 port->iotype = UPIO_MEM; in stm32_usart_init_port()
1522 port->flags = UPF_BOOT_AUTOCONF; in stm32_usart_init_port()
1523 port->ops = &stm32_uart_ops; in stm32_usart_init_port()
1524 port->dev = &pdev->dev; in stm32_usart_init_port()
1525 port->fifosize = stm32port->info->cfg.fifosize; in stm32_usart_init_port()
1526 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE); in stm32_usart_init_port()
1527 port->irq = irq; in stm32_usart_init_port()
1528 port->rs485_config = stm32_usart_config_rs485; in stm32_usart_init_port()
1529 port->rs485_supported = stm32_rs485_supported; in stm32_usart_init_port()
1535 stm32port->wakeup_src = stm32port->info->cfg.has_wakeup && in stm32_usart_init_port()
1536 of_property_read_bool(pdev->dev.of_node, "wakeup-source"); in stm32_usart_init_port()
1538 stm32port->swap = stm32port->info->cfg.has_swap && in stm32_usart_init_port()
1539 of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"); in stm32_usart_init_port()
1541 stm32port->fifoen = stm32port->info->cfg.has_fifo; in stm32_usart_init_port()
1542 if (stm32port->fifoen) { in stm32_usart_init_port()
1543 stm32_usart_get_ftcfg(pdev, "rx-threshold", in stm32_usart_init_port()
1544 &stm32port->rxftcfg); in stm32_usart_init_port()
1545 stm32_usart_get_ftcfg(pdev, "tx-threshold", in stm32_usart_init_port()
1546 &stm32port->txftcfg); in stm32_usart_init_port()
1549 port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in stm32_usart_init_port()
1550 if (IS_ERR(port->membase)) in stm32_usart_init_port()
1551 return PTR_ERR(port->membase); in stm32_usart_init_port()
1552 port->mapbase = res->start; in stm32_usart_init_port()
1554 spin_lock_init(&port->lock); in stm32_usart_init_port()
1556 stm32port->clk = devm_clk_get(&pdev->dev, NULL); in stm32_usart_init_port()
1557 if (IS_ERR(stm32port->clk)) in stm32_usart_init_port()
1558 return PTR_ERR(stm32port->clk); in stm32_usart_init_port()
1561 ret = clk_prepare_enable(stm32port->clk); in stm32_usart_init_port()
1565 stm32port->port.uartclk = clk_get_rate(stm32port->clk); in stm32_usart_init_port()
1566 if (!stm32port->port.uartclk) { in stm32_usart_init_port()
1567 ret = -EINVAL; in stm32_usart_init_port()
1571 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0); in stm32_usart_init_port()
1572 if (IS_ERR(stm32port->gpios)) { in stm32_usart_init_port()
1573 ret = PTR_ERR(stm32port->gpios); in stm32_usart_init_port()
1578 * Both CTS/RTS gpios and "st,hw-flow-ctrl" (deprecated) or "uart-has-rtscts" in stm32_usart_init_port()
1581 if (stm32port->hw_flow_control) { in stm32_usart_init_port()
1582 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) || in stm32_usart_init_port()
1583 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) { in stm32_usart_init_port()
1584 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n"); in stm32_usart_init_port()
1585 ret = -EINVAL; in stm32_usart_init_port()
1593 clk_disable_unprepare(stm32port->clk); in stm32_usart_init_port()
1600 struct device_node *np = pdev->dev.of_node; in stm32_usart_of_get_port()
1608 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); in stm32_usart_of_get_port()
1616 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ || in stm32_usart_of_get_port()
1617 of_property_read_bool (np, "uart-has-rtscts"); in stm32_usart_of_get_port()
1627 { .compatible = "st,stm32-uart", .data = &stm32f4_info},
1628 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
1629 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
1639 if (stm32port->rx_buf) in stm32_usart_of_dma_rx_remove()
1640 dma_free_coherent(&pdev->dev, RX_BUF_L, stm32port->rx_buf, in stm32_usart_of_dma_rx_remove()
1641 stm32port->rx_dma_buf); in stm32_usart_of_dma_rx_remove()
1647 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_of_dma_rx_probe()
1648 struct uart_port *port = &stm32port->port; in stm32_usart_of_dma_rx_probe()
1649 struct device *dev = &pdev->dev; in stm32_usart_of_dma_rx_probe()
1653 stm32port->rx_buf = dma_alloc_coherent(dev, RX_BUF_L, in stm32_usart_of_dma_rx_probe()
1654 &stm32port->rx_dma_buf, in stm32_usart_of_dma_rx_probe()
1656 if (!stm32port->rx_buf) in stm32_usart_of_dma_rx_probe()
1657 return -ENOMEM; in stm32_usart_of_dma_rx_probe()
1661 config.src_addr = port->mapbase + ofs->rdr; in stm32_usart_of_dma_rx_probe()
1664 ret = dmaengine_slave_config(stm32port->rx_ch, &config); in stm32_usart_of_dma_rx_probe()
1666 dev_err(dev, "rx dma channel config failed\n"); in stm32_usart_of_dma_rx_probe()
1677 if (stm32port->tx_buf) in stm32_usart_of_dma_tx_remove()
1678 dma_free_coherent(&pdev->dev, TX_BUF_L, stm32port->tx_buf, in stm32_usart_of_dma_tx_remove()
1679 stm32port->tx_dma_buf); in stm32_usart_of_dma_tx_remove()
1685 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_of_dma_tx_probe()
1686 struct uart_port *port = &stm32port->port; in stm32_usart_of_dma_tx_probe()
1687 struct device *dev = &pdev->dev; in stm32_usart_of_dma_tx_probe()
1691 stm32port->tx_buf = dma_alloc_coherent(dev, TX_BUF_L, in stm32_usart_of_dma_tx_probe()
1692 &stm32port->tx_dma_buf, in stm32_usart_of_dma_tx_probe()
1694 if (!stm32port->tx_buf) in stm32_usart_of_dma_tx_probe()
1695 return -ENOMEM; in stm32_usart_of_dma_tx_probe()
1699 config.dst_addr = port->mapbase + ofs->tdr; in stm32_usart_of_dma_tx_probe()
1702 ret = dmaengine_slave_config(stm32port->tx_ch, &config); in stm32_usart_of_dma_tx_probe()
1704 dev_err(dev, "tx dma channel config failed\n"); in stm32_usart_of_dma_tx_probe()
1719 return -ENODEV; in stm32_usart_serial_probe()
1721 stm32port->info = of_device_get_match_data(&pdev->dev); in stm32_usart_serial_probe()
1722 if (!stm32port->info) in stm32_usart_serial_probe()
1723 return -EINVAL; in stm32_usart_serial_probe()
1725 stm32port->rx_ch = dma_request_chan(&pdev->dev, "rx"); in stm32_usart_serial_probe()
1726 if (PTR_ERR(stm32port->rx_ch) == -EPROBE_DEFER) in stm32_usart_serial_probe()
1727 return -EPROBE_DEFER; in stm32_usart_serial_probe()
1729 /* Fall back in interrupt mode for any non-deferral error */ in stm32_usart_serial_probe()
1730 if (IS_ERR(stm32port->rx_ch)) in stm32_usart_serial_probe()
1731 stm32port->rx_ch = NULL; in stm32_usart_serial_probe()
1733 stm32port->tx_ch = dma_request_chan(&pdev->dev, "tx"); in stm32_usart_serial_probe()
1734 if (PTR_ERR(stm32port->tx_ch) == -EPROBE_DEFER) { in stm32_usart_serial_probe()
1735 ret = -EPROBE_DEFER; in stm32_usart_serial_probe()
1738 /* Fall back in interrupt mode for any non-deferral error */ in stm32_usart_serial_probe()
1739 if (IS_ERR(stm32port->tx_ch)) in stm32_usart_serial_probe()
1740 stm32port->tx_ch = NULL; in stm32_usart_serial_probe()
1746 if (stm32port->wakeup_src) { in stm32_usart_serial_probe()
1747 device_set_wakeup_capable(&pdev->dev, true); in stm32_usart_serial_probe()
1748 ret = dev_pm_set_wake_irq(&pdev->dev, stm32port->port.irq); in stm32_usart_serial_probe()
1753 if (stm32port->rx_ch && stm32_usart_of_dma_rx_probe(stm32port, pdev)) { in stm32_usart_serial_probe()
1755 dma_release_channel(stm32port->rx_ch); in stm32_usart_serial_probe()
1756 stm32port->rx_ch = NULL; in stm32_usart_serial_probe()
1759 if (stm32port->tx_ch && stm32_usart_of_dma_tx_probe(stm32port, pdev)) { in stm32_usart_serial_probe()
1761 dma_release_channel(stm32port->tx_ch); in stm32_usart_serial_probe()
1762 stm32port->tx_ch = NULL; in stm32_usart_serial_probe()
1765 if (!stm32port->rx_ch) in stm32_usart_serial_probe()
1766 dev_info(&pdev->dev, "interrupt mode for rx (no dma)\n"); in stm32_usart_serial_probe()
1767 if (!stm32port->tx_ch) in stm32_usart_serial_probe()
1768 dev_info(&pdev->dev, "interrupt mode for tx (no dma)\n"); in stm32_usart_serial_probe()
1770 platform_set_drvdata(pdev, &stm32port->port); in stm32_usart_serial_probe()
1772 pm_runtime_get_noresume(&pdev->dev); in stm32_usart_serial_probe()
1773 pm_runtime_set_active(&pdev->dev); in stm32_usart_serial_probe()
1774 pm_runtime_enable(&pdev->dev); in stm32_usart_serial_probe()
1776 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); in stm32_usart_serial_probe()
1780 pm_runtime_put_sync(&pdev->dev); in stm32_usart_serial_probe()
1785 pm_runtime_disable(&pdev->dev); in stm32_usart_serial_probe()
1786 pm_runtime_set_suspended(&pdev->dev); in stm32_usart_serial_probe()
1787 pm_runtime_put_noidle(&pdev->dev); in stm32_usart_serial_probe()
1789 if (stm32port->tx_ch) in stm32_usart_serial_probe()
1791 if (stm32port->rx_ch) in stm32_usart_serial_probe()
1794 if (stm32port->wakeup_src) in stm32_usart_serial_probe()
1795 dev_pm_clear_wake_irq(&pdev->dev); in stm32_usart_serial_probe()
1798 if (stm32port->wakeup_src) in stm32_usart_serial_probe()
1799 device_set_wakeup_capable(&pdev->dev, false); in stm32_usart_serial_probe()
1804 if (stm32port->tx_ch) in stm32_usart_serial_probe()
1805 dma_release_channel(stm32port->tx_ch); in stm32_usart_serial_probe()
1808 if (stm32port->rx_ch) in stm32_usart_serial_probe()
1809 dma_release_channel(stm32port->rx_ch); in stm32_usart_serial_probe()
1818 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_serial_remove()
1821 pm_runtime_get_sync(&pdev->dev); in stm32_usart_serial_remove()
1824 pm_runtime_disable(&pdev->dev); in stm32_usart_serial_remove()
1825 pm_runtime_set_suspended(&pdev->dev); in stm32_usart_serial_remove()
1826 pm_runtime_put_noidle(&pdev->dev); in stm32_usart_serial_remove()
1828 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_PEIE); in stm32_usart_serial_remove()
1830 if (stm32_port->tx_ch) { in stm32_usart_serial_remove()
1832 dma_release_channel(stm32_port->tx_ch); in stm32_usart_serial_remove()
1835 if (stm32_port->rx_ch) { in stm32_usart_serial_remove()
1837 dma_release_channel(stm32_port->rx_ch); in stm32_usart_serial_remove()
1840 cr3 = readl_relaxed(port->membase + ofs->cr3); in stm32_usart_serial_remove()
1845 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_usart_serial_remove()
1847 if (stm32_port->wakeup_src) { in stm32_usart_serial_remove()
1848 dev_pm_clear_wake_irq(&pdev->dev); in stm32_usart_serial_remove()
1849 device_init_wakeup(&pdev->dev, false); in stm32_usart_serial_remove()
1860 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_console_putchar()
1864 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, isr, in stm32_usart_console_putchar()
1868 dev_err(port->dev, "Error while sending data in UART TX : %d\n", ret); in stm32_usart_console_putchar()
1871 writel_relaxed(ch, port->membase + ofs->tdr); in stm32_usart_console_putchar()
1878 struct uart_port *port = &stm32_ports[co->index].port; in stm32_usart_console_write()
1880 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_console_write()
1881 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_console_write()
1887 locked = spin_trylock_irqsave(&port->lock, flags); in stm32_usart_console_write()
1889 spin_lock_irqsave(&port->lock, flags); in stm32_usart_console_write()
1892 old_cr1 = readl_relaxed(port->membase + ofs->cr1); in stm32_usart_console_write()
1894 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); in stm32_usart_console_write()
1895 writel_relaxed(new_cr1, port->membase + ofs->cr1); in stm32_usart_console_write()
1900 writel_relaxed(old_cr1, port->membase + ofs->cr1); in stm32_usart_console_write()
1903 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_console_write()
1914 if (co->index >= STM32_MAX_PORTS) in stm32_usart_console_setup()
1915 return -ENODEV; in stm32_usart_console_setup()
1917 stm32port = &stm32_ports[co->index]; in stm32_usart_console_setup()
1922 * this to be called during the uart port registration when the in stm32_usart_console_setup()
1925 if (stm32port->port.mapbase == 0 || !stm32port->port.membase) in stm32_usart_console_setup()
1926 return -ENXIO; in stm32_usart_console_setup()
1931 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); in stm32_usart_console_setup()
1940 .index = -1,
1953 struct stm32_usart_info *info = port->private_data; in early_stm32_usart_console_putchar()
1955 while (!(readl_relaxed(port->membase + info->ofs.isr) & USART_SR_TXE)) in early_stm32_usart_console_putchar()
1958 writel_relaxed(ch, port->membase + info->ofs.tdr); in early_stm32_usart_console_putchar()
1963 struct earlycon_device *device = console->data; in early_stm32_serial_write()
1964 struct uart_port *port = &device->port; in early_stm32_serial_write()
1971 if (!(device->port.membase || device->port.iobase)) in early_stm32_h7_serial_setup()
1972 return -ENODEV; in early_stm32_h7_serial_setup()
1973 device->port.private_data = &stm32h7_info; in early_stm32_h7_serial_setup()
1974 device->con->write = early_stm32_serial_write; in early_stm32_h7_serial_setup()
1980 if (!(device->port.membase || device->port.iobase)) in early_stm32_f7_serial_setup()
1981 return -ENODEV; in early_stm32_f7_serial_setup()
1982 device->port.private_data = &stm32f7_info; in early_stm32_f7_serial_setup()
1983 device->con->write = early_stm32_serial_write; in early_stm32_f7_serial_setup()
1989 if (!(device->port.membase || device->port.iobase)) in early_stm32_f4_serial_setup()
1990 return -ENODEV; in early_stm32_f4_serial_setup()
1991 device->port.private_data = &stm32f4_info; in early_stm32_f4_serial_setup()
1992 device->con->write = early_stm32_serial_write; in early_stm32_f4_serial_setup()
1996 OF_EARLYCON_DECLARE(stm32, "st,stm32h7-uart", early_stm32_h7_serial_setup);
1997 OF_EARLYCON_DECLARE(stm32, "st,stm32f7-uart", early_stm32_f7_serial_setup);
1998 OF_EARLYCON_DECLARE(stm32, "st,stm32-uart", early_stm32_f4_serial_setup);
2014 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_serial_en_wakeup()
2015 struct tty_port *tport = &port->state->port; in stm32_usart_serial_en_wakeup()
2020 if (!stm32_port->wakeup_src || !tty_port_initialized(tport)) in stm32_usart_serial_en_wakeup()
2024 * Enable low-power wake-up and wake-up irq if argument is set to in stm32_usart_serial_en_wakeup()
2025 * "enable", disable low-power wake-up and wake-up irq otherwise in stm32_usart_serial_en_wakeup()
2028 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM); in stm32_usart_serial_en_wakeup()
2029 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE); in stm32_usart_serial_en_wakeup()
2030 mctrl_gpio_enable_irq_wake(stm32_port->gpios); in stm32_usart_serial_en_wakeup()
2034 * entering low-power mode and re-enabled when exiting from in stm32_usart_serial_en_wakeup()
2035 * low-power mode. in stm32_usart_serial_en_wakeup()
2037 if (stm32_port->rx_ch) { in stm32_usart_serial_en_wakeup()
2038 spin_lock_irqsave(&port->lock, flags); in stm32_usart_serial_en_wakeup()
2039 /* Poll data from DMA RX buffer if any */ in stm32_usart_serial_en_wakeup()
2048 /* Poll data from RX FIFO if any */ in stm32_usart_serial_en_wakeup()
2051 if (stm32_port->rx_ch) { in stm32_usart_serial_en_wakeup()
2056 mctrl_gpio_disable_irq_wake(stm32_port->gpios); in stm32_usart_serial_en_wakeup()
2057 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM); in stm32_usart_serial_en_wakeup()
2058 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); in stm32_usart_serial_en_wakeup()
2115 clk_disable_unprepare(stm32port->clk); in stm32_usart_runtime_suspend()
2126 return clk_prepare_enable(stm32port->clk); in stm32_usart_runtime_resume()