497 #define sci_getreg(up, offset)		(&to_sci_port(up)->params->regs[offset])  macro
507 	const struct plat_sci_reg *reg = sci_getreg(p, offset);  in sci_serial_in()
521 	const struct plat_sci_reg *reg = sci_getreg(p, offset);  in sci_serial_out()
761 	} else if (sci_getreg(port, SCSPTR)->size) {  in sci_init_pins()
782 	reg = sci_getreg(port, SCTFDR);  in sci_txfill()
786 	reg = sci_getreg(port, SCFDR);  in sci_txfill()
804 	reg = sci_getreg(port, SCRFDR);  in sci_rxfill()
808 	reg = sci_getreg(port, SCFDR);  in sci_rxfill()
999 	reg = sci_getreg(port, s->params->overrun_reg);  in sci_handle_fifo_overrun()
1053 	if (sci_getreg(port, HSRTRGR)->size) {  in scif_set_rtrg()
1104 	if (sci_getreg(port, HSRTRGR)->size)  in scif_rtrg_enabled()
1571 		(sci_getreg(port, SCxTDR)->offset << port->regshift);  in sci_request_dma_chan()
1574 		(sci_getreg(port, SCxRDR)->offset << port->regshift);  in sci_request_dma_chan()
1864 	else if (sci_getreg(port, s->params->overrun_reg)->size)  in sci_mpxed_interrupt()
2063 	} else if (sci_getreg(port, SCSPTR)->size) {  in sci_set_rts()
2080 	} else if (sci_getreg(port, SCSPTR)->size) {  in sci_get_cts()
2110 		reg = sci_getreg(port, SCFCR);  in sci_set_mctrl()
2182 	if (!sci_getreg(port, SCSPTR)->size) {  in sci_break_ctl()
2396 	reg = sci_getreg(port, SCFCR);  in sci_reset()
2403 	if (sci_getreg(port, SCLSR)->size) {  in sci_reset()
2490 	if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {  in sci_set_termios()
2506 	if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {  in sci_set_termios()
2543 	if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {  in sci_set_termios()
2557 	if (sci_getreg(port, SEMR)->size)  in sci_set_termios()
2576 		if (sci_getreg(port, HSSRR)->size) {  in sci_set_termios()
2615 	reg = sci_getreg(port, SCFCR);  in sci_set_termios()