Lines Matching +full:ctrl +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 * Copyright (C) 2002 - 2011 Paul Mundt
9 * based off of the old drivers/char/sh-sci.c by:
26 #include <linux/dma-mapping.h>
58 #include "sh-sci.h"
60 /* Offsets into the sci_port->irqs array */
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
88 #define SCI_SR(x) BIT((x) - 1)
89 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
95 #define min_sr(_port) ffs((_port)->sampling_rate_mask)
96 #define max_sr(_port) fls((_port)->sampling_rate_mask)
100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
101 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
125 struct mctrl_gpios *gpios; member
268 * Common SH-2(A) SCIF definitions for ports with FIFO data
321 * Common SH-3 SCIF definitions.
343 * Common SH-4(A) SCIF(B) definitions.
423 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
447 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
474 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
497 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
509 if (reg->size == 8) in sci_serial_in()
510 return ioread8(p->membase + (reg->offset << p->regshift)); in sci_serial_in()
511 else if (reg->size == 16) in sci_serial_in()
512 return ioread16(p->membase + (reg->offset << p->regshift)); in sci_serial_in()
523 if (reg->size == 8) in sci_serial_out()
524 iowrite8(value, p->membase + (reg->offset << p->regshift)); in sci_serial_out()
525 else if (reg->size == 16) in sci_serial_out()
526 iowrite16(value, p->membase + (reg->offset << p->regshift)); in sci_serial_out()
535 if (!sci_port->port.dev) in sci_port_enable()
538 pm_runtime_get_sync(sci_port->port.dev); in sci_port_enable()
541 clk_prepare_enable(sci_port->clks[i]); in sci_port_enable()
542 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); in sci_port_enable()
544 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; in sci_port_enable()
551 if (!sci_port->port.dev) in sci_port_disable()
554 for (i = SCI_NUM_CLKS; i-- > 0; ) in sci_port_disable()
555 clk_disable_unprepare(sci_port->clks[i]); in sci_port_disable()
557 pm_runtime_put_sync(sci_port->port.dev); in sci_port_disable()
564 * special-casing the port type, we check the port initialization in port_rx_irq_mask()
569 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); in port_rx_irq_mask()
575 unsigned short ctrl; in sci_start_tx() local
578 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { in sci_start_tx()
580 if (s->chan_tx) in sci_start_tx()
588 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && in sci_start_tx()
589 dma_submit_error(s->cookie_tx)) { in sci_start_tx()
590 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) in sci_start_tx()
592 disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]); in sci_start_tx()
594 s->cookie_tx = 0; in sci_start_tx()
595 schedule_work(&s->work_tx); in sci_start_tx()
599 if (!s->chan_tx || s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE || in sci_start_tx()
600 port->type == PORT_SCIFA || port->type == PORT_SCIFB) { in sci_start_tx()
602 ctrl = serial_port_in(port, SCSCR); in sci_start_tx()
609 if (port->type == PORT_SCI) in sci_start_tx()
610 ctrl |= SCSCR_TE; in sci_start_tx()
612 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); in sci_start_tx()
618 unsigned short ctrl; in sci_stop_tx() local
621 ctrl = serial_port_in(port, SCSCR); in sci_stop_tx()
623 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) in sci_stop_tx()
624 ctrl &= ~SCSCR_TDRQE; in sci_stop_tx()
626 ctrl &= ~SCSCR_TIE; in sci_stop_tx()
628 serial_port_out(port, SCSCR, ctrl); in sci_stop_tx()
631 if (to_sci_port(port)->chan_tx && in sci_stop_tx()
632 !dma_submit_error(to_sci_port(port)->cookie_tx)) { in sci_stop_tx()
633 dmaengine_terminate_async(to_sci_port(port)->chan_tx); in sci_stop_tx()
634 to_sci_port(port)->cookie_tx = -EINVAL; in sci_stop_tx()
641 unsigned short ctrl; in sci_start_rx() local
643 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); in sci_start_rx()
645 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) in sci_start_rx()
646 ctrl &= ~SCSCR_RDRQE; in sci_start_rx()
648 serial_port_out(port, SCSCR, ctrl); in sci_start_rx()
653 unsigned short ctrl; in sci_stop_rx() local
655 ctrl = serial_port_in(port, SCSCR); in sci_stop_rx()
657 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) in sci_stop_rx()
658 ctrl &= ~SCSCR_RDRQE; in sci_stop_rx()
660 ctrl &= ~port_rx_irq_mask(port); in sci_stop_rx()
662 serial_port_out(port, SCSCR, ctrl); in sci_stop_rx()
667 if (port->type == PORT_SCI) { in sci_clear_SCxSR()
670 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { in sci_clear_SCxSR()
731 * Use port-specific handler if provided. in sci_init_pins()
733 if (s->cfg->ops && s->cfg->ops->init_pins) { in sci_init_pins()
734 s->cfg->ops->init_pins(port, cflag); in sci_init_pins()
738 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { in sci_init_pins()
740 u16 ctrl = serial_port_in(port, SCPCR); in sci_init_pins() local
743 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); in sci_init_pins()
744 if (to_sci_port(port)->has_rtscts) { in sci_init_pins()
746 if (!(port->mctrl & TIOCM_RTS)) { in sci_init_pins()
747 ctrl |= SCPCR_RTSC; in sci_init_pins()
749 } else if (!s->autorts) { in sci_init_pins()
750 ctrl |= SCPCR_RTSC; in sci_init_pins()
754 ctrl &= ~SCPCR_RTSC; in sci_init_pins()
757 ctrl &= ~SCPCR_CTSC; in sci_init_pins()
760 serial_port_out(port, SCPCR, ctrl); in sci_init_pins()
761 } else if (sci_getreg(port, SCSPTR)->size) { in sci_init_pins()
766 if (!(port->mctrl & TIOCM_RTS)) in sci_init_pins()
768 else if (!s->autorts) in sci_init_pins()
779 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; in sci_txfill()
783 if (reg->size) in sci_txfill()
787 if (reg->size) in sci_txfill()
795 return port->fifosize - sci_txfill(port); in sci_txroom()
801 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; in sci_rxfill()
805 if (reg->size) in sci_rxfill()
809 if (reg->size) in sci_rxfill()
821 struct circ_buf *xmit = &port->state->xmit; in sci_transmit_chars()
824 unsigned short ctrl; in sci_transmit_chars() local
829 ctrl = serial_port_in(port, SCSCR); in sci_transmit_chars()
831 ctrl &= ~SCSCR_TIE; in sci_transmit_chars()
833 ctrl |= SCSCR_TIE; in sci_transmit_chars()
834 serial_port_out(port, SCSCR, ctrl); in sci_transmit_chars()
843 if (port->x_char) { in sci_transmit_chars()
844 c = port->x_char; in sci_transmit_chars()
845 port->x_char = 0; in sci_transmit_chars()
847 c = xmit->buf[xmit->tail]; in sci_transmit_chars()
848 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in sci_transmit_chars()
849 } else if (port->type == PORT_SCI && uart_circ_empty(xmit)) { in sci_transmit_chars()
850 ctrl = serial_port_in(port, SCSCR); in sci_transmit_chars()
851 ctrl &= ~SCSCR_TE; in sci_transmit_chars()
852 serial_port_out(port, SCSCR, ctrl); in sci_transmit_chars()
860 port->icount.tx++; in sci_transmit_chars()
861 } while (--count > 0); in sci_transmit_chars()
868 if (port->type == PORT_SCI) { in sci_transmit_chars()
869 ctrl = serial_port_in(port, SCSCR); in sci_transmit_chars()
870 ctrl &= ~SCSCR_TIE; in sci_transmit_chars()
871 ctrl |= SCSCR_TEIE; in sci_transmit_chars()
872 serial_port_out(port, SCSCR, ctrl); in sci_transmit_chars()
881 struct tty_port *tport = &port->state->port; in sci_receive_chars()
898 if (port->type == PORT_SCI) { in sci_receive_chars()
908 if (port->type == PORT_SCIF || in sci_receive_chars()
909 port->type == PORT_HSCIF) { in sci_receive_chars()
917 count--; i--; in sci_receive_chars()
924 port->icount.frame++; in sci_receive_chars()
927 port->icount.parity++; in sci_receive_chars()
939 port->icount.rx += count; in sci_receive_chars()
957 struct tty_port *tport = &port->state->port; in sci_handle_errors()
961 if (status & s->params->overrun_mask) { in sci_handle_errors()
962 port->icount.overrun++; in sci_handle_errors()
971 port->icount.frame++; in sci_handle_errors()
979 port->icount.parity++; in sci_handle_errors()
993 struct tty_port *tport = &port->state->port; in sci_handle_fifo_overrun()
999 reg = sci_getreg(port, s->params->overrun_reg); in sci_handle_fifo_overrun()
1000 if (!reg->size) in sci_handle_fifo_overrun()
1003 status = serial_port_in(port, s->params->overrun_reg); in sci_handle_fifo_overrun()
1004 if (status & s->params->overrun_mask) { in sci_handle_fifo_overrun()
1005 status &= ~s->params->overrun_mask; in sci_handle_fifo_overrun()
1006 serial_port_out(port, s->params->overrun_reg, status); in sci_handle_fifo_overrun()
1008 port->icount.overrun++; in sci_handle_fifo_overrun()
1022 struct tty_port *tport = &port->state->port; in sci_handle_breaks()
1028 port->icount.brk++; in sci_handle_breaks()
1047 if (rx_trig >= port->fifosize) in scif_set_rtrg()
1048 rx_trig = port->fifosize - 1; in scif_set_rtrg()
1053 if (sci_getreg(port, HSRTRGR)->size) { in scif_set_rtrg()
1058 switch (port->type) { in scif_set_rtrg()
1104 if (sci_getreg(port, HSRTRGR)->size) in scif_rtrg_enabled()
1114 struct uart_port *port = &s->port; in rx_fifo_timer_fn()
1116 dev_dbg(port->dev, "Rx timed out\n"); in rx_fifo_timer_fn()
1126 return sprintf(buf, "%d\n", sci->rx_trigger); in rx_fifo_trigger_show()
1142 sci->rx_trigger = scif_set_rtrg(port, r); in rx_fifo_trigger_store()
1143 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) in rx_fifo_trigger_store()
1159 if (port->type == PORT_HSCIF) in rx_fifo_timeout_show()
1160 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; in rx_fifo_timeout_show()
1162 v = sci->rx_fifo_timeout; in rx_fifo_timeout_show()
1181 if (port->type == PORT_HSCIF) { in rx_fifo_timeout_store()
1183 return -EINVAL; in rx_fifo_timeout_store()
1184 sci->hscif_tot = r << HSSCR_TOT_SHIFT; in rx_fifo_timeout_store()
1186 sci->rx_fifo_timeout = r; in rx_fifo_timeout_store()
1189 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); in rx_fifo_timeout_store()
1202 struct uart_port *port = &s->port; in sci_dma_tx_complete()
1203 struct circ_buf *xmit = &port->state->xmit; in sci_dma_tx_complete()
1206 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); in sci_dma_tx_complete()
1208 spin_lock_irqsave(&port->lock, flags); in sci_dma_tx_complete()
1210 uart_xmit_advance(port, s->tx_dma_len); in sci_dma_tx_complete()
1216 s->cookie_tx = 0; in sci_dma_tx_complete()
1217 schedule_work(&s->work_tx); in sci_dma_tx_complete()
1219 s->cookie_tx = -EINVAL; in sci_dma_tx_complete()
1220 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || in sci_dma_tx_complete()
1221 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { in sci_dma_tx_complete()
1222 u16 ctrl = serial_port_in(port, SCSCR); in sci_dma_tx_complete() local
1223 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); in sci_dma_tx_complete()
1224 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { in sci_dma_tx_complete()
1226 dmaengine_pause(s->chan_tx_saved); in sci_dma_tx_complete()
1227 enable_irq(s->irqs[SCIx_TXI_IRQ]); in sci_dma_tx_complete()
1232 spin_unlock_irqrestore(&port->lock, flags); in sci_dma_tx_complete()
1238 struct uart_port *port = &s->port; in sci_dma_rx_push()
1239 struct tty_port *tport = &port->state->port; in sci_dma_rx_push()
1244 port->icount.buf_overrun++; in sci_dma_rx_push()
1246 port->icount.rx += copied; in sci_dma_rx_push()
1255 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) in sci_dma_rx_find_active()
1256 if (s->active_rx == s->cookie_rx[i]) in sci_dma_rx_find_active()
1259 return -1; in sci_dma_rx_find_active()
1266 s->chan_rx = NULL; in sci_dma_rx_chan_invalidate()
1267 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) in sci_dma_rx_chan_invalidate()
1268 s->cookie_rx[i] = -EINVAL; in sci_dma_rx_chan_invalidate()
1269 s->active_rx = 0; in sci_dma_rx_chan_invalidate()
1274 struct dma_chan *chan = s->chan_rx_saved; in sci_dma_rx_release()
1276 s->chan_rx_saved = NULL; in sci_dma_rx_release()
1279 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], in sci_dma_rx_release()
1280 sg_dma_address(&s->sg_rx[0])); in sci_dma_rx_release()
1295 struct uart_port *port = &s->port; in sci_dma_rx_reenable_irq()
1300 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || in sci_dma_rx_reenable_irq()
1301 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { in sci_dma_rx_reenable_irq()
1302 enable_irq(s->irqs[SCIx_RXI_IRQ]); in sci_dma_rx_reenable_irq()
1303 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) in sci_dma_rx_reenable_irq()
1304 scif_set_rtrg(port, s->rx_trigger); in sci_dma_rx_reenable_irq()
1314 struct dma_chan *chan = s->chan_rx; in sci_dma_rx_complete()
1315 struct uart_port *port = &s->port; in sci_dma_rx_complete()
1320 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, in sci_dma_rx_complete()
1321 s->active_rx); in sci_dma_rx_complete()
1323 spin_lock_irqsave(&port->lock, flags); in sci_dma_rx_complete()
1327 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); in sci_dma_rx_complete()
1329 start_hrtimer_us(&s->rx_timer, s->rx_timeout); in sci_dma_rx_complete()
1332 tty_flip_buffer_push(&port->state->port); in sci_dma_rx_complete()
1334 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, in sci_dma_rx_complete()
1340 desc->callback = sci_dma_rx_complete; in sci_dma_rx_complete()
1341 desc->callback_param = s; in sci_dma_rx_complete()
1342 s->cookie_rx[active] = dmaengine_submit(desc); in sci_dma_rx_complete()
1343 if (dma_submit_error(s->cookie_rx[active])) in sci_dma_rx_complete()
1346 s->active_rx = s->cookie_rx[!active]; in sci_dma_rx_complete()
1350 spin_unlock_irqrestore(&port->lock, flags); in sci_dma_rx_complete()
1351 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", in sci_dma_rx_complete()
1352 __func__, s->cookie_rx[active], active, s->active_rx); in sci_dma_rx_complete()
1356 spin_unlock_irqrestore(&port->lock, flags); in sci_dma_rx_complete()
1357 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); in sci_dma_rx_complete()
1359 spin_lock_irqsave(&port->lock, flags); in sci_dma_rx_complete()
1363 spin_unlock_irqrestore(&port->lock, flags); in sci_dma_rx_complete()
1368 struct dma_chan *chan = s->chan_tx_saved; in sci_dma_tx_release()
1370 cancel_work_sync(&s->work_tx); in sci_dma_tx_release()
1371 s->chan_tx_saved = s->chan_tx = NULL; in sci_dma_tx_release()
1372 s->cookie_tx = -EINVAL; in sci_dma_tx_release()
1374 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, in sci_dma_tx_release()
1381 struct dma_chan *chan = s->chan_rx; in sci_dma_rx_submit()
1382 struct uart_port *port = &s->port; in sci_dma_rx_submit()
1387 struct scatterlist *sg = &s->sg_rx[i]; in sci_dma_rx_submit()
1396 desc->callback = sci_dma_rx_complete; in sci_dma_rx_submit()
1397 desc->callback_param = s; in sci_dma_rx_submit()
1398 s->cookie_rx[i] = dmaengine_submit(desc); in sci_dma_rx_submit()
1399 if (dma_submit_error(s->cookie_rx[i])) in sci_dma_rx_submit()
1404 s->active_rx = s->cookie_rx[0]; in sci_dma_rx_submit()
1412 spin_lock_irqsave(&port->lock, flags); in sci_dma_rx_submit()
1418 spin_unlock_irqrestore(&port->lock, flags); in sci_dma_rx_submit()
1419 return -EAGAIN; in sci_dma_rx_submit()
1426 struct dma_chan *chan = s->chan_tx; in sci_dma_tx_work_fn()
1427 struct uart_port *port = &s->port; in sci_dma_tx_work_fn()
1428 struct circ_buf *xmit = &port->state->xmit; in sci_dma_tx_work_fn()
1440 spin_lock_irq(&port->lock); in sci_dma_tx_work_fn()
1441 head = xmit->head; in sci_dma_tx_work_fn()
1442 tail = xmit->tail; in sci_dma_tx_work_fn()
1443 buf = s->tx_dma_addr + tail; in sci_dma_tx_work_fn()
1444 s->tx_dma_len = CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE); in sci_dma_tx_work_fn()
1445 if (!s->tx_dma_len) { in sci_dma_tx_work_fn()
1447 spin_unlock_irq(&port->lock); in sci_dma_tx_work_fn()
1451 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, in sci_dma_tx_work_fn()
1455 spin_unlock_irq(&port->lock); in sci_dma_tx_work_fn()
1456 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); in sci_dma_tx_work_fn()
1460 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, in sci_dma_tx_work_fn()
1463 desc->callback = sci_dma_tx_complete; in sci_dma_tx_work_fn()
1464 desc->callback_param = s; in sci_dma_tx_work_fn()
1465 s->cookie_tx = dmaengine_submit(desc); in sci_dma_tx_work_fn()
1466 if (dma_submit_error(s->cookie_tx)) { in sci_dma_tx_work_fn()
1467 spin_unlock_irq(&port->lock); in sci_dma_tx_work_fn()
1468 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); in sci_dma_tx_work_fn()
1472 spin_unlock_irq(&port->lock); in sci_dma_tx_work_fn()
1473 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", in sci_dma_tx_work_fn()
1474 __func__, xmit->buf, tail, head, s->cookie_tx); in sci_dma_tx_work_fn()
1480 spin_lock_irqsave(&port->lock, flags); in sci_dma_tx_work_fn()
1481 s->chan_tx = NULL; in sci_dma_tx_work_fn()
1483 spin_unlock_irqrestore(&port->lock, flags); in sci_dma_tx_work_fn()
1490 struct dma_chan *chan = s->chan_rx; in sci_dma_rx_timer_fn()
1491 struct uart_port *port = &s->port; in sci_dma_rx_timer_fn()
1498 dev_dbg(port->dev, "DMA Rx timed out\n"); in sci_dma_rx_timer_fn()
1500 spin_lock_irqsave(&port->lock, flags); in sci_dma_rx_timer_fn()
1504 spin_unlock_irqrestore(&port->lock, flags); in sci_dma_rx_timer_fn()
1508 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); in sci_dma_rx_timer_fn()
1510 spin_unlock_irqrestore(&port->lock, flags); in sci_dma_rx_timer_fn()
1511 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", in sci_dma_rx_timer_fn()
1512 s->active_rx, active); in sci_dma_rx_timer_fn()
1526 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); in sci_dma_rx_timer_fn()
1528 spin_unlock_irqrestore(&port->lock, flags); in sci_dma_rx_timer_fn()
1529 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); in sci_dma_rx_timer_fn()
1534 dmaengine_terminate_async(s->chan_rx); in sci_dma_rx_timer_fn()
1535 read = sg_dma_len(&s->sg_rx[active]) - state.residue; in sci_dma_rx_timer_fn()
1538 count = sci_dma_rx_push(s, s->rx_buf[active], read); in sci_dma_rx_timer_fn()
1540 tty_flip_buffer_push(&port->state->port); in sci_dma_rx_timer_fn()
1543 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || in sci_dma_rx_timer_fn()
1544 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) in sci_dma_rx_timer_fn()
1549 spin_unlock_irqrestore(&port->lock, flags); in sci_dma_rx_timer_fn()
1561 chan = dma_request_slave_channel(port->dev, in sci_request_dma_chan()
1564 dev_dbg(port->dev, "dma_request_slave_channel failed\n"); in sci_request_dma_chan()
1570 cfg.dst_addr = port->mapbase + in sci_request_dma_chan()
1571 (sci_getreg(port, SCxTDR)->offset << port->regshift); in sci_request_dma_chan()
1573 cfg.src_addr = port->mapbase + in sci_request_dma_chan()
1574 (sci_getreg(port, SCxRDR)->offset << port->regshift); in sci_request_dma_chan()
1579 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); in sci_request_dma_chan()
1592 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); in sci_request_dma()
1601 if (!port->dev->of_node) in sci_request_dma()
1604 s->cookie_tx = -EINVAL; in sci_request_dma()
1610 if (!of_property_present(port->dev->of_node, "dmas")) in sci_request_dma()
1614 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); in sci_request_dma()
1617 s->tx_dma_addr = dma_map_single(chan->device->dev, in sci_request_dma()
1618 port->state->xmit.buf, in sci_request_dma()
1621 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { in sci_request_dma()
1622 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); in sci_request_dma()
1625 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", in sci_request_dma()
1627 port->state->xmit.buf, &s->tx_dma_addr); in sci_request_dma()
1629 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn); in sci_request_dma()
1630 s->chan_tx_saved = s->chan_tx = chan; in sci_request_dma()
1635 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); in sci_request_dma()
1641 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); in sci_request_dma()
1642 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, in sci_request_dma()
1645 dev_warn(port->dev, in sci_request_dma()
1652 struct scatterlist *sg = &s->sg_rx[i]; in sci_request_dma()
1655 s->rx_buf[i] = buf; in sci_request_dma()
1657 sg_dma_len(sg) = s->buf_len_rx; in sci_request_dma()
1659 buf += s->buf_len_rx; in sci_request_dma()
1660 dma += s->buf_len_rx; in sci_request_dma()
1663 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in sci_request_dma()
1664 s->rx_timer.function = sci_dma_rx_timer_fn; in sci_request_dma()
1666 s->chan_rx_saved = s->chan_rx = chan; in sci_request_dma()
1668 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || in sci_request_dma()
1669 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) in sci_request_dma()
1678 if (s->chan_tx_saved) in sci_free_dma()
1680 if (s->chan_rx_saved) in sci_free_dma()
1693 s->tx_dma_len = 0; in sci_flush_buffer()
1694 if (s->chan_tx) { in sci_flush_buffer()
1695 dmaengine_terminate_async(s->chan_tx); in sci_flush_buffer()
1696 s->cookie_tx = -EINVAL; in sci_flush_buffer()
1717 if (s->chan_rx) { in sci_rx_interrupt()
1722 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || in sci_rx_interrupt()
1723 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { in sci_rx_interrupt()
1724 disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]); in sci_rx_interrupt()
1725 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { in sci_rx_interrupt()
1741 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", in sci_rx_interrupt()
1742 jiffies, s->rx_timeout); in sci_rx_interrupt()
1743 start_hrtimer_us(&s->rx_timer, s->rx_timeout); in sci_rx_interrupt()
1751 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { in sci_rx_interrupt()
1753 scif_set_rtrg(port, s->rx_trigger); in sci_rx_interrupt()
1755 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( in sci_rx_interrupt()
1756 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); in sci_rx_interrupt()
1773 spin_lock_irqsave(&port->lock, flags); in sci_tx_interrupt()
1775 spin_unlock_irqrestore(&port->lock, flags); in sci_tx_interrupt()
1784 unsigned short ctrl; in sci_tx_end_interrupt() local
1786 if (port->type != PORT_SCI) in sci_tx_end_interrupt()
1789 spin_lock_irqsave(&port->lock, flags); in sci_tx_end_interrupt()
1790 ctrl = serial_port_in(port, SCSCR); in sci_tx_end_interrupt()
1791 ctrl &= ~(SCSCR_TE | SCSCR_TEIE); in sci_tx_end_interrupt()
1792 serial_port_out(port, SCSCR, ctrl); in sci_tx_end_interrupt()
1793 spin_unlock_irqrestore(&port->lock, flags); in sci_tx_end_interrupt()
1818 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) { in sci_er_interrupt()
1832 if (port->type == PORT_SCI) { in sci_er_interrupt()
1840 if (!s->chan_rx) in sci_er_interrupt()
1847 if (!s->chan_tx) in sci_er_interrupt()
1862 if (s->params->overrun_reg == SCxSR) in sci_mpxed_interrupt()
1864 else if (sci_getreg(port, s->params->overrun_reg)->size) in sci_mpxed_interrupt()
1865 orer_status = serial_port_in(port, s->params->overrun_reg); in sci_mpxed_interrupt()
1871 !s->chan_tx) in sci_mpxed_interrupt()
1878 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && in sci_mpxed_interrupt()
1887 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] && in sci_mpxed_interrupt()
1892 if (orer_status & s->params->overrun_mask) { in sci_mpxed_interrupt()
1948 struct uart_port *up = &port->port; in sci_request_irq()
1957 if (port->irqs[w] == port->irqs[i]) in sci_request_irq()
1964 irq = up->irq; in sci_request_irq()
1966 irq = port->irqs[i]; in sci_request_irq()
1977 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", in sci_request_irq()
1978 dev_name(up->dev), desc->desc); in sci_request_irq()
1979 if (!port->irqstr[j]) { in sci_request_irq()
1980 ret = -ENOMEM; in sci_request_irq()
1984 ret = request_irq(irq, desc->handler, up->irqflags, in sci_request_irq()
1985 port->irqstr[j], port); in sci_request_irq()
1987 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); in sci_request_irq()
1995 while (--i >= 0) in sci_request_irq()
1996 free_irq(port->irqs[i], port); in sci_request_irq()
1999 while (--j >= 0) in sci_request_irq()
2000 kfree(port->irqstr[j]); in sci_request_irq()
2014 int irq = port->irqs[i]; in sci_free_irq()
2025 if (port->irqs[j] == irq) in sci_free_irq()
2030 free_irq(port->irqs[i], port); in sci_free_irq()
2031 kfree(port->irqstr[i]); in sci_free_irq()
2050 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { in sci_set_rts()
2063 } else if (sci_getreg(port, SCSPTR)->size) { in sci_set_rts()
2064 u16 ctrl = serial_port_in(port, SCSPTR); in sci_set_rts() local
2068 ctrl &= ~SCSPTR_RTSDT; in sci_set_rts()
2070 ctrl |= SCSPTR_RTSDT; in sci_set_rts()
2071 serial_port_out(port, SCSPTR, ctrl); in sci_set_rts()
2077 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { in sci_get_cts()
2080 } else if (sci_getreg(port, SCSPTR)->size) { in sci_get_cts()
2092 * handled via the ->init_pins() op, which is a bit of a one-way street,
2093 * lacking any ability to defer pin control -- this will later be
2111 if (reg->size) in sci_set_mctrl()
2117 mctrl_gpio_set(s->gpios, mctrl); in sci_set_mctrl()
2119 if (!s->has_rtscts) in sci_set_mctrl()
2129 } else if (s->autorts) { in sci_set_mctrl()
2130 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { in sci_set_mctrl()
2148 struct mctrl_gpios *gpios = s->gpios; in sci_get_mctrl() local
2151 mctrl_gpio_get(gpios, &mctrl); in sci_get_mctrl()
2157 if (s->autorts) { in sci_get_mctrl()
2160 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) { in sci_get_mctrl()
2163 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)) in sci_get_mctrl()
2165 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)) in sci_get_mctrl()
2173 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); in sci_enable_ms()
2182 if (!sci_getreg(port, SCSPTR)->size) { in sci_break_ctl()
2190 spin_lock_irqsave(&port->lock, flags); in sci_break_ctl()
2194 if (break_state == -1) { in sci_break_ctl()
2204 spin_unlock_irqrestore(&port->lock, flags); in sci_break_ctl()
2212 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); in sci_startup()
2231 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); in sci_shutdown()
2233 s->autorts = false; in sci_shutdown()
2234 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); in sci_shutdown()
2236 spin_lock_irqsave(&port->lock, flags); in sci_shutdown()
2245 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); in sci_shutdown()
2246 spin_unlock_irqrestore(&port->lock, flags); in sci_shutdown()
2249 if (s->chan_rx_saved) { in sci_shutdown()
2250 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, in sci_shutdown()
2251 port->line); in sci_shutdown()
2252 hrtimer_cancel(&s->rx_timer); in sci_shutdown()
2256 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) in sci_shutdown()
2257 del_timer_sync(&s->rx_fifo_timer); in sci_shutdown()
2265 unsigned long freq = s->clk_rates[SCI_SCK]; in sci_sck_calc()
2269 if (s->port.type != PORT_HSCIF) in sci_sck_calc()
2273 err = DIV_ROUND_CLOSEST(freq, sr) - bps; in sci_sck_calc()
2278 *srr = sr - 1; in sci_sck_calc()
2284 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, in sci_sck_calc()
2296 if (s->port.type != PORT_HSCIF) in sci_brg_calc()
2303 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; in sci_brg_calc()
2309 *srr = sr - 1; in sci_brg_calc()
2315 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, in sci_brg_calc()
2325 unsigned long freq = s->clk_rates[SCI_FCK]; in sci_scbrr_calc()
2329 if (s->port.type != PORT_HSCIF) in sci_scbrr_calc()
2343 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - in sci_scbrr_calc()
2344 * (|D - 0.5| / N * (1 + F))| in sci_scbrr_calc()
2356 * err = freq / (br * prediv) - bps in sci_scbrr_calc()
2368 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; in sci_scbrr_calc()
2373 *brr = br - 1; in sci_scbrr_calc()
2374 *srr = sr - 1; in sci_scbrr_calc()
2383 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, in sci_scbrr_calc()
2394 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ in sci_reset()
2397 if (reg->size) in sci_reset()
2403 if (sci_getreg(port, SCLSR)->size) { in sci_reset()
2409 if (s->rx_trigger > 1) { in sci_reset()
2410 if (s->rx_fifo_timeout) { in sci_reset()
2412 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); in sci_reset()
2414 if (port->type == PORT_SCIFA || in sci_reset()
2415 port->type == PORT_SCIFB) in sci_reset()
2418 scif_set_rtrg(port, s->rx_trigger); in sci_reset()
2433 int best_clk = -1; in sci_set_termios()
2436 if ((termios->c_cflag & CSIZE) == CS7) { in sci_set_termios()
2439 termios->c_cflag &= ~CSIZE; in sci_set_termios()
2440 termios->c_cflag |= CS8; in sci_set_termios()
2442 if (termios->c_cflag & PARENB) in sci_set_termios()
2444 if (termios->c_cflag & PARODD) in sci_set_termios()
2446 if (termios->c_cflag & CSTOPB) in sci_set_termios()
2450 * earlyprintk comes here early on with port->uartclk set to zero. in sci_set_termios()
2453 * the baud rate is not programmed during earlyprintk - it is assumed in sci_set_termios()
2457 if (!port->uartclk) { in sci_set_termios()
2463 max_freq = max(max_freq, s->clk_rates[i]); in sci_set_termios()
2475 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && in sci_set_termios()
2476 port->type != PORT_SCIFB) { in sci_set_termios()
2490 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { in sci_set_termios()
2491 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, in sci_set_termios()
2506 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { in sci_set_termios()
2507 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, in sci_set_termios()
2534 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", in sci_set_termios()
2535 s->clks[best_clk], baud, min_err); in sci_set_termios()
2543 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { in sci_set_termios()
2548 spin_lock_irqsave(&port->lock, flags); in sci_set_termios()
2552 uart_update_timeout(port, termios->c_cflag, baud); in sci_set_termios()
2555 bits = tty_get_frame_size(termios->c_cflag); in sci_set_termios()
2557 if (sci_getreg(port, SEMR)->size) in sci_set_termios()
2561 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) in sci_set_termios()
2573 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); in sci_set_termios()
2576 if (sci_getreg(port, HSSRR)->size) { in sci_set_termios()
2581 int last_stop = bits * 2 - 1; in sci_set_termios()
2591 int shift = clamp(deviation / 2, -8, 7); in sci_set_termios()
2601 udelay((1000000 + (baud - 1)) / baud); in sci_set_termios()
2604 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); in sci_set_termios()
2607 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); in sci_set_termios()
2611 sci_init_pins(port, termios->c_cflag); in sci_set_termios()
2613 port->status &= ~UPSTAT_AUTOCTS; in sci_set_termios()
2614 s->autorts = false; in sci_set_termios()
2616 if (reg->size) { in sci_set_termios()
2617 unsigned short ctrl = serial_port_in(port, SCFCR); in sci_set_termios() local
2619 if ((port->flags & UPF_HARD_FLOW) && in sci_set_termios()
2620 (termios->c_cflag & CRTSCTS)) { in sci_set_termios()
2622 port->status |= UPSTAT_AUTOCTS; in sci_set_termios()
2624 s->autorts = true; in sci_set_termios()
2632 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); in sci_set_termios()
2634 serial_port_out(port, SCFCR, ctrl); in sci_set_termios()
2636 if (port->flags & UPF_HARD_FLOW) { in sci_set_termios()
2638 sci_set_mctrl(port, port->mctrl); in sci_set_termios()
2646 if (port->type != PORT_SCI) in sci_set_termios()
2648 scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); in sci_set_termios()
2649 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); in sci_set_termios()
2651 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { in sci_set_termios()
2662 s->rx_frame = (10000 * bits) / (baud / 100); in sci_set_termios()
2664 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; in sci_set_termios()
2667 if ((termios->c_cflag & CREAD) != 0) in sci_set_termios()
2670 spin_unlock_irqrestore(&port->lock, flags); in sci_set_termios()
2674 if (UART_ENABLE_MS(port, termios->c_cflag)) in sci_set_termios()
2695 switch (port->type) { in sci_type()
2720 if (port->membase) in sci_remap_port()
2723 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { in sci_remap_port()
2724 port->membase = ioremap(port->mapbase, sport->reg_size); in sci_remap_port()
2725 if (unlikely(!port->membase)) { in sci_remap_port()
2726 dev_err(port->dev, "can't remap port#%d\n", port->line); in sci_remap_port()
2727 return -ENXIO; in sci_remap_port()
2735 port->membase = (void __iomem *)(uintptr_t)port->mapbase; in sci_remap_port()
2745 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { in sci_release_port()
2746 iounmap(port->membase); in sci_release_port()
2747 port->membase = NULL; in sci_release_port()
2750 release_mem_region(port->mapbase, sport->reg_size); in sci_release_port()
2759 res = request_mem_region(port->mapbase, sport->reg_size, in sci_request_port()
2760 dev_name(port->dev)); in sci_request_port()
2762 dev_err(port->dev, "request_mem_region failed."); in sci_request_port()
2763 return -EBUSY; in sci_request_port()
2780 port->type = sport->cfg->type; in sci_config_port()
2787 if (ser->baud_base < 2400) in sci_verify_port()
2789 return -EINVAL; in sci_verify_port()
2830 if (sci_port->cfg->type == PORT_HSCIF) in sci_init_clocks()
2856 sci_port->clks[i] = clk; in sci_init_clocks()
2866 if (cfg->regtype != SCIx_PROBE_REGTYPE) in sci_probe_regmap()
2867 return &sci_port_params[cfg->regtype]; in sci_probe_regmap()
2869 switch (cfg->type) { in sci_probe_regmap()
2884 * The SH-4 is a bit of a misnomer here, although that's in sci_probe_regmap()
2906 struct uart_port *port = &sci_port->port; in sci_init_single()
2911 sci_port->cfg = p; in sci_init_single()
2913 port->ops = &sci_uart_ops; in sci_init_single()
2914 port->iotype = UPIO_MEM; in sci_init_single()
2915 port->line = index; in sci_init_single()
2916 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE); in sci_init_single()
2920 return -ENOMEM; in sci_init_single()
2922 port->mapbase = res->start; in sci_init_single()
2923 sci_port->reg_size = resource_size(res); in sci_init_single()
2925 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) { in sci_init_single()
2927 sci_port->irqs[i] = platform_get_irq_optional(dev, i); in sci_init_single()
2929 sci_port->irqs[i] = platform_get_irq(dev, i); in sci_init_single()
2936 if (p->type == PORT_SCI) in sci_init_single()
2937 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]); in sci_init_single()
2942 * In the non-muxed case, up to 6 interrupt signals might be generated in sci_init_single()
2946 if (sci_port->irqs[0] < 0) in sci_init_single()
2947 return -ENXIO; in sci_init_single()
2949 if (sci_port->irqs[1] < 0) in sci_init_single()
2950 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) in sci_init_single()
2951 sci_port->irqs[i] = sci_port->irqs[0]; in sci_init_single()
2953 sci_port->params = sci_probe_regmap(p); in sci_init_single()
2954 if (unlikely(sci_port->params == NULL)) in sci_init_single()
2955 return -EINVAL; in sci_init_single()
2957 switch (p->type) { in sci_init_single()
2959 sci_port->rx_trigger = 48; in sci_init_single()
2962 sci_port->rx_trigger = 64; in sci_init_single()
2965 sci_port->rx_trigger = 32; in sci_init_single()
2968 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) in sci_init_single()
2970 sci_port->rx_trigger = 1; in sci_init_single()
2972 sci_port->rx_trigger = 8; in sci_init_single()
2975 sci_port->rx_trigger = 1; in sci_init_single()
2979 sci_port->rx_fifo_timeout = 0; in sci_init_single()
2980 sci_port->hscif_tot = 0; in sci_init_single()
2986 sci_port->sampling_rate_mask = p->sampling_rate in sci_init_single()
2987 ? SCI_SR(p->sampling_rate) in sci_init_single()
2988 : sci_port->params->sampling_rate_mask; in sci_init_single()
2991 ret = sci_init_clocks(sci_port, &dev->dev); in sci_init_single()
2995 port->dev = &dev->dev; in sci_init_single()
2997 pm_runtime_enable(&dev->dev); in sci_init_single()
3000 port->type = p->type; in sci_init_single()
3001 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; in sci_init_single()
3002 port->fifosize = sci_port->params->fifosize; in sci_init_single()
3004 if (port->type == PORT_SCI && !dev->dev.of_node) { in sci_init_single()
3005 if (sci_port->reg_size >= 0x20) in sci_init_single()
3006 port->regshift = 2; in sci_init_single()
3008 port->regshift = 1; in sci_init_single()
3013 * for the multi-IRQ ports, which is where we are primarily in sci_init_single()
3018 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; in sci_init_single()
3019 port->irqflags = 0; in sci_init_single()
3021 port->serial_in = sci_serial_in; in sci_init_single()
3022 port->serial_out = sci_serial_out; in sci_init_single()
3029 pm_runtime_disable(port->port.dev); in sci_cleanup_single()
3046 struct sci_port *sci_port = &sci_ports[co->index]; in serial_console_write()
3047 struct uart_port *port = &sci_port->port; in serial_console_write()
3048 unsigned short bits, ctrl, ctrl_temp; in serial_console_write() local
3052 if (port->sysrq) in serial_console_write()
3055 locked = spin_trylock_irqsave(&port->lock, flags); in serial_console_write()
3057 spin_lock_irqsave(&port->lock, flags); in serial_console_write()
3060 ctrl = serial_port_in(port, SCSCR); in serial_console_write()
3062 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | in serial_console_write()
3063 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); in serial_console_write()
3064 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); in serial_console_write()
3074 serial_port_out(port, SCSCR, ctrl); in serial_console_write()
3077 spin_unlock_irqrestore(&port->lock, flags); in serial_console_write()
3093 if (co->index < 0 || co->index >= SCI_NPORTS) in serial_console_setup()
3094 return -ENODEV; in serial_console_setup()
3096 sci_port = &sci_ports[co->index]; in serial_console_setup()
3097 port = &sci_port->port; in serial_console_setup()
3102 if (!port->ops) in serial_console_setup()
3103 return -ENODEV; in serial_console_setup()
3121 .index = -1,
3146 .index = -1,
3151 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); in sci_probe_earlyprintk()
3154 return -EEXIST; in sci_probe_earlyprintk()
3156 early_serial_console.index = pdev->id; in sci_probe_earlyprintk()
3158 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); in sci_probe_earlyprintk()
3173 return -EINVAL; in sci_probe_earlyprintk()
3196 unsigned int type = port->port.type; /* uart_remove_... clears it */ in sci_remove()
3198 sci_ports_in_use &= ~BIT(port->port.line); in sci_remove()
3199 uart_remove_one_port(&sci_uart_driver, &port->port); in sci_remove()
3203 if (port->port.fifosize > 1) in sci_remove()
3204 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); in sci_remove()
3206 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); in sci_remove()
3217 /* SoC-specific types */
3219 .compatible = "renesas,scif-r7s72100",
3223 .compatible = "renesas,scif-r7s9210",
3227 .compatible = "renesas,scif-r9a07g044",
3230 /* Family-specific types */
3232 .compatible = "renesas,rcar-gen1-scif",
3235 .compatible = "renesas,rcar-gen2-scif",
3238 .compatible = "renesas,rcar-gen3-scif",
3241 .compatible = "renesas,rcar-gen4-scif",
3274 struct device_node *np = pdev->dev.of_node; in sci_parse_dt()
3282 return ERR_PTR(-EINVAL); in sci_parse_dt()
3284 data = of_device_get_match_data(&pdev->dev); in sci_parse_dt()
3286 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); in sci_parse_dt()
3288 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc), in sci_parse_dt()
3289 "failed to get reset ctrl\n")); in sci_parse_dt()
3293 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret); in sci_parse_dt()
3297 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc); in sci_parse_dt()
3299 dev_err(&pdev->dev, "failed to register assert devm action, %d\n", in sci_parse_dt()
3304 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); in sci_parse_dt()
3306 return ERR_PTR(-ENOMEM); in sci_parse_dt()
3313 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); in sci_parse_dt()
3314 return ERR_PTR(-EINVAL); in sci_parse_dt()
3317 dev_err(&pdev->dev, "serial%d out of range\n", id); in sci_parse_dt()
3318 return ERR_PTR(-EINVAL); in sci_parse_dt()
3324 p->type = SCI_OF_TYPE(data); in sci_parse_dt()
3325 p->regtype = SCI_OF_REGTYPE(data); in sci_parse_dt()
3327 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); in sci_parse_dt()
3341 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", in sci_probe_single()
3343 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); in sci_probe_single()
3344 return -EINVAL; in sci_probe_single()
3348 return -EBUSY; in sci_probe_single()
3364 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); in sci_probe_single()
3365 if (IS_ERR(sciport->gpios)) in sci_probe_single()
3366 return PTR_ERR(sciport->gpios); in sci_probe_single()
3368 if (sciport->has_rtscts) { in sci_probe_single()
3369 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) || in sci_probe_single()
3370 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) { in sci_probe_single()
3371 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); in sci_probe_single()
3372 return -EINVAL; in sci_probe_single()
3374 sciport->port.flags |= UPF_HARD_FLOW; in sci_probe_single()
3377 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); in sci_probe_single()
3403 if (dev->dev.of_node) { in sci_probe()
3408 p = dev->dev.platform_data; in sci_probe()
3410 dev_err(&dev->dev, "no platform data supplied\n"); in sci_probe()
3411 return -EINVAL; in sci_probe()
3414 dev_id = dev->id; in sci_probe()
3424 if (sp->port.fifosize > 1) { in sci_probe()
3425 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger); in sci_probe()
3429 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || in sci_probe()
3430 sp->port.type == PORT_HSCIF) { in sci_probe()
3431 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); in sci_probe()
3433 if (sp->port.fifosize > 1) { in sci_probe()
3434 device_remove_file(&dev->dev, in sci_probe()
3454 uart_suspend_port(&sci_uart_driver, &sport->port); in sci_suspend()
3464 uart_resume_port(&sci_uart_driver, &sport->port); in sci_resume()
3475 .name = "sh-sci",
3506 if (!device->port.membase) in early_console_setup()
3507 return -ENODEV; in early_console_setup()
3509 device->port.serial_in = sci_serial_in; in early_console_setup()
3510 device->port.serial_out = sci_serial_out; in early_console_setup()
3511 device->port.type = type; in early_console_setup()
3512 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); in early_console_setup()
3520 device->con->write = serial_console_write; in early_console_setup()
3558 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3559 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
3569 MODULE_ALIAS("platform:sh-sci");