Lines Matching refs:membase
191 st = readl(port->membase + UART_STAT); in mvebu_uart_tx_empty()
213 unsigned int ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
216 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
225 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port)); in mvebu_uart_start_tx()
229 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
231 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
238 ctl = readl(port->membase + UART_CTRL(port)); in mvebu_uart_stop_rx()
240 writel(ctl, port->membase + UART_CTRL(port)); in mvebu_uart_stop_rx()
242 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
244 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
253 ctl = readl(port->membase + UART_CTRL(port)); in mvebu_uart_break_ctl()
258 writel(ctl, port->membase + UART_CTRL(port)); in mvebu_uart_break_ctl()
271 ch = readl(port->membase + UART_RBR(port)); in mvebu_uart_rx_chars()
285 ret = readl(port->membase + UART_STAT); in mvebu_uart_rx_chars()
287 writel(ret, port->membase + UART_STAT); in mvebu_uart_rx_chars()
329 status = readl(port->membase + UART_STAT); in mvebu_uart_rx_chars()
340 !(readl(port->membase + UART_STAT) & STAT_TX_FIFO_FUL), in mvebu_uart_tx_chars()
341 writel(ch, port->membase + UART_TSH(port)), in mvebu_uart_tx_chars()
348 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_isr()
363 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_rx_isr()
375 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_tx_isr()
390 port->membase + UART_CTRL(port)); in mvebu_uart_startup()
394 ret = readl(port->membase + UART_STAT); in mvebu_uart_startup()
396 writel(ret, port->membase + UART_STAT); in mvebu_uart_startup()
398 writel(CTRL_BRK_INT, port->membase + UART_CTRL(port)); in mvebu_uart_startup()
400 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_startup()
402 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_startup()
445 writel(0, port->membase + UART_INTR(port)); in mvebu_uart_shutdown()
520 brdv = readl(port->membase + UART_BRDV); in mvebu_uart_baud_rate_set()
523 writel(brdv, port->membase + UART_BRDV); in mvebu_uart_baud_rate_set()
526 osamp = readl(port->membase + UART_OSAMP); in mvebu_uart_baud_rate_set()
531 writel(osamp, port->membase + UART_OSAMP); in mvebu_uart_baud_rate_set()
613 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_get_poll_char()
618 return readl(port->membase + UART_RBR(port)); in mvebu_uart_get_poll_char()
626 st = readl(port->membase + UART_STAT); in mvebu_uart_put_poll_char()
634 writel(c, port->membase + UART_TSH(port)); in mvebu_uart_put_poll_char()
667 st = readl(port->membase + UART_STAT); in mvebu_uart_putc()
673 writel(c, port->membase + UART_STD_TSH); in mvebu_uart_putc()
676 st = readl(port->membase + UART_STAT); in mvebu_uart_putc()
695 if (!device->port.membase) in mvebu_uart_early_console_setup()
711 readl_poll_timeout_atomic(port->membase + UART_STAT, val, in wait_for_xmitr()
719 readl_poll_timeout_atomic(port->membase + UART_STAT, val, in wait_for_xmite()
726 writel(ch, port->membase + UART_TSH(port)); in mvebu_uart_console_putchar()
742 ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT; in mvebu_uart_console_write()
743 intr = readl(port->membase + UART_INTR(port)) & in mvebu_uart_console_write()
745 writel(0, port->membase + UART_CTRL(port)); in mvebu_uart_console_write()
746 writel(0, port->membase + UART_INTR(port)); in mvebu_uart_console_write()
753 writel(ier, port->membase + UART_CTRL(port)); in mvebu_uart_console_write()
756 ctl = intr | readl(port->membase + UART_INTR(port)); in mvebu_uart_console_write()
757 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_console_write()
777 if (!port->mapbase || !port->membase) { in mvebu_uart_console_setup()
830 mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port)); in mvebu_uart_suspend()
831 mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port)); in mvebu_uart_suspend()
832 mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port)); in mvebu_uart_suspend()
833 mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port)); in mvebu_uart_suspend()
834 mvuart->pm_regs.stat = readl(port->membase + UART_STAT); in mvebu_uart_suspend()
836 mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV); in mvebu_uart_suspend()
838 mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP); in mvebu_uart_suspend()
851 writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port)); in mvebu_uart_resume()
852 writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port)); in mvebu_uart_resume()
853 writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port)); in mvebu_uart_resume()
854 writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port)); in mvebu_uart_resume()
855 writel(mvuart->pm_regs.stat, port->membase + UART_STAT); in mvebu_uart_resume()
857 writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV); in mvebu_uart_resume()
859 writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP); in mvebu_uart_resume()
921 port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, ®); in mvebu_uart_probe()
922 if (IS_ERR(port->membase)) in mvebu_uart_probe()
923 return PTR_ERR(port->membase); in mvebu_uart_probe()
981 writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port)); in mvebu_uart_probe()
983 writel(0, port->membase + UART_CTRL(port)); in mvebu_uart_probe()