Lines Matching +full:rs485 +full:- +full:rts +full:- +full:active +full:- +full:low
1 // SPDX-License-Identifier: GPL-2.0+
29 #include <linux/dma-mapping.h>
32 #include <linux/dma/imx-dma.h>
73 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
81 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
123 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
126 #define USR1_RTSS (1<<14) /* RTS pin status */
128 #define USR1_RTSD (1<<12) /* RTS delta */
146 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
159 /* We've been assigned a range on the "Low-density serial ports" major */
172 #define DRIVER_NAME "IMX-uart"
263 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
264 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
265 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
266 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
273 writel(val, sport->port.membase + offset); in imx_uart_writel()
278 return readl(sport->port.membase + offset); in imx_uart_readl()
283 return sport->devdata->uts_reg; in imx_uart_uts_reg()
288 return sport->devdata->devtype == IMX1_UART; in imx_uart_is_imx1()
299 ucr->ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_ucrs_save()
300 ucr->ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_ucrs_save()
301 ucr->ucr3 = imx_uart_readl(sport, UCR3); in imx_uart_ucrs_save()
308 imx_uart_writel(sport, ucr->ucr1, UCR1); in imx_uart_ucrs_restore()
309 imx_uart_writel(sport, ucr->ucr2, UCR2); in imx_uart_ucrs_restore()
310 imx_uart_writel(sport, ucr->ucr3, UCR3); in imx_uart_ucrs_restore()
319 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS); in imx_uart_rts_active()
328 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS); in imx_uart_rts_inactive()
347 * and UTS[6-3]". in imx_uart_soft_reset()
360 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) in imx_uart_soft_reset()
368 sport->idle_counter = 0; in imx_uart_soft_reset()
392 if (sport->dma_is_enabled) { in imx_uart_start_rx()
411 if (sport->tx_state == OFF) in imx_uart_stop_tx()
418 if (sport->dma_is_txing) in imx_uart_stop_tx()
434 /* in rs485 mode disable transmitter */ in imx_uart_stop_tx()
435 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_stop_tx()
436 if (sport->tx_state == SEND) { in imx_uart_stop_tx()
437 sport->tx_state = WAIT_AFTER_SEND; in imx_uart_stop_tx()
439 if (port->rs485.delay_rts_after_send > 0) { in imx_uart_stop_tx()
440 start_hrtimer_ms(&sport->trigger_stop_tx, in imx_uart_stop_tx()
441 port->rs485.delay_rts_after_send); in imx_uart_stop_tx()
448 if (sport->tx_state == WAIT_AFTER_RTS || in imx_uart_stop_tx()
449 sport->tx_state == WAIT_AFTER_SEND) { in imx_uart_stop_tx()
452 hrtimer_try_to_cancel(&sport->trigger_start_tx); in imx_uart_stop_tx()
455 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_stop_tx()
461 if (!port->rs485_rx_during_tx_gpio) in imx_uart_stop_tx()
464 sport->tx_state = OFF; in imx_uart_stop_tx()
467 sport->tx_state = OFF; in imx_uart_stop_tx()
481 if (sport->dma_is_enabled) { in imx_uart_stop_rx()
492 if (port->rs485.flags & SER_RS485_ENABLED && in imx_uart_stop_rx()
493 port->rs485.flags & SER_RS485_RTS_ON_SEND && in imx_uart_stop_rx()
494 sport->have_rtscts && !sport->have_rtsgpio) { in imx_uart_stop_rx()
511 mod_timer(&sport->timer, jiffies); in imx_uart_enable_ms()
513 mctrl_gpio_enable_ms(sport->gpios); in imx_uart_enable_ms()
521 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_transmit_buffer()
523 if (sport->port.x_char) { in imx_uart_transmit_buffer()
525 imx_uart_writel(sport, sport->port.x_char, URTX0); in imx_uart_transmit_buffer()
526 sport->port.icount.tx++; in imx_uart_transmit_buffer()
527 sport->port.x_char = 0; in imx_uart_transmit_buffer()
531 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { in imx_uart_transmit_buffer()
532 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
536 if (sport->dma_is_enabled) { in imx_uart_transmit_buffer()
539 * We've just sent a X-char Ensure the TX DMA is enabled in imx_uart_transmit_buffer()
544 if (sport->dma_is_txing) { in imx_uart_transmit_buffer()
557 /* send xmit->buf[xmit->tail] in imx_uart_transmit_buffer()
559 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); in imx_uart_transmit_buffer()
560 uart_xmit_advance(&sport->port, 1); in imx_uart_transmit_buffer()
564 uart_write_wakeup(&sport->port); in imx_uart_transmit_buffer()
567 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
573 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_dma_tx_callback()
574 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_dma_tx_callback()
578 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_dma_tx_callback()
580 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx_callback()
586 uart_xmit_advance(&sport->port, sport->tx_bytes); in imx_uart_dma_tx_callback()
588 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); in imx_uart_dma_tx_callback()
590 sport->dma_is_txing = 0; in imx_uart_dma_tx_callback()
593 uart_write_wakeup(&sport->port); in imx_uart_dma_tx_callback()
595 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) in imx_uart_dma_tx_callback()
597 else if (sport->port.rs485.flags & SER_RS485_ENABLED) { in imx_uart_dma_tx_callback()
603 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_dma_tx_callback()
609 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_dma_tx()
610 struct scatterlist *sgl = sport->tx_sgl; in imx_uart_dma_tx()
612 struct dma_chan *chan = sport->dma_chan_tx; in imx_uart_dma_tx()
613 struct device *dev = sport->port.dev; in imx_uart_dma_tx()
617 if (sport->dma_is_txing) in imx_uart_dma_tx()
624 sport->tx_bytes = uart_circ_chars_pending(xmit); in imx_uart_dma_tx()
626 if (xmit->tail < xmit->head || xmit->head == 0) { in imx_uart_dma_tx()
627 sport->dma_tx_nents = 1; in imx_uart_dma_tx()
628 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); in imx_uart_dma_tx()
630 sport->dma_tx_nents = 2; in imx_uart_dma_tx()
632 sg_set_buf(sgl, xmit->buf + xmit->tail, in imx_uart_dma_tx()
633 UART_XMIT_SIZE - xmit->tail); in imx_uart_dma_tx()
634 sg_set_buf(sgl + 1, xmit->buf, xmit->head); in imx_uart_dma_tx()
637 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx()
645 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, in imx_uart_dma_tx()
650 desc->callback = imx_uart_dma_tx_callback; in imx_uart_dma_tx()
651 desc->callback_param = sport; in imx_uart_dma_tx()
661 sport->dma_is_txing = 1; in imx_uart_dma_tx()
673 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) in imx_uart_start_tx()
677 * We cannot simply do nothing here if sport->tx_state == SEND already in imx_uart_start_tx()
682 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_start_tx()
683 if (sport->tx_state == OFF) { in imx_uart_start_tx()
685 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) in imx_uart_start_tx()
691 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX) && in imx_uart_start_tx()
692 !port->rs485_rx_during_tx_gpio) in imx_uart_start_tx()
695 sport->tx_state = WAIT_AFTER_RTS; in imx_uart_start_tx()
697 if (port->rs485.delay_rts_before_send > 0) { in imx_uart_start_tx()
698 start_hrtimer_ms(&sport->trigger_start_tx, in imx_uart_start_tx()
699 port->rs485.delay_rts_before_send); in imx_uart_start_tx()
706 if (sport->tx_state == WAIT_AFTER_SEND in imx_uart_start_tx()
707 || sport->tx_state == WAIT_AFTER_RTS) { in imx_uart_start_tx()
709 hrtimer_try_to_cancel(&sport->trigger_stop_tx); in imx_uart_start_tx()
714 * tx-callback. in imx_uart_start_tx()
716 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
722 sport->tx_state = SEND; in imx_uart_start_tx()
725 sport->tx_state = SEND; in imx_uart_start_tx()
728 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
733 if (sport->dma_is_enabled) { in imx_uart_start_tx()
734 if (sport->port.x_char) { in imx_uart_start_tx()
735 /* We have X-char to send, so enable TX IRQ and in imx_uart_start_tx()
736 * disable TX DMA to let TX interrupt to send X-char */ in imx_uart_start_tx()
744 if (!uart_circ_empty(&port->state->xmit) && in imx_uart_start_tx()
758 uart_handle_cts_change(&sport->port, usr1); in __imx_uart_rtsint()
759 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in __imx_uart_rtsint()
769 spin_lock(&sport->port.lock); in imx_uart_rtsint()
773 spin_unlock(&sport->port.lock); in imx_uart_rtsint()
782 spin_lock(&sport->port.lock); in imx_uart_txint()
784 spin_unlock(&sport->port.lock); in imx_uart_txint()
822 * We count interrupts, not chars in 'idle-counter' for simplicity. in imx_uart_check_flood()
827 sport->idle_counter = 0; in imx_uart_check_flood()
828 } else if (++sport->idle_counter > 3) { in imx_uart_check_flood()
829 dev_warn(sport->port.dev, "RX flood detected: soft reset."); in imx_uart_check_flood()
830 imx_uart_soft_reset(sport); /* also clears 'sport->idle_counter' */ in imx_uart_check_flood()
837 struct tty_port *port = &sport->port.state->port; in __imx_uart_rxint()
847 sport->port.icount.rx++; in __imx_uart_rxint()
851 sport->port.icount.brk++; in __imx_uart_rxint()
852 if (uart_handle_break(&sport->port)) in __imx_uart_rxint()
856 sport->port.icount.parity++; in __imx_uart_rxint()
858 sport->port.icount.frame++; in __imx_uart_rxint()
860 sport->port.icount.overrun++; in __imx_uart_rxint()
862 if (rx & sport->port.ignore_status_mask) in __imx_uart_rxint()
865 rx &= (sport->port.read_status_mask | 0xFF); in __imx_uart_rxint()
876 sport->port.sysrq = 0; in __imx_uart_rxint()
877 } else if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) { in __imx_uart_rxint()
881 if (sport->port.ignore_status_mask & URXD_DUMMY_READ) in __imx_uart_rxint()
885 sport->port.icount.buf_overrun++; in __imx_uart_rxint()
898 spin_lock(&sport->port.lock); in imx_uart_rxint()
902 spin_unlock(&sport->port.lock); in imx_uart_rxint()
910 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
925 if (sport->dte_mode) in imx_uart_get_hwmctrl()
940 changed = status ^ sport->old_status; in imx_uart_mctrl_check()
945 sport->old_status = status; in imx_uart_mctrl_check()
948 sport->port.icount.rng++; in imx_uart_mctrl_check()
950 sport->port.icount.dsr++; in imx_uart_mctrl_check()
952 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); in imx_uart_mctrl_check()
954 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); in imx_uart_mctrl_check()
956 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in imx_uart_mctrl_check()
965 spin_lock(&sport->port.lock); in imx_uart_int()
1030 sport->port.icount.overrun++; in imx_uart_int()
1035 spin_unlock(&sport->port.lock); in imx_uart_int()
1051 if (sport->dma_is_txing) in imx_uart_tx_empty()
1063 mctrl_gpio_get(sport->gpios, &ret); in imx_uart_get_mctrl()
1074 if (!(port->rs485.flags & SER_RS485_ENABLED)) { in imx_uart_set_mctrl()
1078 * Turn off autoRTS if RTS is lowered and restore autoRTS in imx_uart_set_mctrl()
1079 * setting if RTS is raised. in imx_uart_set_mctrl()
1106 mctrl_gpio_set(sport->gpios, mctrl); in imx_uart_set_mctrl()
1118 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_break_ctl()
1127 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_break_ctl()
1131 * This is our per-port timeout handler, for checking the
1139 if (sport->port.state) { in imx_uart_timeout()
1140 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_timeout()
1142 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_timeout()
1144 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); in imx_uart_timeout()
1159 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_dma_rx_callback()
1160 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_dma_rx_callback()
1161 struct tty_port *port = &sport->port.state->port; in imx_uart_dma_rx_callback()
1163 struct circ_buf *rx_ring = &sport->rx_ring; in imx_uart_dma_rx_callback()
1169 status = dmaengine_tx_status(chan, sport->rx_cookie, &state); in imx_uart_dma_rx_callback()
1172 spin_lock(&sport->port.lock); in imx_uart_dma_rx_callback()
1174 spin_unlock(&sport->port.lock); in imx_uart_dma_rx_callback()
1179 * The state-residue variable represents the empty space in imx_uart_dma_rx_callback()
1182 * length - DMA transaction residue. The UART script from the in imx_uart_dma_rx_callback()
1184 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). in imx_uart_dma_rx_callback()
1190 rx_ring->head = sg_dma_len(sgl) - state.residue; in imx_uart_dma_rx_callback()
1193 bd_size = sg_dma_len(sgl) / sport->rx_periods; in imx_uart_dma_rx_callback()
1194 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; in imx_uart_dma_rx_callback()
1196 if (rx_ring->head <= sg_dma_len(sgl) && in imx_uart_dma_rx_callback()
1197 rx_ring->head > rx_ring->tail) { in imx_uart_dma_rx_callback()
1200 r_bytes = rx_ring->head - rx_ring->tail; in imx_uart_dma_rx_callback()
1203 spin_lock(&sport->port.lock); in imx_uart_dma_rx_callback()
1205 spin_unlock(&sport->port.lock); in imx_uart_dma_rx_callback()
1207 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { in imx_uart_dma_rx_callback()
1210 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1214 sport->rx_buf + rx_ring->tail, r_bytes); in imx_uart_dma_rx_callback()
1217 dma_sync_sg_for_device(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1221 sport->port.icount.buf_overrun++; in imx_uart_dma_rx_callback()
1223 sport->port.icount.rx += w_bytes; in imx_uart_dma_rx_callback()
1226 WARN_ON(rx_ring->head > sg_dma_len(sgl)); in imx_uart_dma_rx_callback()
1227 WARN_ON(rx_ring->head <= rx_ring->tail); in imx_uart_dma_rx_callback()
1232 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); in imx_uart_dma_rx_callback()
1238 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_start_rx_dma()
1239 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_start_rx_dma()
1240 struct device *dev = sport->port.dev; in imx_uart_start_rx_dma()
1244 sport->rx_ring.head = 0; in imx_uart_start_rx_dma()
1245 sport->rx_ring.tail = 0; in imx_uart_start_rx_dma()
1247 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size); in imx_uart_start_rx_dma()
1251 return -EINVAL; in imx_uart_start_rx_dma()
1255 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, in imx_uart_start_rx_dma()
1261 return -EINVAL; in imx_uart_start_rx_dma()
1263 desc->callback = imx_uart_dma_rx_callback; in imx_uart_start_rx_dma()
1264 desc->callback_param = sport; in imx_uart_start_rx_dma()
1267 sport->dma_is_rxing = 1; in imx_uart_start_rx_dma()
1268 sport->rx_cookie = dmaengine_submit(desc); in imx_uart_start_rx_dma()
1275 struct tty_port *port = &sport->port.state->port; in imx_uart_clear_rx_errors()
1282 sport->port.icount.brk++; in imx_uart_clear_rx_errors()
1284 uart_handle_break(&sport->port); in imx_uart_clear_rx_errors()
1286 sport->port.icount.buf_overrun++; in imx_uart_clear_rx_errors()
1290 sport->port.icount.frame++; in imx_uart_clear_rx_errors()
1293 sport->port.icount.parity++; in imx_uart_clear_rx_errors()
1299 sport->port.icount.overrun++; in imx_uart_clear_rx_errors()
1303 sport->idle_counter = 0; in imx_uart_clear_rx_errors()
1325 if (sport->dma_chan_rx) { in imx_uart_dma_exit()
1326 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_dma_exit()
1327 dma_release_channel(sport->dma_chan_rx); in imx_uart_dma_exit()
1328 sport->dma_chan_rx = NULL; in imx_uart_dma_exit()
1329 sport->rx_cookie = -EINVAL; in imx_uart_dma_exit()
1330 kfree(sport->rx_buf); in imx_uart_dma_exit()
1331 sport->rx_buf = NULL; in imx_uart_dma_exit()
1334 if (sport->dma_chan_tx) { in imx_uart_dma_exit()
1335 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_dma_exit()
1336 dma_release_channel(sport->dma_chan_tx); in imx_uart_dma_exit()
1337 sport->dma_chan_tx = NULL; in imx_uart_dma_exit()
1344 struct device *dev = sport->port.dev; in imx_uart_dma_init()
1348 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); in imx_uart_dma_init()
1349 if (!sport->dma_chan_rx) { in imx_uart_dma_init()
1351 ret = -EINVAL; in imx_uart_dma_init()
1356 slave_config.src_addr = sport->port.mapbase + URXD0; in imx_uart_dma_init()
1359 slave_config.src_maxburst = RXTL_DMA - 1; in imx_uart_dma_init()
1360 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); in imx_uart_dma_init()
1366 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods; in imx_uart_dma_init()
1367 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL); in imx_uart_dma_init()
1368 if (!sport->rx_buf) { in imx_uart_dma_init()
1369 ret = -ENOMEM; in imx_uart_dma_init()
1372 sport->rx_ring.buf = sport->rx_buf; in imx_uart_dma_init()
1375 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); in imx_uart_dma_init()
1376 if (!sport->dma_chan_tx) { in imx_uart_dma_init()
1378 ret = -EINVAL; in imx_uart_dma_init()
1383 slave_config.dst_addr = sport->port.mapbase + URTX0; in imx_uart_dma_init()
1386 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); in imx_uart_dma_init()
1409 sport->dma_is_enabled = 1; in imx_uart_enable_dma()
1423 sport->dma_is_enabled = 0; in imx_uart_disable_dma()
1437 retval = clk_prepare_enable(sport->clk_per); in imx_uart_startup()
1440 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_startup()
1442 clk_disable_unprepare(sport->clk_per); in imx_uart_startup()
1463 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_startup()
1476 if (sport->have_rtscts) in imx_uart_startup()
1484 if (sport->inverted_rx) in imx_uart_startup()
1492 if (sport->inverted_tx) in imx_uart_startup()
1498 if (sport->dte_mode) in imx_uart_startup()
1506 if (!sport->have_rtscts) in imx_uart_startup()
1509 * make sure the edge sensitive RTS-irq is disabled, in imx_uart_startup()
1519 imx_uart_enable_ms(&sport->port); in imx_uart_startup()
1536 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_startup()
1547 if (sport->dma_is_enabled) { in imx_uart_shutdown()
1548 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_shutdown()
1549 if (sport->dma_is_txing) { in imx_uart_shutdown()
1550 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], in imx_uart_shutdown()
1551 sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_shutdown()
1552 sport->dma_is_txing = 0; in imx_uart_shutdown()
1554 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_shutdown()
1555 if (sport->dma_is_rxing) { in imx_uart_shutdown()
1556 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, in imx_uart_shutdown()
1558 sport->dma_is_rxing = 0; in imx_uart_shutdown()
1561 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1565 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1569 mctrl_gpio_disable_ms(sport->gpios); in imx_uart_shutdown()
1571 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1575 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1580 del_timer_sync(&sport->timer); in imx_uart_shutdown()
1586 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1592 if (port->rs485.flags & SER_RS485_ENABLED && in imx_uart_shutdown()
1593 port->rs485.flags & SER_RS485_RTS_ON_SEND && in imx_uart_shutdown()
1594 sport->have_rtscts && !sport->have_rtsgpio) { in imx_uart_shutdown()
1608 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1610 clk_disable_unprepare(sport->clk_per); in imx_uart_shutdown()
1611 clk_disable_unprepare(sport->clk_ipg); in imx_uart_shutdown()
1618 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_flush_buffer()
1620 if (!sport->dma_chan_tx) in imx_uart_flush_buffer()
1623 sport->tx_bytes = 0; in imx_uart_flush_buffer()
1624 dmaengine_terminate_all(sport->dma_chan_tx); in imx_uart_flush_buffer()
1625 if (sport->dma_is_txing) { in imx_uart_flush_buffer()
1628 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, in imx_uart_flush_buffer()
1633 sport->dma_is_txing = 0; in imx_uart_flush_buffer()
1648 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in imx_uart_set_termios()
1656 while ((termios->c_cflag & CSIZE) != CS7 && in imx_uart_set_termios()
1657 (termios->c_cflag & CSIZE) != CS8) { in imx_uart_set_termios()
1658 termios->c_cflag &= ~CSIZE; in imx_uart_set_termios()
1659 termios->c_cflag |= old_csize; in imx_uart_set_termios()
1663 del_timer_sync(&sport->timer); in imx_uart_set_termios()
1668 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); in imx_uart_set_termios()
1671 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_set_termios()
1681 if ((termios->c_cflag & CSIZE) == CS8) in imx_uart_set_termios()
1684 if (!sport->have_rtscts) in imx_uart_set_termios()
1685 termios->c_cflag &= ~CRTSCTS; in imx_uart_set_termios()
1687 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_set_termios()
1689 * RTS is mandatory for rs485 operation, so keep in imx_uart_set_termios()
1693 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_set_termios()
1698 } else if (termios->c_cflag & CRTSCTS) { in imx_uart_set_termios()
1700 * Only let receiver control RTS output if we were not requested in imx_uart_set_termios()
1701 * to have RTS inactive (which then should take precedence). in imx_uart_set_termios()
1707 if (termios->c_cflag & CRTSCTS) in imx_uart_set_termios()
1709 if (termios->c_cflag & CSTOPB) in imx_uart_set_termios()
1711 if (termios->c_cflag & PARENB) { in imx_uart_set_termios()
1713 if (termios->c_cflag & PARODD) in imx_uart_set_termios()
1717 sport->port.read_status_mask = 0; in imx_uart_set_termios()
1718 if (termios->c_iflag & INPCK) in imx_uart_set_termios()
1719 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); in imx_uart_set_termios()
1720 if (termios->c_iflag & (BRKINT | PARMRK)) in imx_uart_set_termios()
1721 sport->port.read_status_mask |= URXD_BRK; in imx_uart_set_termios()
1726 sport->port.ignore_status_mask = 0; in imx_uart_set_termios()
1727 if (termios->c_iflag & IGNPAR) in imx_uart_set_termios()
1728 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; in imx_uart_set_termios()
1729 if (termios->c_iflag & IGNBRK) { in imx_uart_set_termios()
1730 sport->port.ignore_status_mask |= URXD_BRK; in imx_uart_set_termios()
1735 if (termios->c_iflag & IGNPAR) in imx_uart_set_termios()
1736 sport->port.ignore_status_mask |= URXD_OVRRUN; in imx_uart_set_termios()
1739 if ((termios->c_cflag & CREAD) == 0) in imx_uart_set_termios()
1740 sport->port.ignore_status_mask |= URXD_DUMMY_READ; in imx_uart_set_termios()
1743 * Update the per-port timeout. in imx_uart_set_termios()
1745 uart_update_timeout(port, termios->c_cflag, baud); in imx_uart_set_termios()
1747 /* custom-baudrate handling */ in imx_uart_set_termios()
1748 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1750 baud = sport->port.uartclk / (quot * 16); in imx_uart_set_termios()
1752 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1758 rational_best_approximation(16 * div * baud, sport->port.uartclk, in imx_uart_set_termios()
1761 tdiv64 = sport->port.uartclk; in imx_uart_set_termios()
1767 num -= 1; in imx_uart_set_termios()
1768 denom -= 1; in imx_uart_set_termios()
1781 * RTS/CTS handshake and suddenly gets broken bytes. in imx_uart_set_termios()
1791 imx_uart_writel(sport, sport->port.uartclk / div / 1000, in imx_uart_set_termios()
1796 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) in imx_uart_set_termios()
1797 imx_uart_enable_ms(&sport->port); in imx_uart_set_termios()
1799 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_set_termios()
1804 return port->type == PORT_IMX ? "IMX" : NULL; in imx_uart_type()
1813 port->type = PORT_IMX; in imx_uart_config_port()
1826 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) in imx_uart_verify_port()
1827 ret = -EINVAL; in imx_uart_verify_port()
1828 if (port->irq != ser->irq) in imx_uart_verify_port()
1829 ret = -EINVAL; in imx_uart_verify_port()
1830 if (ser->io_type != UPIO_MEM) in imx_uart_verify_port()
1831 ret = -EINVAL; in imx_uart_verify_port()
1832 if (port->uartclk / 16 != ser->baud_base) in imx_uart_verify_port()
1833 ret = -EINVAL; in imx_uart_verify_port()
1834 if (port->mapbase != (unsigned long)ser->iomem_base) in imx_uart_verify_port()
1835 ret = -EINVAL; in imx_uart_verify_port()
1836 if (port->iobase != ser->port) in imx_uart_verify_port()
1837 ret = -EINVAL; in imx_uart_verify_port()
1838 if (ser->hub6 != 0) in imx_uart_verify_port()
1839 ret = -EINVAL; in imx_uart_verify_port()
1852 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_poll_init()
1855 retval = clk_prepare_enable(sport->clk_per); in imx_uart_poll_init()
1857 clk_disable_unprepare(sport->clk_ipg); in imx_uart_poll_init()
1861 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_poll_init()
1889 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_poll_init()
1930 if (rs485conf->flags & SER_RS485_ENABLED) { in imx_uart_rs485_config()
1931 /* Enable receiver if low-active RTS signal is requested */ in imx_uart_rs485_config()
1932 if (sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_rs485_config()
1933 !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) in imx_uart_rs485_config()
1934 rs485conf->flags |= SER_RS485_RX_DURING_TX; in imx_uart_rs485_config()
1938 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_rs485_config()
1945 /* Make sure Rx is enabled in case Tx is active with Rx disabled */ in imx_uart_rs485_config()
1946 if (!(rs485conf->flags & SER_RS485_ENABLED) || in imx_uart_rs485_config()
1947 rs485conf->flags & SER_RS485_RX_DURING_TX) in imx_uart_rs485_config()
1950 if (port->rs485_rx_during_tx_gpio) in imx_uart_rs485_config()
1951 gpiod_set_value_cansleep(port->rs485_rx_during_tx_gpio, in imx_uart_rs485_config()
1952 !!(rs485conf->flags & SER_RS485_RX_DURING_TX)); in imx_uart_rs485_config()
1999 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_write()
2005 if (sport->port.sysrq) in imx_uart_console_write()
2008 locked = spin_trylock_irqsave(&sport->port.lock, flags); in imx_uart_console_write()
2010 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_console_write()
2027 uart_console_write(&sport->port, s, count, imx_uart_console_putchar); in imx_uart_console_write()
2038 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_console_write()
2078 ucfr_rfdiv = 6 - ucfr_rfdiv; in imx_uart_console_get_options()
2080 uartclk = clk_get_rate(sport->clk_per); in imx_uart_console_get_options()
2099 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", in imx_uart_console_get_options()
2119 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) in imx_uart_console_setup()
2120 co->index = 0; in imx_uart_console_setup()
2121 sport = imx_uart_ports[co->index]; in imx_uart_console_setup()
2123 return -ENODEV; in imx_uart_console_setup()
2126 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_console_setup()
2137 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); in imx_uart_console_setup()
2140 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2144 retval = clk_prepare_enable(sport->clk_per); in imx_uart_console_setup()
2146 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2155 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_exit()
2157 clk_disable_unprepare(sport->clk_per); in imx_uart_console_exit()
2158 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_exit()
2171 .index = -1,
2196 spin_lock_irqsave(&sport->port.lock, flags); in imx_trigger_start_tx()
2197 if (sport->tx_state == WAIT_AFTER_RTS) in imx_trigger_start_tx()
2198 imx_uart_start_tx(&sport->port); in imx_trigger_start_tx()
2199 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_trigger_start_tx()
2209 spin_lock_irqsave(&sport->port.lock, flags); in imx_trigger_stop_tx()
2210 if (sport->tx_state == WAIT_AFTER_SEND) in imx_trigger_stop_tx()
2211 imx_uart_stop_tx(&sport->port); in imx_trigger_stop_tx()
2212 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_trigger_stop_tx()
2217 static const struct serial_rs485 imx_no_rs485 = {}; /* No RS485 if no RTS */
2231 struct device_node *np = pdev->dev.of_node; in imx_uart_probe()
2240 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); in imx_uart_probe()
2242 return -ENOMEM; in imx_uart_probe()
2244 sport->devdata = of_device_get_match_data(&pdev->dev); in imx_uart_probe()
2248 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); in imx_uart_probe()
2251 sport->port.line = ret; in imx_uart_probe()
2253 sport->have_rtscts = of_property_read_bool(np, "uart-has-rtscts") || in imx_uart_probe()
2254 of_property_read_bool(np, "fsl,uart-has-rtscts"); /* deprecated */ in imx_uart_probe()
2256 sport->dte_mode = of_property_read_bool(np, "fsl,dte-mode"); in imx_uart_probe()
2258 sport->have_rtsgpio = of_property_present(np, "rts-gpios"); in imx_uart_probe()
2260 sport->inverted_tx = of_property_read_bool(np, "fsl,inverted-tx"); in imx_uart_probe()
2262 sport->inverted_rx = of_property_read_bool(np, "fsl,inverted-rx"); in imx_uart_probe()
2264 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) { in imx_uart_probe()
2265 sport->rx_period_length = dma_buf_conf[0]; in imx_uart_probe()
2266 sport->rx_periods = dma_buf_conf[1]; in imx_uart_probe()
2268 sport->rx_period_length = RX_DMA_PERIOD_LEN; in imx_uart_probe()
2269 sport->rx_periods = RX_DMA_PERIODS; in imx_uart_probe()
2272 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { in imx_uart_probe()
2273 dev_err(&pdev->dev, "serial%d out of range\n", in imx_uart_probe()
2274 sport->port.line); in imx_uart_probe()
2275 return -EINVAL; in imx_uart_probe()
2288 sport->port.dev = &pdev->dev; in imx_uart_probe()
2289 sport->port.mapbase = res->start; in imx_uart_probe()
2290 sport->port.membase = base; in imx_uart_probe()
2291 sport->port.type = PORT_IMX; in imx_uart_probe()
2292 sport->port.iotype = UPIO_MEM; in imx_uart_probe()
2293 sport->port.irq = rxirq; in imx_uart_probe()
2294 sport->port.fifosize = 32; in imx_uart_probe()
2295 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE); in imx_uart_probe()
2296 sport->port.ops = &imx_uart_pops; in imx_uart_probe()
2297 sport->port.rs485_config = imx_uart_rs485_config; in imx_uart_probe()
2298 /* RTS is required to control the RS485 transmitter */ in imx_uart_probe()
2299 if (sport->have_rtscts || sport->have_rtsgpio) in imx_uart_probe()
2300 sport->port.rs485_supported = imx_rs485_supported; in imx_uart_probe()
2302 sport->port.rs485_supported = imx_no_rs485; in imx_uart_probe()
2303 sport->port.flags = UPF_BOOT_AUTOCONF; in imx_uart_probe()
2304 timer_setup(&sport->timer, imx_uart_timeout, 0); in imx_uart_probe()
2306 sport->gpios = mctrl_gpio_init(&sport->port, 0); in imx_uart_probe()
2307 if (IS_ERR(sport->gpios)) in imx_uart_probe()
2308 return PTR_ERR(sport->gpios); in imx_uart_probe()
2310 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in imx_uart_probe()
2311 if (IS_ERR(sport->clk_ipg)) { in imx_uart_probe()
2312 ret = PTR_ERR(sport->clk_ipg); in imx_uart_probe()
2313 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); in imx_uart_probe()
2317 sport->clk_per = devm_clk_get(&pdev->dev, "per"); in imx_uart_probe()
2318 if (IS_ERR(sport->clk_per)) { in imx_uart_probe()
2319 ret = PTR_ERR(sport->clk_per); in imx_uart_probe()
2320 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); in imx_uart_probe()
2324 sport->port.uartclk = clk_get_rate(sport->clk_per); in imx_uart_probe()
2327 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_probe()
2329 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); in imx_uart_probe()
2333 ret = uart_get_rs485_mode(&sport->port); in imx_uart_probe()
2335 clk_disable_unprepare(sport->clk_ipg); in imx_uart_probe()
2339 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2340 (!sport->have_rtscts && !sport->have_rtsgpio)) in imx_uart_probe()
2341 dev_err(&pdev->dev, "no RTS control, disabling rs485\n"); in imx_uart_probe()
2344 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B) in imx_uart_probe()
2345 * signal cannot be set low during transmission in case the in imx_uart_probe()
2348 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2349 sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_probe()
2350 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && in imx_uart_probe()
2351 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) in imx_uart_probe()
2352 dev_err(&pdev->dev, in imx_uart_probe()
2353 "low-active RTS not possible when receiver is off, enabling receiver\n"); in imx_uart_probe()
2366 * In case RS485 is enabled without GPIO RTS control, the UART IP in imx_uart_probe()
2375 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2376 sport->have_rtscts && !sport->have_rtsgpio) { in imx_uart_probe()
2390 if (!imx_uart_is_imx1(sport) && sport->dte_mode) { in imx_uart_probe()
2421 clk_disable_unprepare(sport->clk_ipg); in imx_uart_probe()
2423 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2424 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2425 sport->trigger_start_tx.function = imx_trigger_start_tx; in imx_uart_probe()
2426 sport->trigger_stop_tx.function = imx_trigger_stop_tx; in imx_uart_probe()
2433 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, in imx_uart_probe()
2434 dev_name(&pdev->dev), sport); in imx_uart_probe()
2436 dev_err(&pdev->dev, "failed to request rx irq: %d\n", in imx_uart_probe()
2441 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, in imx_uart_probe()
2442 dev_name(&pdev->dev), sport); in imx_uart_probe()
2444 dev_err(&pdev->dev, "failed to request tx irq: %d\n", in imx_uart_probe()
2449 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0, in imx_uart_probe()
2450 dev_name(&pdev->dev), sport); in imx_uart_probe()
2452 dev_err(&pdev->dev, "failed to request rts irq: %d\n", in imx_uart_probe()
2457 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, in imx_uart_probe()
2458 dev_name(&pdev->dev), sport); in imx_uart_probe()
2460 dev_err(&pdev->dev, "failed to request irq: %d\n", ret); in imx_uart_probe()
2465 imx_uart_ports[sport->port.line] = sport; in imx_uart_probe()
2469 return uart_add_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_probe()
2476 uart_remove_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_remove()
2485 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_restore_context()
2486 if (!sport->context_saved) { in imx_uart_restore_context()
2487 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_restore_context()
2491 imx_uart_writel(sport, sport->saved_reg[4], UFCR); in imx_uart_restore_context()
2492 imx_uart_writel(sport, sport->saved_reg[5], UESC); in imx_uart_restore_context()
2493 imx_uart_writel(sport, sport->saved_reg[6], UTIM); in imx_uart_restore_context()
2494 imx_uart_writel(sport, sport->saved_reg[7], UBIR); in imx_uart_restore_context()
2495 imx_uart_writel(sport, sport->saved_reg[8], UBMR); in imx_uart_restore_context()
2496 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); in imx_uart_restore_context()
2497 imx_uart_writel(sport, sport->saved_reg[0], UCR1); in imx_uart_restore_context()
2498 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); in imx_uart_restore_context()
2499 imx_uart_writel(sport, sport->saved_reg[2], UCR3); in imx_uart_restore_context()
2500 imx_uart_writel(sport, sport->saved_reg[3], UCR4); in imx_uart_restore_context()
2501 sport->context_saved = false; in imx_uart_restore_context()
2502 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_restore_context()
2510 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_save_context()
2511 sport->saved_reg[0] = imx_uart_readl(sport, UCR1); in imx_uart_save_context()
2512 sport->saved_reg[1] = imx_uart_readl(sport, UCR2); in imx_uart_save_context()
2513 sport->saved_reg[2] = imx_uart_readl(sport, UCR3); in imx_uart_save_context()
2514 sport->saved_reg[3] = imx_uart_readl(sport, UCR4); in imx_uart_save_context()
2515 sport->saved_reg[4] = imx_uart_readl(sport, UFCR); in imx_uart_save_context()
2516 sport->saved_reg[5] = imx_uart_readl(sport, UESC); in imx_uart_save_context()
2517 sport->saved_reg[6] = imx_uart_readl(sport, UTIM); in imx_uart_save_context()
2518 sport->saved_reg[7] = imx_uart_readl(sport, UBIR); in imx_uart_save_context()
2519 sport->saved_reg[8] = imx_uart_readl(sport, UBMR); in imx_uart_save_context()
2520 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); in imx_uart_save_context()
2521 sport->context_saved = true; in imx_uart_save_context()
2522 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_save_context()
2538 if (sport->have_rtscts) { in imx_uart_enable_wakeup()
2556 clk_disable(sport->clk_ipg); in imx_uart_suspend_noirq()
2570 ret = clk_enable(sport->clk_ipg); in imx_uart_resume_noirq()
2584 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_suspend()
2585 disable_irq(sport->port.irq); in imx_uart_suspend()
2587 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_suspend()
2604 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_resume()
2605 enable_irq(sport->port.irq); in imx_uart_resume()
2607 clk_disable_unprepare(sport->clk_ipg); in imx_uart_resume()
2616 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_freeze()
2618 return clk_prepare_enable(sport->clk_ipg); in imx_uart_freeze()
2625 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_thaw()
2627 clk_disable_unprepare(sport->clk_ipg); in imx_uart_thaw()
2650 .name = "imx-uart",
2682 MODULE_ALIAS("platform:imx-uart");