283 static unsigned int pl011_read(const struct uart_amba_port *uap,  in pl011_read()  function
316 		status = pl011_read(uap, REG_FR);  in pl011_fifo_to_tty()
321 		ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;  in pl011_fifo_to_tty()
779 	if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {  in pl011_dma_tx_start()
1191 	while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)  in pl011_dma_shutdown()
1313 	cr = pl011_read(uap, REG_CR);  in pl011_rs485_tx_stop()
1429 	    pl011_read(uap, REG_FR) & UART01x_FR_TXFF)  in pl011_tx_char()
1444 	cr = pl011_read(uap, REG_CR);  in pl011_rs485_tx_start()
1513 	status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;  in pl011_modem_status()
1547 	pl011_read(uap, REG_ICR);  in check_apply_cts_event_workaround()
1548 	pl011_read(uap, REG_ICR);  in check_apply_cts_event_workaround()
1559 	status = pl011_read(uap, REG_RIS) & uap->im;  in pl011_int()
1583 			status = pl011_read(uap, REG_RIS) & uap->im;  in pl011_int()
1599 	unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;  in pl011_tx_empty()
1610 	unsigned int status = pl011_read(uap, REG_FR);  in pl011_get_mctrl()
1630 	cr = pl011_read(uap, REG_CR);  in pl011_set_mctrl()
1661 	lcr_h = pl011_read(uap, REG_LCRH_TX);  in pl011_break_ctl()
1677 	pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);  in pl011_quiesce_irqs()
1691 	pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,  in pl011_quiesce_irqs()
1707 	status = pl011_read(uap, REG_FR);  in pl011_get_poll_char()
1711 	return pl011_read(uap, REG_DR);  in pl011_get_poll_char()
1720 	while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)  in pl011_put_poll_char()
1755 	uap->im = pl011_read(uap, REG_IMSC);  in pl011_hwinit()
1818 		if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE)  in pl011_enable_interrupts()
1821 		pl011_read(uap, REG_DR);  in pl011_enable_interrupts()
1866 	cr = pl011_read(uap, REG_CR);  in pl011_startup()
1880 	uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;  in pl011_startup()
1921       val = pl011_read(uap, lcrh);  in pl011_shutdown_channel()
1937 	cr = pl011_read(uap, REG_CR);  in pl011_disable_uart()
2127 	old_cr = pl011_read(uap, REG_CR);  in pl011_set_termios()
2247 		u32 cr = pl011_read(uap, REG_CR);  in pl011_rs485_config()
2320 	while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)  in pl011_console_putchar()
2347 		old_cr = pl011_read(uap, REG_CR);  in pl011_console_write()
2360 	while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)  in pl011_console_write()
2376 	if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {  in pl011_console_get_options()
2379 		lcr_h = pl011_read(uap, REG_LCRH_TX);  in pl011_console_get_options()
2394 		ibrd = pl011_read(uap, REG_IBRD);  in pl011_console_get_options()
2395 		fbrd = pl011_read(uap, REG_FBRD);  in pl011_console_get_options()
2400 			if (pl011_read(uap, REG_CR)  in pl011_console_get_options()